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1 features ? incorporates the arm920t ? arm ? thumb ? processor ? 200 mips at 180 mhz, memory management unit ? 16-kbyte data cache, 16-kbyte instruction cache, write buffer ? in-circuit emulator including debug communication channel ? mid-level implementation embedded trace macrocell (256-ball bga package only) low power: 30.4 ma on vddcore, 3.1 ma in standby mode additional embedded memories ? 16k bytes of sram and 128k bytes of rom external bus interface (ebi) ? supports sdram, static memory, burst flash, glueless connection to compactflash ? , smartmedia ? and nand flash system peripherals for enhanced performance: ? enhanced clock generator and power management controller ? two on-chip oscillators with two plls ? very slow clock operating mode and software power optimization capabilities ? four programmable external clock signals ? system timer including periodic interrupt, watchdog and second counter ? real-time clock with alarm interrupt ? debug unit, two-wire uart and support for debug communication channel ? advanced interrupt controller with 8-level priority, individually maskable vectored interrupt sources, spurious interrupt protected ? seven external interrupt sources and one fast interrupt source ? four 32-bit pio controllers with up to 122 programmable i/o lines, input change interrupt and open-drain capability on each line ? 20-channel peripheral data controller (dma) ethernet mac 10/100 base-t ? media independent interface (mii) or reduced media independent interface (rmii) ? integrated 28-byte fifos and dedicated dma channels for receive and transmit usb 2.0 full speed (12 mbits per second) host double port ? dual on-chip transceivers (single port only on 208-lead pqfp package) ? integrated fifos and dedicated dma channels usb 2.0 full speed (12 mbits per second) device port ? on-chip transceiver, 2-kbyte configurable integrated fifos multimedia card interface (mci) ? automatic protocol control and fast automatic data transfers ? mmc and sd memory card-compliant, supports up to two sd memory cards three synchronous serial controllers (ssc) ? independent clock and frame sync signals for each receiver and transmitter ?i 2 s analog interface support, time division multiplex support ? high-speed continuous data stream capabilities with 32-bit data transfer four universal synchronous/asynchronous receiver/transmitters (usart) ? support for iso7816 t0/t1 smart card ? hardware and software handshaking ? rs485 support, irda up to 115 kbps ? full modem control lines on usart1 master/slave serial peripheral interface (spi) ? 8- to 16-bit programmable data length, 4 external peripheral chip selects two 3-channel, 16-bit timer/counters (tc) ? three external clock inputs, two multi-purpose i/o pins per channel ? double pwm generation, capture/waveform mode, up/down capability two-wire interface (twi) ? master mode support, all 2-wire atmel eeproms supported ieee 1149.1 jtag boundary scan on all digital pins power supplies ? 1.65v to 1.95v for vddcore, vddosc and vddpll ? 1.65v to 3.6v for vddiop (peripheral i/os) and for vddiom (memory i/os) available in a 208-lead pqfp or 256-ball bga package arm920t ? - based microcontroller AT91RM9200 rev. 1768b-atarm?08/03
2 AT91RM9200 1768b?atarm?08/03 description the AT91RM9200 is a complete system-on-chip built around the arm920t arm thumb pro- cessor. it incorporates a rich set of system and application peripherals and standard interfaces in order to provide a single-chip solution for a wide range of compute-intensive applications that require maximum functionality at minimum power consumption at lowest cost. the AT91RM9200 incorporates a high-speed on-chip sram workspace, and a low-latency external bus interface (ebi) for seamless conne ction to whatever configuration of off-chip memories and memory-mapped peripherals is required by the application. the ebi incorpo- rates controllers for synchronous dram (sdram), burst flash and static memories and features specific circuitry facilitating the interface for smartmedia, compactflash and nand flash. the advanced interrupt controller (aic) enhances the interrupt handling performance of the arm920t processor by providing multiple vectored, prioritized interrupt sources and reducing the time taken to transfer to an interrupt handler. the peripheral data controller (pdc) provides dma channels for all the serial peripherals, enabling them to transfer data to or from on- and off-chip memories without processor inter- vention. this reduces the processor overhead when dealing with transfers of continuous data streams.the AT91RM9200 benefits from a new generation of pdc which includes dual point- ers that simplify significantly buffer chaining. the set of parallel i/o (pio) controllers multiplex the peripheral input/output lines with general- purpose data i/os for maximum flexibility in dev ice configuration. an input change interrupt, open drain capability and programmable pull-up resistor is included on each line. the power management controller (pmc) keeps system power consumption to a minimum by selectively enabling/disabling the processor and various peripherals under software control. it uses an enhanced clock generator to provide a se lection of clock signals including a slow clock (32 khz) to optimize power consumption and performance at all times. the AT91RM9200 integrates a wide range of standard interfaces including usb 2.0 full speed host and device and ethernet 10/100 base-t media access controller (mac), which provides connection to a extensive range of external peripheral devices and a widely used net- working layer. in addition, it provides an extensive set of peripherals that operate in accordance with several industry standards, such as those used in audio, telecom, flash card, infrared and smart card applications. to complete the offer, the AT91RM9200 benefits from the integration of a wide range of debug features including jtag-ice, a dedicated uart debug channel (dbgu) and an embedded real time trace. this enables the development and debug of all applications, especially those with real-time constraints.
3 AT91RM9200 1768b?atarm?08/03 block diagram bold arrows ( ) indicate master-to-slave dependency. figure 1. AT91RM9200 block diagram arm920t core jtag scan ice aic fast sram 16k bytes pio pllb plla osc pmc system timer osc rtc ebi pioa/piob/pioc/piod controller dbgu mci usart0 usart1 usart2 usart3 spi ssc0 ssc1 ssc2 timer counter tc0 tc1 tc2 timer counter tc3 tc4 tc5 twi pio pio d0-d15 a0/nbs0 a1/nbs2/nwr2 a2-a15/a18-a22 a16/ba0 a17/ba1 ncs0/bfcs ncs1/sdcs ncs3/smcs nrd/noe/cfoe nwr0/nwe/cfwe nwr1/nbs1/cfior nwr3/nbs3/cfiow sdck sdcke ras-cas sdwe sda10 bfrdy/smoe bfck bfavd bfbaa/smwe bfoe bfwe a23-a24 ncs5/cfce1 d16-d31 tf0 tk0 td0 rd0 rk0 rf0 tf1 tk1 td1 rd1 rk1 rf1 tf2 tk2 td2 rd2 rk2 rf2 tclk0 tclk1 tclk2 tioa0 tiob0 tioa1 tiob1 tioa2 tiob2 tclk3 tclk4 tclk5 tioa3 tiob3 tioa4 tiob4 tioa5 tiob5 twd twck jtagsel tdi tdo tms tck ntrst fiq irq0-irq6 pck0-pck3 pllrcb pllrca xin xout xin32 xout32 ddm ddp mcck mccda mcda0-mcda3 mccdb rxd0 txd0 sck0 rts0 cts0 rxd1 txd1 sck1 rts1 cts1 dsr1 dtr1 dcd1 ri1 rxd2 txd2 sck2 rts2 cts2 rxd3 txd3 sck3 rts3 cts3 npcs0 npcs1 npcs2 npcs3 miso mosi spck mcdb0-mcdb3 hdma hdpb hdpa hdmb drxd dtxd ethernet mac 10/100 etxck-erxck-erefck etxen-etxer ecrs-ecol erxer-erxdv erx0-erx3 etx0-etx3 emdc sdram controller burst flash controller static memory controller pio instruction cache 16k bytes data cache 16k bytes mmu emdio dma fifo dma fifo usb host fifo usb device transceiver pio pio pio reset and test tst0-tst1 nrst apb fast rom 128k bytes bms ncs2 a25/cfrnw ncs4/cfcs misalignment detector address decoder abort status ncs6/cfce2 transceiver ncs7 memory controller bus arbiter peripheral bridge peripheral data controller ef100 etm tsync tclk tps0 - tps2 tpk0 - tpk15 compactflash smartmedia nand flash pdc pdc pdc pdc pdc pdc pdc pdc pdc pdc pdc pdc
4 AT91RM9200 1768b?atarm?08/03 key features this section presents the key features of each block. arm920t processor arm9tdmi ? -based on arm ? architecture v4t two instruction sets ?arm ? high-performance 32-bit instruction set ? thumb ? high code density 16-bit instruction set 5-stage pipeline architecture: ? instruction fetch (f) ? instruction decode (d) ?execute (e) ? data memory (m) ? register write (w) 16-kbyte data cache, 16-kbyte instruction cache ? virtually-addressed 64-way associative cache ?8 words per line ? write-though and write-back operation ? pseudo-random or round-robin replacement ? low-power cam ram implementation write buffer ? 16-word data buffer ? 4-address address buffer ? software control drain standard armv4 memory management unit (mmu) ? access permission for sections ? access permission for large pages and small pages can be specified separately for each quarter of the pages ? 16 embedded domains ? 64 entry instruction tlb and 64 entry data tlb 8-, 16-, 32-bit data bus for instructions and data debug and test integrated embedded in-circuit-emulator debug unit ?two-pin uart ? debug communication channel ? chip id register embedded trace macrocell: etm9 rev2a ? medium level implementation ? half-rate clock mode ? four pairs of address comparators ? two data comparators ? eight memory map decoder inputs ? two counters ? one sequencer ? one 18-byte fifo
5 AT91RM9200 1768b?atarm?08/03 ieee1149.1 jtag boundary scan on all digital pins boot program default boot program stored in rom-based products downloads and runs an application from external storage media into internal sram downloaded code size depends on embedded sram size automatic detection of valid application bootloader supporting a wide range of non-volatile memories ? spi dataflash ? connected on spi npcs0 ? two-wire eeprom ? 8-bit parallel memories on ncs0 if device integrates ebi boot uploader in case no valid program is detected in external nvm and supporting several communication media serial communication on a dbgu (xmodem protocol) usb device port (dfu protocol) embedded software services compliant with atpcs compliant with ainsi/iso standard c compiled in arm/thumb interworking rom entry service tempo, xmodem and dataflash services crc and sine tables reset controller two reset input lines (nrst and ntrst) providing, respectively: initialization of the user interface registers (defined in the user interface of each peripheral) and: ? sample the signals needed at bootup ? compel the processor to fetch the next instruction at address zero. initialization of the embedded ice tap controller. memory controller programmable bus arbiter handling four masters ? internal bus is shared by arm920t, pdc, usb host port and ethernet mac masters ? each master can be assigned a priority between 0 and 7 address decoder provides selection for ? eight external 256-mbyte memory areas ? four internal 1-mbyte memory areas ? one 256-mbyte embedded peripheral area boot mode select option ? non-volatile boot memory can be internal or external ? selection is made by bms pin sampled at reset abort status registers ? source, type and all parameters of the access leading to an abort are saved misalignment detector ? alignment checking of all data accesses
6 AT91RM9200 1768b?atarm?08/03 ? abort generation in case of misalignment remap command ? provides remapping of an internal sram in place of the boot nvm external bus interface integrates three external memory controllers: ? static memory controller ? sdram controller ? burst flash controller additional logic for smartmedia tm and compactflash tm support optimized external bus: ? 16- or 32-bit data bus ? up to 26-bit address bus, up to 64-mbytes addressable ? up to 8 chip selects, each reserved to one of the eight memory areas ? optimized pin multiplexing to reduce latencies on external memories configurable chip select assignment: ? burst flash controller or static memory controller on ncs0 ? sdram controller or static memory controller on ncs1 ? static memory controller on ncs3, optional smartmedia support ? static memory controller on ncs4 - ncs6, optional compactflash support ? static memory controller on ncs7 static memory controller external memory mapping, 512-mbyte address space up to 8 chip select lines 8- or 16-bit data bus remap of boot memory multiple access modes supported ? byte write or byte select lines ? two different read protocols for each memory bank multiple device adaptability ? compliant with lcd module ? programmable setup time read/write ? programmable hold time read/write multiple wait state management ? programmable wait state generation ? external wait request ? programmable data float time sdram controller numerous configurations supported ? 2k, 4k, 8k row address memory parts ? sdram with two or four internal banks ? sdram with 16- or 32-bit data path programming facilities ? word, half-word, byte access ? automatic page break when memory boundary has been reached
7 AT91RM9200 1768b?atarm?08/03 ? multibank ping-pong access ? timing parameters specified by software ? automatic refresh operation, refresh rate is programmable energy-saving capabilities ? self-refresh and low-power modes supported error detection ? refresh error interrupt sdram power-up initialization by software latency is set to two clocks (cas latency of 1, 3 not supported) auto precharge command not used burst flash controller multiple access modes supported ? asynchronous or burst mode byte, half-word or word read accesses ? asynchronous mode half-word write accesses adaptability to different device speed grades ? programmable burst flash clock rate ? programmable data access time ? programmable latency after output enable adaptability to different device access protocols and bus interfaces ? two burst read protocols: clock control address advance or signal controlled address advance ? multiplexed or separate address and data buses ? continuous burst and page mode accesses supported peripheral data controller generates transfers to/from peripherals such as dbgu, usart, ssc, spi and mci twenty channels one master clock cycle needed for a transfer from memory to peripheral two master clock cycles needed for a transfer from peripheral to memory advanced interrupt controller controls the interrupt lines (nirq and nfiq) of an arm ? processor thirty-two individually maskable and vectored interrupt sources ? source 0 is reserved for the fast interrupt input (fiq) ? source 1 is reserved for system peripherals (st, rtc, pmc, dbgu?) ? source 2 to source 31 control thirty embedded peripheral interrupts or external interrupts ? programmable edge-triggered or level-sensitive internal sources ? programmable positive/negative edge-triggered or high/low level-sensitive external sources 8-level priority controller ? drives the normal interrupt of the processor ? handles priority of the interrupt sources 1 to 31 ? higher priority interrupts can be served during service of lower priority interrupt vectoring ? optimizes interrupt service routine branch and execution
8 AT91RM9200 1768b?atarm?08/03 ? one 32-bit vector register per interrupt source ? interrupt vector register reads the corresponding current interrupt vector protect mode ? easy debugging by preventing automatic operations fast forcing ? permits redirecting any normal interrupt source on the fast interrupt of the processor general interrupt mask ? provides processor synchronization on events without triggering an interrupt power management controller optimizes the power consumption of the whole system embeds and controls: ? one main oscillator and one slow clock oscillator (32.768hz) ? two phase locked loops (plls) and dividers ?clock prescalers provides: ? the processor clock pck ? the master clock mck ? the usb clocks, uhpck and udpck, respectively for the usb host port and the usb device port ? programmable automatic pll switch-off in usb device suspend conditions ? up to thirty peripheral clocks ? four programmable clock outputs pck0 to pck3 four operating modes: ? normal mode, idle mode, slow clock mode, standby mode system timer one period interval timer, 16-bit programmable counter one watchdog timer, 16-bit programmable counter one real-time timer, 20-bit free-running counter interrupt generation on event real time clock low power consumption full asynchronous design two hundred year calendar programmable periodic interrupt alarm and update parallel load control of alarm and update time/calendar data in debug unit system peripheral to facilitate debug of atmel?s arm ? -based systems composed of four functions ?two-pin uart ? debug communication channel (dcc) support ? chip id registers ? ice access prevention
9 AT91RM9200 1768b?atarm?08/03 two-pin uart ? implemented features are 100% compatible with the standard atmel usart ? independent receiver and transmitter with a common programmable baud rate generator ? even, odd, mark or space parity generation ? parity, framing and overrun error detection ? automatic echo, local loopback and remote loopback channel modes ? interrupt generation ? support for two pdc channels with connection to receiver and transmitter debug communication channel support ? offers visibility of commrx and commtx signals from the arm processor ? interrupt generation chip id registers ? identification of the device revision, sizes of the embedded memories, set of peripherals pio controller up to 32 programmable i/o lines fully programmable through set/clear registers multiplexing of two peripheral functions per i/o line for each i/o line (whether assigned to a peripheral or used as general purpose i/o) ? input change interrupt ? glitch filter ? multi-drive option enables driving in open drain ? programmable pull up on each i/o line ? pin data status register, supplies visibility of the level on the pin at any time synchronous output, provides set and clear of several i/o lines in a single write usb host port compliance with open hci rev 1.0 specification compliance with usb v2.0 full-speed and low-speed specification supports both low-speed 1.5 mbps and full-speed 12 mbps usb devices root hub integrated with two downstream usb ports two embedded usb transceivers supports power management operates as a master on the memory controller usb device port usb v2.0 full-speed compliant, 12 mbits per second embedded usb v2.0 full-speed transceiver embedded dual-port ram for endpoints suspend/resume logic ping-pong mode (two memory banks) for isochronous and bulk endpoints six general-purpose endpoints ? endpoint 0, endpoint 3: 8 bytes, no ping-pong mode ? endpoint 1, endpoint 2: 64 bytes, ping-pong mode ? endpoint 4, endpoint 5: 256 bytes, ping-pong mode
10 AT91RM9200 1768b?atarm?08/03 ethernet mac compatibility with ieee standard 802.3 10 and 100 mbits per second data throughput capability full- and half-duplex operation mii or rmii interface to the physical layer register interface to address, status and control registers dma interface, operating as a master on the memory controller interrupt generation to signal receive and transmit completion 28-byte transmit and 28-byte receive fifos automatic pad and crc generation on transmitted frames address checking logic to recognize four 48-bit addresses supports promiscuous mode where all valid frames are copied to memory supports physical layer management through mdio interface control of alarm and update time/calendar data in serial peripheral interface supports communication with serial external devices ? four chip selects with external decoder support allow communication with up to 15 peripherals ? serial memories, such as dataflash and 3-wire eeproms ? serial peripherals, such as adcs, dacs, lcd controllers, can controllers and sensors ? external co-processors master or slave serial peripheral bus interface ? 8- to 16-bit programmable data length per chip select ? programmable phase and polarity per chip select ? programmable transfer delays between consecutive transfers and between clock and data per chip select ? programmable delay between consecutive transfers ? selectable mode fault detection connection to pdc channel optimizes data transfers ? one channel for the receiver, one channel for the transmitter ? next buffer support two-wire interface compatibility with standard two-wire serial memory one, two or three bytes for slave address sequential read/write operations usart programmable baud rate generator 5- to 9-bit full-duplex synchronous or asynchronous serial communications ? 1, 1.5 or 2 stop bits in asynchronous mode or 1 or 2 stop bits in synchronous mode ? parity generation and error detection ? framing error detection, overrun error detection ? msb- or lsb-first ? optional break generation and detection
11 AT91RM9200 1768b?atarm?08/03 ? by 8 or by-16 over-sampling receiver frequency ? optional hardware handshaking rts-cts ? optional modem signal management dtr-dsr-dcd-ri ? receiver time-out and transmitter timeguard ? optional multi-drop mode with address generation and detection rs485 with driver control signal iso7816, t = 0 or t = 1 protocols for interfacing with smart cards ? nack handling, error counter with repetition and iteration limit irda modulation and demodulation ? communication at up to 115.2 kbps test modes ? remote loopback, local loopback, automatic echo connection of two peripheral data controller channels (pdc) ? offers buffer transfer without processor intervention serial synchronous controller provides serial synchronous communication links used in audio and telecom applications contains an independent receiver and transmitter and a common clock divider interfaced with two pdc channels (dma access) to reduce processor overhead offers a configurable frame sync and data length receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal receiver and transmitter include a data signal, a clock signal and a frame synchronization signal timer counter three 16-bit timer counter channels wide range of functions including: ? frequency measurement ? event counting ? interval measurement ? pulse generation ?delay timing ? pulse width modulation ? up/down capabilities each channel is user-configurable and contains: ? three external clock inputs ? five internal clock inputs ? two multi-purpose input/output signals internal interrupt signal two global registers that act on all three tc channels multimedia card interface compatibility with multimedia card specification version 2.2 compatibility with sd memory card specification version 1.0 cards clock rate up to master clock divided by 2 embedded power management to slow down clock rate when not used
12 AT91RM9200 1768b?atarm?08/03 supports two slots ? one slot for one multimediacard bus (up to 30 cards) or one sd memory card support for stream, block and multi-block data read and write connection to a peripheral data controller channel ? minimizes processor intervention for large buffer transfers
13 AT91RM9200 1768b?atarm?08/03 AT91RM9200 product properties power supplies the AT91RM9200 has five types of power supply pins: vddcore pins. they power the core, including processor, memories and peripherals; voltage ranges from 1.65v to 1.95v, 1.8v nominal. vddiom pins. they power the external bus interface i/o lines; voltage ranges from 1.65v to 3.6v, 1.8v, 3v or 3.3v nominal. vddiop pins. they power the peripheral i/o lines and the usb transceivers; voltage ranges from 1.65v to 3.6v, 1.8v, 3v or 3.3v nominal. (1) vddpll pins. they power the pll cells; voltage ranges from 1.65v to 1.95v, 1.8v nominal. vddosc pin. they power both oscillators; voltage ranges from 1.65v to 1.95v, 1.8v nominal. note: 1. powering vddiop with a voltage lower than 3v prevents any use of the usb host and device ports. this also affects the operation of the trace port. the double power supplies vddiom and vddiop are identified in table 1 on page 14 and table 2 on page 16. these supplies enable the user to power the device differently for inter- facing with memories and for interfacing with peripherals. ground pins are common to all power supplies, except vddpll and vddosc pins. for these pins, gndpll and gndosc are provided, respectively. pinout the AT91RM9200 is available in two packages: 208-lead pqfp, 31.2 x 31.2 mm, 0.5 mm lead pitch 256-ball bga, 15 x 15 mm, 0.8 mm ball pitch the product features of the 256-ball bga package are extended compared to the 208-lead pqfp package. the features that are available only with the 256-ball bga package are: parallel i/o controller d etm port with outputs multiplexed on the pio controller d a second usb host transceiver, opening the hub capabilities of the embedded usb host.
14 AT91RM9200 1768b?atarm?08/03 208-lead pqfp package pinout table 1. AT91RM9200 pinout for 208-lead pqfp package pin number signal name pin number signal name pin number signal name pin number signal name 1 pc24 37 vddpll 73 pa27 109 tms 2 pc25 38 pllrcb 74 pa28 110 ntrst 3 pc26 39 gndpll 75 vddiop 111 vddiop 4 pc27 40 vddiop 76 gnd 112 gnd 5 pc28 41 gnd 77 pa29 113 tst0 6 pc29 42 pa0 78 pa30 114 tst1 7 vddiom 43 pa1 79 pa31/bms 115 nrst 8 gnd 44 pa2 80 pb0 116 vddcore 9 pc30 45 pa3 81 pb1 117 gnd 10 pc31 46 pa4 82 pb2 118 pb23 11 pc10 47 pa5 83 pb3 119 pb24 12 pc11 48 pa6 84 pb4 120 pb25 13 pc12 49 pa7 85 pb5 121 pb26 14 pc13 50 pa8 86 pb6 122 pb27 15 pc14 51 pa9 87 pb7 123 pb28 16 pc15 52 pa10 88 pb8 124 pb29 17 pc0 53 pa11 89 pb9 125 hdma 18 pc1 54 pa12 90 pb10 126 hdpa 19 vddcore 55 pa13 91 pb11 127 ddm 20 gnd 56 vddiop 92 pb12 128 ddp 21 pc2 57 gnd 93 vddiop 129 vddiop 22 pc3 58 pa14 94 gnd 130 gnd 23 pc4 59 pa15 95 pb13 131 vddiom 24 pc5 60 pa16 96 pb14 132 gnd 25 pc6 61 pa17 97 pb15 133 a0/nbs0 26 vddiom 62 vddcore 98 pb16 134 a1/nbs2/nwr2 27 gnd 63 gnd 99 pb17 135 a2 28 vddpll 64 pa18 100 pb18 136 a3 29 pllrca 65 pa19 101 pb19 137 a4 30 gndpll 66 pa20 102 pb20 138 a5 31 xout 67 pa21 103 pb21 139 a6 32 xin 68 pa22 104 pb22 140 a7 33 vddosc 69 pa23 105 jtagsel 141 a8 34 gndosc 70 pa24 106 tdi 142 a9 35 xout32 71 pa25 107 tdo 143 a10 36 xin32 72 pa26 108 tck 144 sda10
15 AT91RM9200 1768b?atarm?08/03 note: 1. shaded cells define the pins powered by vddiom. mechanical overview of the 208-lead pqfp package figure 2 shows the orientation of the 208-lead pqfp package. a detailed mechanical description is given in the section mechanical characteristics. figure 2. 208-lead pqfp pinout (top view) 145 a11 161 pc7 177 cas 193 d10 146 vddiom 162 pc8 178 sdwe 194 d11 147 gnd 163 pc9 179 d0 195 d12 148 a12 164 vddiom 180 d1 196 d13 149 a13 165 gnd 181 d2 197 d14 150 a14 166 ncs0/bfcs 182 d3 198 d15 151 a15 167 ncs1/sdcs 183 vddiom 199 vddiom 152 vddcore 168 ncs2 184 gnd 200 gnd 153 gnd 169 ncs3/smcs 185 d4 201 pc16 154 a16/ba0 170 nrd/noe/cfoe 186 d5 202 pc17 155 a17/ba1 171 nwr0/nwe/cfwe 187 d6 203 pc18 156 a18 172 nwr1/nbs1/cfior 188 vddcore 204 pc19 157 a19 173 nwr3/nbs3/cfiow 189 gnd 205 pc20 158 a20 174 sdck 190 d7 206 pc21 159 a21 175 sdcke 191 d8 207 pc22 160 a22 176 ras 192 d9 208 pc23 table 1. AT91RM9200 pinout for 208-lead pqfp package (continued) pin number signal name pin number signal name pin number signal name pin number signal name 152 53 104 105 156 157 208
16 AT91RM9200 1768b?atarm?08/03 256-ball bga package pinout table 2. AT91RM9200 pinout for 256-ball bga package pin signal name pin signal name pin signal name pin signal name a1 tdi c3 pd14 e5 tck g14 pa1 a2 jtagsel c4 pb22 e6 gnd g15 pa2 a3 pb20 c5 pb19 e7 pb15 g16 pa3 a4 pb17 c6 pd10 e8 gnd g17 xin32 a5 pd11 c7 pb13 e9 pb7 h1 pd23 a6 pd8 c8 pb12 e10 pb3 h2 pd20 a7 vddiop c9 pb6 e11 pa29 h3 pd22 a8 pb9 c10 pb1 e12 pa26 h4 pd21 a9 pb4 c11 gnd e13 pa25 h5 vddiop a10 pa31/bms c12 pa20 e14 pa9 h13 vddpllb a11 vddiop c13 pa18 e15 pa6 h14 vddiop a12 pa23 c14 vddcore e16 pd3 h15 gndpllb a13 pa19 c15 gnd e17 pd0 h16 gnd a14 gnd c16 pa8 f1 pd16 h17 xout32 a15 pa14 c17 pd5 f2 gnd j1 pd25 a16 vddiop d1 tst1 f3 pb23 j2 pd27 a17 pa13 d2 vddiop f4 pb25 j3 pd24 b1 tdo d3 vddiop f5 pb24 j4 pd26 b2 pd13 d4 gnd f6 vddcore j5 pb28 b3 pb18 d5 vddiop f7 pb16 j6 pb29 b4 pb21 d6 pd7 f9 pb11 j12 gnd b5 pd12 d7 pb14 f11 pa30 j13 gndosc b6 pd9 d8 vddiop f12 pa28 j14 vddosc b7 gnd d9 pb8 f13 pa4 j15 vddplla b8 pb10 d10 pb2 f14 pd2 j16 gndplla b9 pb5 d11 gnd f15 pd1 j17 xin b10 pb0 d12 pa22 f16 pa5 k1 hdpa b11 vddiop d13 pa21 f17 pllrcb k2 ddm b12 pa24 d14 pa16 g1 pd19 k3 hdma b13 pa17 d15 pa10 g2 pd17 k4 vddiop b14 pa15 d16 pd6 g3 gnd k5 ddp b15 pa11 d17 pd4 g4 pb26 k13 pc5 b16 pa12 e1 nrst g5 pd18 k14 pc4 b17 pa7 e2 ntrst g6 pb27 k15 pc6 c1 tms e3 gnd g12 pa27 k16 vddiom c2 pd15 e4 tst0 g13 pa0 k17 xout
17 AT91RM9200 1768b?atarm?08/03 note: 1. shaded cells define the pins powered by vddiom. l1 gnd n2 a5 p13 d15 t7 nwr1/nbs1/ cfior l2 hdpb n3 a9 p14 pc26 t8 sdwe l3 hdmb n4 a4 p15 pc27 t9 gnd l4 a6 n5 a14 p16 vddiom t10 vddcore l5 gnd n6 sda10 p17 gnd t11 d9 l6 vddiop n7 a8 r1 gnd t12 d12 l12 pc10 n8 a21 r2 gnd t13 gnd l13 pc15 n9 nrd/noe/cfoe r3 a18 t14 pc19 l14 pc2 n10 ras r4 a20 t15 pc21 l15 pc3 n11 d2 r5 pc8 t16 pc23 l16 vddcore n12 gnd r6 vddiom t17 pc25 l17 pllrca n13 pc28 r7 ncs3/smcs u1 vddcore m1 vddiom n14 pc31 r8 nwr3/nbs3/ cfiow u2 gnd m2 gnd n15 pc30 r9 d0 u3 a16/ba0 m3 a3 n16 pc11 r10 vddiom u4 a19 m4 a1/nbs2/nwr2 n17 pc12 r11 d8 u5 gnd m5 a10 p1 a7 r12 d13 u6 ncs0/bfcs m6 a2 p2 a13 r13 pc17 u7 sdck m7 gnd p3 a12 r14 vddiom u8 cas m9 ncs1/sdcs p4 vddiom r15 pc24 u9 d3 m11 d4 p5 a11 r16 pc29 u10 d6 m12 gnd p6 a22 r17 vddiom u11 d7 m13 pc13 p7 pc9 t1 a15 u12 d11 m14 pc1 p8 nwr0/nwe/cfwe t2 vddcore u13 d14 m15 pc0 p9 sdcke t3 a17/ba1 u14 pc16 m16 gnd p10 d1 t4 pc7 u15 pc18 m17 pc14 p11 d5 t5 vddiom u16 pc20 n1 a0/nbs0 p12 d10 t6 ncs2 u17 pc22 table 2. AT91RM9200 pinout for 256-ball bga package (continued) pin signal name pin signal name pin signal name pin signal name
18 AT91RM9200 1768b?atarm?08/03 mechanical overview of the 256-ball bga package figure 3 on page 18 shows the orientation of the 256-ball bga package. a detailed mechanical description is given in the section mechanical characteristics. figure 3. 256-ball bga pinout (top view) peripheral multiplexing on pio lines the AT91RM9200 features four pio controllers: pioa and piob, multiplexing i/o lines of the peripheral set. pioc, multiplexing the data bus bits 16 to 31 and several external bus interface control signals. using pioc pins increases the number of general-purpose i/o lines available but prevents 32-bit memory access. piod, available in the 256-ball bga package option only, multiplexing outputs of the peripheral set and the etm port. each pio controller controls up to 32 lines. each line can be assigned to one of two peripheral functions, a or b. the tables in the following paragraphs define how the i/o lines of the periph- erals a and b are multiplexed on the pio controllers a, b, c and d. the two columns ?function? and ?comments? have been inserted for the user?s own comments; they may be used to track how pins are defined in an application. the column ?reset state? indicates whether the pio line resets in i/o mode or in peripheral mode. if equal to ?i/o?, the pio line resets in input with the pull-up enabled so that the device is maintained in a static state as soon as the nrst pin is asserted. as a result, the bit corre- sponding to the pio line in the register pio_psr (peripheral status register) resets low. if a signal name is in the ?reset state? column, the pio line is assigned to this function and the corresponding bit in pio_psr resets high. this is the case for pins controlling memories, either address lines or chip selects, and that require the pin to be driven as soon as nrst raises. note that the pull-up resistor is also enabled in this case. see table 3 on page 19, table 4 on page 20, table 5 on page 21 and table 6 on page 22.
19 AT91RM9200 1768b?atarm?08/03 pio controller a multiplexing table 3. multiplexing on pio controller a pio controller a application usage i/o line peripheral a peripheral b reset state function comments pa0 miso pck3 i/o pa1 mosi pck0 i/o pa2 spck irq4 i/o pa3 npcs0 irq5 i/o pa4 npcs1 pck1 i/o pa5 npcs2 txd3 i/o pa6 npcs3 rxd3 i/o pa7 etxck/erefck pck2 i/o pa8 etxen mccdb i/o pa9 etx0 mcdb0 i/o pa10 etx1 mcdb1 i/o pa11 ecrs/ecrsdv mcdb2 i/o pa12 erx0 mcdb3 i/o pa13 erx1 tclk0 i/o pa14 erxer tclk1 i/o pa15 emdc tclk2 i/o pa16 emdio irq6 i/o pa17 txd0 tioa0 i/o pa18 rxd0 tiob0 i/o pa19 sck0 tioa1 i/o pa20 cts0 tiob1 i/o pa21 rts0 tioa2 i/o pa22 rxd2 tiob2 i/o pa23 txd2 irq3 i/o pa24 sck2 pck1 i/o pa25 twd irq2 i/o pa26 twck irq1 i/o pa27 mcck tclk3 i/o pa28 mccda tclk4 i/o pa29 mcda0 tclk5 i/o pa30 drxd cts2 i/o pa31 dtxd rts2 i/o
20 AT91RM9200 1768b?atarm?08/03 pio controller b multiplexing table 4. multiplexing on pio controller b pio controller b application usage i/o line peripheral a peripheral b reset state function comments pb0 tf0 rts3 i/o pb1 tk0 cts3 i/o pb2 td0 sck3 i/o pb3 rd0 mcda1 i/o pb4 rk0 mcda2 i/o pb5 rf0 mcda3 i/o pb6 tf1 tioa3 i/o pb7 tk1 tiob3 i/o pb8 td1 tioa4 i/o pb9 rd1 tiob4 i/o pb10 rk1 tioa5 i/o pb11 rf1 tiob5 i/o pb12 tf2 etx2 i/o pb13 tk2 etx3 i/o pb14 td2 etxer i/o pb15 rd2 erx2 i/o pb16 rk2 erx3 i/o pb17 rf2 erxdv i/o pb18 ri1 ecol i/o pb19 dtr1 erxck i/o pb20 txd1 i/o pb21 rxd1 i/o pb22 sck1 i/o pb23 dcd1 i/o pb24 cts1 i/o pb25 dsr1 ef100 i/o pb26 rts1 i/o pb27 pck0 i/o pb28 fiq i/o pb29 irq0 i/o
21 AT91RM9200 1768b?atarm?08/03 pio controller c multiplexing the pio controller c has no multiplexing and only peripheral a lines are used. selecting peripheral b on the pio controller c has no effect. table 5. multiplexing on pio controller c pio controller c application usage i/o line peripheral a peripheral b reset state function comments pc0 bfck i/o pc1 bfrdy/smoe i/o pc2 bfavd i/o pc3 bfbaa/smwe i/o pc4 bfoe i/o pc5 bfwe i/o pc6 nwait i/o pc7 a23 a23 pc8 a24 a24 pc9 a25/cfrnw a25 pc10 ncs4/cfcs ncs4 pc11 ncs5/cfce1 ncs5 pc12 ncs6/cfce2 ncs6 pc13 ncs7 ncs7 pc14 i/o pc15 i/o pc16 d16 i/o pc17 d17 i/o pc18 d18 i/o pc19 d19 i/o pc20 d20 i/o pc21 d21 i/o pc22 d22 i/o pc23 d23 i/o pc24 d24 i/o pc25 d25 i/o pc26 d26 i/o pc27 d27 i/o pc28 d28 i/o pc29 d29 i/o pc30 d30 i/o pc31 d31 i/o
22 AT91RM9200 1768b?atarm?08/03 pio controller d multiplexing the pio controller d multiplexes pure output signals on peripheral a connections, in particular from the emac rmii inter- face and the etm port on the peripheral b connections. the pio controller d is available only in the 256-ball bga package option of the AT91RM9200. table 6. multiplexing on pio controller d pio controller d application usage i/o line peripheral a peripheral b reset state function comments pd0 etx0 i/o pd1 etx1 i/o pd2 etx2 i/o pd3 etx3 i/o pd4 etxen i/o pd5 etxer i/o pd6 dtxd i/o pd7 pck0 tsync i/o pd8 pck1 tclk i/o pd9 pck2 tps0 i/o pd10 pck3 tps1 i/o pd11 tps2 i/o pd12 tpk0 i/o pd13 tpk1 i/o pd14 tpk2 i/o pd15 td0 tpk3 i/o pd16 td1 tpk4 i/o pd17 td2 tpk5 i/o pd18 npcs1 tpk6 i/o pd19 npcs2 tpk7 i/o pd20 npcs3 tpk8 i/o pd21 rts0 tpk9 i/o pd22 rts1 tpk10 i/o pd23 rts2 tpk11 i/o pd24 rts3 tpk12 i/o pd25 dtr1 tpk13 i/o pd26 tpk14 i/o pd27 tpk15 i/o
23 AT91RM9200 1768b?atarm?08/03 pin name description table 7 gives details on the pin name classified by peripheral. table 7. pin description list pin name function type active level comments power vddiom memory i/o lines power supply power 1.65v to 3.6v vddiop peripheral i/o lines power supply power 1.65v to 3.6v vddpll oscillator and pll power supply power 1.65v to 1.95v vddcore core chip power supply power 1.65v to 1.95v vddosc oscillator power supply power 1.65v to 1.95v gnd ground ground gndpll pll ground ground gndosc oscillator ground ground clocks, oscillators and plls xin main crystal input input xout main crystal output output xin32 32khz crystal input input xout32 32khz crystal output output pllrca pll a filter input pllrcb pll b filter input pck0 - pck3 programmable clock output output ice and jtag tck test clock input tdi test data in input tdo test data out output tms test mode select input ntrst test reset signal input low jtagsel jtag selection input etm tsync trace synchronization signal output tclk trace clock output tps0 - tps2 trace arm pipeline status output tpk0 - tpk15 trace packet port output reset/test nrst microcontroller reset input low no on-chip pull-up tst0 - tst1 test mode select input must be tied low for normal operation
24 AT91RM9200 1768b?atarm?08/03 memory controller bms boot mode select input debug unit drxd debug receive data input debug receive data dtxd debug transmit data output debug transmit data aic irq0 - irq6 external interrupt inputs input fiq fast interrupt input input pio pa0 - pa31 parallel io controller a i/o pulled-up input at reset pb0 - pb29 parallel io controller b i/o pulled-up input at reset pc0 - pc31 parallel io controller c i/o pulled-up input at reset pd0 - pd27 parallel io controller d i/o pulled-up input at reset ebi d0 - d15 data bus i/o pulled-up input at reset d16 - d31 data bus i/o pulled-up input at reset a0 - a25 address bus output 0 at reset smc ncs0 - ncs7 chip select lines output low 1 at reset nwr0 - nwr3 write signal output low 1 at reset noe output enable output low 1 at reset nrd read signal output low 1 at reset nub upper byte select output low 1 at reset nlb lower byte select output low 1 at reset nwe write enable output low 1 at reset nbs0 - nbs3 byte mask signal output low 1 at reset ebi for compactflash support cfce1 - cfce2 compactflash chip enable output low cfoe compactflash output enable output low cfwe compactflash write enable output low cfior compactflash io read output low cfiow compactflash io write output low table 7. pin description list (continued) pin name function type active level comments
25 AT91RM9200 1768b?atarm?08/03 cfrnw compactflash read not write output cfcs compactflash chip select output low ebi for smartmedia support smcs smartmedia chip select output low smoe smartmedia output enable output low smwe smartmedia write enable output low sdram controller sdck sdram clock output sdcke sdram clock enable output high sdcs sdram controller chip select output low ba0 - ba1 bank select output sdwe sdram write enable output low ras - cas row and column signal output low sda10 sdram address 10 line output burst flash controller bfck burst flash clock output bfcs burst flash chip select output low bfavd burst flash address valid output low bfbaa burst flash address advance output low bfoe burst flash output enable output low bfrdy burst flash ready input high bfwe burst flash write enable output low multimedia card interface mcck multimedia card clock output mccda multimedia card a command i/o mcda0 - mcda3 multimedia card a data i/o mccdb multimedia card b command i/o mcdb0 - mcdb3 multimedia card b data i/o usart sck0 - sck3 serial clock i/o txd0 - txd3 transmit data output rxd0 - rxd3 receive data input rts0 - rts3 ready to send output cts0 - cts3 clear to send input dsr1 data set ready input table 7. pin description list (continued) pin name function type active level comments
26 AT91RM9200 1768b?atarm?08/03 dtr1 data terminal ready output dcd1 data carrier detect input ri1 ring indicator input usb device port ddm usb device port data - analog ddp usb device port data + analog usb host port hdma usb host port a data - analog hdpa usb host port a data + analog hdmb usb host port b data - analog hdpb usb host port b data + analog ethernet mac erefck reference clock input rmii only etxck transmit clock input mii only erxck receive clock input mii only etxen transmit enable output etx0 - etx3 transmit data output etx0 - etx1 only in rmii etxer transmit coding error output mii only erxdv receive data valid input mii only ecrsdv carrier sense and data valid input rmii only erx0 - erx3 receive data input erx0 - erx1 only in rmii erxer receive error input ecrs carrier sense input mii only ecol collision detected input mii only emdc management data clock output emdio management data input/output i/o ef100 force 100 mbits/sec. output high rmii only synchronous serial controller td0 - td2 transmit data output rd0 - rd2 receive data input tk0 - tk2 transmit clock i/o rk0 - rk2 receive clock i/o tf0 - tf2 transmit frame sync i/o rf0 - rf2 receive frame sync i/o table 7. pin description list (continued) pin name function type active level comments
27 AT91RM9200 1768b?atarm?08/03 timer/counter tclk0 - tclk5 external clock input input tioa0 - tioa5 i/o line a i/o tiob0 - tiob5 i/o line b i/o spi miso master in slave out i/o mosi master out slave in i/o spck spi serial clock i/o npcs0 spi peripheral chip select 0 i/o low npcs1 - npcs3 spi peripheral chip select output low two-wire interface twd two-wire serial data i/o twck two-wire serial clock i/o table 7. pin description list (continued) pin name function type active level comments
28 AT91RM9200 1768b?atarm?08/03 peripheral identifiers the AT91RM9200 embeds a wide range of peripherals. table 8 defines the peripheral identifi- ers of the AT91RM9200. a peripheral identifier is required for the control of the peripheral interrupt with the advanced interrupt controller and for the control of the peripheral clock with the power management controller. table 8. peripheral identifiers peripheral id peripheral mnemonic peripheral name external interrupt 0 aic advanced interrupt controller fiq 1sysirq 2 pioa parallel i/o controller a 3 piob parallel i/o controller b 4 pioc parallel i/o controller c 5 piod parallel i/o controller d 6 us0 usart 0 7 us1 usart 1 8 us2 usart 2 9 us3 usart 3 10 mci multimedia card interface 11 udp usb device port 12 twi two-wire interface 13 spi serial peripheral interface 14 ssc0 synchronous serial controller 0 15 ssc1 synchronous serial controller 1 16 ssc2 synchronous serial controller 2 17 tc0 timer/counter 0 18 tc1 timer/counter 1 19 tc2 timer/counter 2 20 tc3 timer/counter 3 21 tc4 timer/counter 4 22 tc5 timer/counter 5 23 uhp usb host port 24 emac ethernet mac 25 aic advanced interrupt controller irq0 26 aic advanced interrupt controller irq1 27 aic advanced interrupt controller irq2 28 aic advanced interrupt controller irq3 29 aic advanced interrupt controller irq4 30 aic advanced interrupt controller irq5 31 aic advanced interrupt controller irq6
29 AT91RM9200 1768b?atarm?08/03 system interrupt the system interrupt is the wired-or of the interrupt signals coming from: the memory controller the debug unit the system timer the real-time clock the power management controller the clock of these peripherals cannot be controlled and the peripheral id 1 can only be used within the advanced interrupt controller. external interrupts all external interrupt signals, i.e., the fast interrupt signal fiq or the interrupt signals irq0 to irq6, use a dedicated peripheral id. however, there is no clock control associated with these peripheral ids.
30 AT91RM9200 1768b?atarm?08/03 product memory mapping a first level of address decoding is performed by the memory controller, i.e., by the implemen- tation of the advanced system bus (asb) with additional features. decoding splits the 4g bytes of address space into 16 areas of 256m bytes. the areas 1 to 8 are directed to the ebi that associates these areas to the external chip selects nc0 to ncs7. the area 0 is reserved for the addressing of the internal memories, and a second level of decoding provides 1m bytes of internal memory area. the area 15 is reserved for the peripher- als and provides access to the advanced peripheral bus (apb). other areas are unused and performing an access within them provides an abort to the master requesting such an access. external memory mapping figure 4. external memory mapping 0x0000 0000 0x0fff ffff 0x1000 0000 0x1fff ffff 0x2000 0000 0x2fff ffff 0x3000 0000 0x3fff ffff 0x4000 0000 0x4fff ffff 0x5000 0000 0x5fff ffff 0x6000 0000 0x6fff ffff 0x7000 0000 0x7fff ffff 0x8000 0000 0x8fff ffff 0x9000 0000 0xefff ffff 0xf000 0000 0xffff ffff 256m bytes 256m bytes 256m bytes 256m bytes 256m bytes 256m bytes 256m bytes 256m bytes 256m bytes 256m bytes 6 x 256m bytes 1,536 bytes internal memories chip select 0 chip select 1 chip select 2 chip select 3 chip select 4 chip select 5 chip select 6 chip select 7 undefined (abort) peripherals smc or bfc smc or sdramc smc smc smc smc smc smc compactflash smartmedia or nand flash
31 AT91RM9200 1768b?atarm?08/03 internal memory mapping internal ram the AT91RM9200 integrates a high-speed, 16-kbyte internal sram. after reset and until the remap command is performed, the sram is only accessible at address 0x20 0000. after remap, the sram is also available at address 0x0. internal rom the AT91RM9200 integrates a 128-kbyte internal rom. at any time, the rom is mapped at address 0x10 0000. it is also accessible at address 0x0 after reset and before the remap command if the bms is tied high during reset. usb host port the AT91RM9200 integrates a usb host port open host controller interface (ohci). the registers of this interface are directly accessible on the asb bus and are mapped like a stan- dard internal memory at address 0x30 0000. figure 5. internal memory mapping 256mbytes internal memory area 0 undefined area (abort) 0x0000 0000 0x000f ffff 0x0010 0000 0x001f ffff 0x0020 0000 0x002f ffff 0x0030 0000 0x0fff ffff 1 mbytes 1 mbytes 1 mbytes 252m bytes internal memory area 1 internal rom internal memory area 2 internal sram internal memory area 3 usb host port 0x003f ffff 0x0040 0000 1 mbytes
32 AT91RM9200 1768b?atarm?08/03 peripheral mapping system peripherals mapping the system peripherals are mapped to the top 4k bytes of the address space, between the addresses 0xffff f000 and 0xffff ffff. each peripheral has 256 or 512 bytes. figure 6. system peripherals mapping 0xffff ffff 0xffff ff00 mc memory controller 256 bytes/64 registers peripheral name size 0xffff feff 0xffff fe00 0xffff fdff 0xffff fd00 0xffff fcff 0xffff fc00 0xffff fa00 0xffff f800 0xffff f600 0xffff f400 0xffff f200 0xffff f000 0xffff fbff 0xffff f9ff 0xffff f7ff 0xffff f5ff 0xffff f3ff 0xffff f1ff 256 bytes/64 registers 256 bytes/64 registers 256 bytes/64 registers real-time clock system timer power management controller pio controller c pio controller b pio controller a debug unit advanced interrupt controller 512 bytes/128 registers 512 bytes/128 registers 512 bytes/128 registers 512 bytes/128 registers 512 bytes/128 registers 512 bytes/128 registers rtc st pmc piod pioc piob pioa dbgu aic pio controller d
33 AT91RM9200 1768b?atarm?08/03 user peripherals mapping the user peripherals are mapped in the upper 256m bytes of the address space, between the addresses 0xfffa 0000and 0xfffe 3fff. each peripheral has a 16-kbyte address space. figure 7. user peripherals mapping 16k bytes peripheral name size 16k bytes 16k bytes 16k bytes 16k bytes 16k bytes 16k bytes 16k bytes 0xfffa 0000 0xfffa 3fff tc0, tc1, tc2 timer/counter 0, 1 and 2 16k bytes 16k bytes 16k bytes 16k bytes 16k bytes 16k bytes reserved reserved 0xfffa 4000 0xfffa 7fff tc3, tc4, tc5 timer/counter 3, 4 and 5 udp usb device port 0xfffb 0000 0xf000 0000 0xfff9 ffff 0xfffa 8000 0xfffa ffff 0xfffb 3fff mci multimedia card interface 0xfffb 4000 0xfffb 7fff twi two-wire interface 0xfffb 8000 0xfffb bfff emac ethernet mac 0xfffb c000 0xfffb ffff usart0 universal synchronous asynchronous receiver transmitter 0 0xfffc 0000 0xfffc 3fff usart1 universal synchronous asynchronous receiver transmitter 1 0xfffc 4000 0xfffc 7fff usart2 universal synchronous asynchronous receiver transmitter 2 0xfffc 8000 0xfffc bfff usart3 universal synchronous asynchronous receiver transmitter 3 0xfffc c000 0xfffc ffff ssc0 serial synchronous controller 0 0xfffd 0000 0xfffd 3fff ssc1 serial synchronous controller 1 0xfffd 4000 0xfffd 7fff ssc2 serial synchronous controller 2 0xfffd 8000 0xfffd bfff reserved 0xfffd c000 0xfffd ffff spi serial peripheral interface 0xfffe 0000 0xfffe 3fff reserved 0xfffe 4000 0xfffe ffff
34 AT91RM9200 1768b?atarm?08/03 peripheral implementation usart the usart describes features allowing management of the modem signals dtr, dsr, dcd and ri. for details, see ?modem mode? on page 422. in the AT91RM9200, only the usart1 implements these signals, named dtr1, dsr1, dcd1 and ri1. the usart0, usart2 and usart3 do not implement all the modem signals. only rts and cts (rts0 and cts0, rts2 and cts2, rts3 and cts3, respectively) are implemented in these usarts for other features. thus, programming the usart0, usart2 or the usart3 in modem mode may lead to unpredictable results. in these usarts, the commands relating to the modem mode have no effect and the status bits relating the status of the modem signals are never activated. timer counter the timer counter 0 to 5 are described with five generic clock inputs, timer_clock1 to timer_clock5. in the AT91RM9200, these clock inputs are connected to the master clock (mck), to the slow clock (slck) and to divisions of the master clock. for details, see ?clock control? on page 476. table 2 gives the correspondence between the timer counter clock inputs and clocks in the AT91RM9200. each timer counter 0 to 5 displays the same configuration. table 2. timer counter clocks assignment tc clock input clock timer_clock1 mck/2 timer_clock2 mck/8 timer_clock3 mck/32 timer_clock4 mck/128 timer_clock5 slck
35 AT91RM9200 1768b?atarm?08/03 arm920t processor overview overview the arm920t cached processor is a member of the arm9 ? thumb ? family of high- performance 32-bit system-on-a-chip processors. it provides a complete high perfor- mance cpu subsystem including: arm9tdmi risc integer cpu 16-kbyte instruction and 16-kbyte data caches instruction and data memory management units (mmus) write buffer amba ? (advanced microprocessor bus architecture) bus interface embedded trace macrocell (etm) interface the arm9tdmi core within the arm920t executes both the 32-bit arm and 16-bit thumb instruction sets. the arm9tdmi processor is a harvard architecture device, implementing a five-stage pipeline consisting of fetch, decode, execute, memory and write stages. the arm920t processor incorporates two coprocessors: cp14 - controls software access to the debug communication channel cp15 - system control processor, providing 16 additional registers that are used to configure and control the caches, the mmu, protection system, clocking mode and other system options the main features of the arm920t processor are: arm9tdmi ? -based, arm ? architecture v4t two instruction sets ? arm high-performance 32-bit instruction set ? thumb high code density 16-bit instruction set 5-stage pipeline architecture ? instruction fetch (f) ? instruction decode (d) ?execute (e) ? data memory access (m) ? register write (w) 16-kbyte data cache, 16-kbyte instruction cache ? virtually-addressed 64-way associative cache ? 8 words per line ? write-though and write-back operation ? pseudo-random or round-robin replacement ? low-power cam ram implementation write buffer ? 16-word data buffer ? 4-address address buffer ? software control drain standard armv4 memory management unit (mmu) ? access permission for sections
36 AT91RM9200 1768b?atarm?08/03 ? access permission for large pages and small pages can be specified separately for each quarter of the pages ? 16 embedded domains ? 64-entry instruction tlb and 64-entry data tlb 8-, 16-, 32-bit data bus for instructions and data block diagram figure 8. arm920t internal functional block diagram r13 cp15 instruction cache instruction mmu write buffer write back pa tag ram data mmu data cache ice arm9tdmi ice interface data virtual address bus data bus data modified virtual address bus bus interface memory controller data physical address bus data index bus r13 instruction modified virtual address bus instruction bus instruction virtual address bus write back physical address bus instruction physical address bus arm920t
37 AT91RM9200 1768b?atarm?08/03 arm9tdmi processor instruction type instructions are either 32 bits (in arm state) or 16 bits (in thumb state). data types arm9tdmi supports byte (8-bit), half-word (16-bit) and word (32-bit) data types. words must be aligned to four-byte boundaries and half-words to two-byte boundaries. unaligned data access behavior depends on which instruction is used in a particular location. arm9tdmi operating modes the arm9tdmi, based on arm architecture v4t, supports seven processor modes: user: standard arm program execution state fiq: designed to support high-speed data transfer or channel processes irq: used for general-purpose interrupt handling supervisor: protected mode for the operating system abort mode: implements virtual memory and/or memory protection system: a privileged user mode for the operating system undefined: supports software emulation of hardware coprocessors mode changes may be made under software control, or may be brought about by exter- nal interrupts or exception pr ocessing. most application programs will execute in user mode. the non-user modes, known as privileged modes, are entered in order to service interrupts or exceptions or to access protected resources.
38 AT91RM9200 1768b?atarm?08/03 arm9tdmi registers the arm9tdmi processor core consists of a 32-bit datapath and associated control logic. that datapath contains 31 general-pur pose registers, coupled to a full shifter, arithmetic logic unit and multiplier. at any one time, 16 registers are visible to the user. the remainder are synonyms used to speed up exception processing. register 15 is the program counter (pc) and can be used in all instructions to reference data relative to the current instruction. r14 holds the return address after a subroutine call. r13 is used (by software convention) as a stack pointer. registers r0 to r7 are unbanked registers, thus each of them refers to the same 32-bit physical register in all processor modes. they are general-purpose registers, with no special uses managed by the architecture, and can be used wherever an instruction allows a general-purpose register to be specified. table 9. arm9tdmi modes and register layout user and system mode supervisor mode abort mode undefined mode interrupt mode fast interrupt mode r0 r0 r0 r0 r0 r0 r1 r1 r1 r1 r1 r1 r2 r2 r2 r2 r2 r2 r3 r3 r3 r3 r3 r3 r4 r4 r4 r4 r4 r4 r5 r5 r5 r5 r5 r5 r6 r6 r6 r6 r6 r6 r7 r7 r7 r7 r7 r7 r8 r8 r8 r8 r8 r8_fiq r9 r9 r9 r9 r9 r9_fiq r10 r10 r10 r10 r10 r10_fiq r11 r11 r11 r11 r11 r11_fiq r12 r12 r12 r12 r12 r12_fiq r13 r13_svc r13_abort r13_undef r13_irq r13_fiq r14 r14_svc r14_abort r14_undef r14_irq r14_fiq pc pc pc pc pc pc cpsr cpsr cpsr cpsr cpsr cpsr spsr_svc spsr_abo rt spsr_und ef spsr_irq spsr_fiq mode-specific banked registers
39 AT91RM9200 1768b?atarm?08/03 registers r8 to r14 are banked registers. this means that each of them depends of the current processor mode. for further details, see the arm architecture reference manual, rev. ddi0100e. modes and exception handling all exceptions have banked registers for r14 and r13. after an exception, r14 holds the return address for exception processing. this address is used both to return after the exception is processed and to address the instruction that caused the exception. r13 is banked across exception modes to provide each exception handler with a private stack pointer. the fast interrupt mode also banks registers 8 to 12 so that interrupt processing can begin without the need to save these registers. a seventh processing mode, system mode, does not have any banked registers. it uses the user mode registers. system mode runs tasks that require a privileged processor mode and allows them to invoke all classes of exceptions. status registers all other processor states are held in status registers. the current operating processor status is in the current program status register (cpsr). the cpsr holds: four alu flags (negative, zero, carry, and overflow), two interrupt disable bits (one for each type of interrupt), one bit to indicate arm or thumb execution five bits to encode the current processor mode all five exception modes also have a saved program status register (spsr) which holds the cpsr of the task immediately before the exception occurred. exception types the arm9tdmi supports five types of exceptions and a privileged processing mode for each type. the types of exceptions are: fast interrupt (fiq) normal interrupt (irq) memory aborts (used to implement memory protection or virtual memory) attempted execution of an undefined instruction software interrupt (swis) exceptions are generated by internal and external sources. more than one exception can occur at the same time. when an exception occurs, the banked version of r14 and the spsr for the exception mode are used to save the state. to return after handling the exception, the spsr is moved to the cpsr and r14 is moved to the pc. this can be done in two ways: use of a data-processing instruction with the s-bit set, and the pc as the destination use of the load multiple with restore cpsr instruction (ldm)
40 AT91RM9200 1768b?atarm?08/03 arm instruction set overview the arm instruction set is divided into: branch instructions data processing instructions status register transfer instructions load and store instructions coprocessor instructions exception-generating instructions arm instructions can be executed conditionally. every instruction contains a 4-bit condi- tion code field (bits[31:28]). for further details, see the arm920t technical reference manual, rev. ddi0151c. table 10 gives the arm instruction mnemonic list. table 10. arm instruction mnemonic list mnemonic operation mnemonic operation mov move cdp coprocessor data processing add add mvn move not sub subtract adc add with carry rsb reverse subtract sbc subtract with carry cmp compare rsc reverse subtract with carry tst test cmn compare negated and logical and teq test equivalence eor logical exclusive or bic bit clear mul multiply orr logical (inclusive) or smull sign long multiply mla multiply accumulate smlal signed long multiply accumulate umull unsigned long multiply msr move to status register umlal unsigned long multiply accumulate b branch mrs move from status register bx branch and exchange bl branch and link ldr load word swi software interrupt ldrsh load signed halfword str store word ldrsb load signed byte strh store half word ldrh load half word strb store byte ldrb load byte strbt store register byte with translation ldrbt load register byte with translation strt store register with translation ldrt load register with translation stm store multiple ldm load multiple swpb swap byte swp swap word mrc move from coprocessor mcr move to coprocessor stc store from coprocessor ldc load to coprocessor
41 AT91RM9200 1768b?atarm?08/03 thumb instruction set overview the thumb instruction set is a re-encoded subset of the arm instruction set. the thumb instruction set is divided into: branch instructions data processing instructions load and store instructions load and store multiple instructions exception-generating instruction in thumb mode, eight general-purpose registers are available, r0 to r7, that are the same physical registers as r0 to r7 when executing arm instructions. some thumb instructions also access the program count er (arm register 15), the link register (arm register 14) and the stack pointer (arm register 13). further instructions allow limited access to the arm register 8 to 15. for further details, see the arm920t technical reference manual, rev. ddi0151c. table 11 gives the thumb instruction mnemonic list. table 11. thumb instruction mnemonic list mnemonic operation mnemonic operation mov move mvn move not add add adc add with carry sub subtract sbc subtract with carry cmp compare cmn compare negated tst test neg negate and logical and bic bit clear eor logical exclusive or orr logical (inclusive) or lsl logical shift left lsr logical shift right asr arithmetic shift right ror rotate right mul multiply b branch bl branch and link bx branch and exchange swi software interrupt ldr load word str store word ldrh load half word strh store half word ldrb load byte strb store byte ldrsh load signed halfword ldrsb load signed byte ldmia load multiple stmia store multiple push push register to stack pop pop register from stack
42 AT91RM9200 1768b?atarm?08/03 cp15 coprocessor coprocessor 15, or system control coprocessor cp15, is used when special features are used with the arm9tdmi such as: on-chip memory management unit (mmu) instruction and/or data cache write buffer to control these features, cp15 provides 16 additional registers. see table 12. notes: 1. tlb: translation lookaside buffer 2. fcse pid: fast context switch extension process identifier table 12. cp15 registers register name access 0 id register read-only 1 control read/write 2 translation table base read/write 3 domain access control read/write 4 reserved none 5 fault status read/write 6 fault address read/write 7 cache operations write-only 8tlb (1) operations write-only 9 cache lockdown read/write 10 tlb lockdown read/write 11 reserved none 12 reserved none 13 fcse pid (2) read/write 14 reserved none 15 test configuration none
43 AT91RM9200 1768b?atarm?08/03 cp15 register access cp15 registers can only be accessed in privileged mode by: mcr (move to coprocessor from arm register) instruction mrc (move to arm register from coprocessor) instruction other instructions (cdp, ldc, stc) cause an undefined instruction exception. the mcr instruction is used to write an arm register to cp15. the mrc instruction is used to read the value of cp15 to an arm register. the assembler code for these instructions is: mcr/mrc{cond} p15, opcode_1, rd, crn, crm, opcode_2. the mcr, mrc instructions bit pattern is shown below: crm[3:0]: specified coprocessor action determines specific coprocessor action. its value is dependent on the cp15 register used. for details, refer to cp15 spe- cific register behavior. opcode_2[7:5] determines specific coprocessor operation code. by default, set to 0. rd[15:12]: arm register defines the arm register whose value is transferred to the coprocessor. if r15 is chosen, the result is unpredictable. crn[19:16]: coprocessor register determines the destination coprocessor register. opcode_1[23:20]: coprocessor code defines the coprocessor specific code. value is c15 for cp15. l: instruction bit 0 = mcr instruction 1 = mrc instruction cond [31:28]: condition 31 30 29 28 27 26 25 24 cond 1110 23 22 21 20 19 18 17 16 opcode_1 l crn 15 14 13 12 11 10 9 8 rd 1111 76543210 opcode_2 1 crm
44 AT91RM9200 1768b?atarm?08/03 memory management unit (mmu) the arm920t processor implements an enhanced arm architecture v4 mmu to pro- vide translation and access permission checks for the instruction and data address ports of the arm9tdmi core. the mmu is controlled from a single set of two-level page tables stored in the main memory, providing a single address and translation protection scheme. independently, instruction and data tlbs in the mmu can be locked and flushed. domain a domain is a collection of sections and pages. the arm920t supports 16 domains. access to the domains is controlled by the domain access control register. for details, refer to ?cp15 register 3, domain access control register? on page 52. mmu faults the mmu generates alignment faults, transla tion faults, domain f aults and permission faults. alignment fault checking is not affected by whether the mmu is enabled or not. the access controls of the mmu detect the c onditions that produce these faults. if the fault is a result of memory access, the mmu aborts the access and signals the fault to the cpu core.the mmu stores the status and address fault in the fsr and far regis- ters (only for faults generated by data access). the mmu does not store fault information about faults generated by an instruction fetch. the memory system can abort during line fetches, memory accesses and translation table access. table 13. mapping details mapping name mapping size access permission by subpage size section 1m byte section - large page 64k bytes 4 separated subpages 16k bytes small page 4k bytes 4 separated subpages 1k byte tiny page 1k byte tiny page -
45 AT91RM9200 1768b?atarm?08/03 caches, write buffers and physical address the arm920t includes an instruction cache (icache), a data cache (dcache), a write buffer and a physical address (pa) tag ram to reduce the effect on main memory bandwidth and latency performance. the arm920t implements separate 16-kbyte instruction and 16-kbyte data caches. the caches and the write buffer are controlled by the cp15 register 1 (control), cp15 register 7 (cache operations) and cp15 register 9 (cache lockdown). instruction cache (icache) the arm920t includes a 16-kbyte instruction cache (icache). the icache has 512 lines of 32 bytes, arranged as a 64-way set associative cache. instruction access is subject to mmu permission and translation checks. if the icache is enabled with the mmu disabl ed, all instructions fetched as threats are cachable. no protection checks are made and the physical address is flat-mapped to the modified virtual address. when the icache is disabled, the cache contents are ignored and all instruction fetches appear on the amba bus. on reset, the icache entries are invalidated and the icache is disabled. for best perfor- mance, icache should be enabled as soon as possible after reset. the icache is enabled by writing 1 to i bit of the cp15 register 1 and disabled by writing 0 to this bit. for more details, see ?cp15 register 1, control? on page 49. the icache is organized as eight segmen ts, each containing 64 lines with each line made up of 8 words.the position of the line within the segment is called the index and is numbered from 0 to 63. a line in the cache is identified by the index and segment. the index is independent of the mva (modified virtual address), and the segment is the bit[7:5] of the mva. data cache (dcache) and write buffer the arm920t includes a 16-kbyte data cache (dcache). the dcache has 512 lines of 32 bytes, arranged as a 64-way set associative cache, and uses mvas translated by cp15 register 13 from the arm9dtmi core. dcache the dcache is organized as eight segments, each containing 64 lines with each line made up of eight words.the position of the line within the segment is called the index and is a number from 0 to 63. the write buffer can hold up to 16 words of data and four separate addresses. dcache and write buffer operations are closely connected as their configuration is set in each section by the page descriptor in the mmu translation table. all data accesses are subject to mmu permission and translation checks. data accesses aborted by the mmu cannot cause linefill or data access via the amba asb interface. write-though operation when a cache hit occurs for a data access, the cache line that contains the data is updated to contains its value. the new data is also immediately written to the main memory. write-back operation when a cache hit occurs for a data access, the cache line is marked as dirty, meaning that its contents are not up-to-date with those in the main memory.
46 AT91RM9200 1768b?atarm?08/03 write buffer the arm920t incorporates a 16-entry write buffer to avoid stalling the processor when writes to external memory are performed. when a store occurs, its data, address and other details are written to the write buffer at high speed. the write buffer then com- pletes the store at the main memory speed (typically slower than the arm speed). in parallel, the arm9tdmi processor can execute further instructions at full speed. physical address tag ram (pa tag ram) the arm920t implements physical address tag ram (pa tag ram) to perform write- backs from the data cache. the physical address of all the lines held in the data cache is stored in the pa tag memory, removing the need for address translation when evicting a line from the cache. when a line is written into the data cache, the physical address tag is written into the pa tag ram. if this line has to be written back to the main memory, the pa tag ram is read and the physical address is used by the amba asb interface to perform the write-back. for a 16-kbyte dcache, the pa tag ram is organized by eight segments with: 64 rows per segments 26 bits per rows
47 AT91RM9200 1768b?atarm?08/03 arm920t user interface cp15 register 0, id code and cache type access: read-only the cp register 0 contains specific hardware information. the contents of the read accesses are determined by the opcode_2 field value. writing to register 0 is unpredictable. id code the id code register is accessed by reading the register 0 with the opcode_2 field set to 0. the contents of the id code is shown below: layoutrev[3:0]: revision contains the processor revision number pnumber[15:4]: processor part number 0x920 value for arm920t processor. archi[19:16]: architecture details the implementor architecture code. 0x2 value means armv4t architecture. srev[23:20]: specification revision number 0x1 value; specification revision number used to distinguished two variants of the same primary part. imp[31:24]: implementor code 0x41 (= a); means arm ltd. 31 30 29 28 27 26 25 24 imp 23 22 21 20 19 18 17 16 srev archi 15 14 13 12 11 10 9 8 pnumber 76543210 layout rev
48 AT91RM9200 1768b?atarm?08/03 cache type the cache type register is accessed by reading the register 0 with the opcode_2 field set to 1. the cache type register contains information about the size and architecture of the caches. isize[11:0]: instruction cache size indicates the size, line length and associativity of the instruction cache. dsize[23:12]: data cache size indicates the size, line length and associativity of the data cache. s[24]: cache indicates if the cache is unified or has separate instruction and data caches. set to 1, this field indicates separate instruction and data caches. ctype[28:25]: cache type defines the cache type. for details on bits dsize and isize, refer to the arm920t technical reference manual, rev. ddi0151c. 31 30 29 28 27 26 25 24 000 ctype s 23 22 21 20 19 18 17 16 dsize 15 14 13 12 11 10 9 8 76543210 isize
49 AT91RM9200 1768b?atarm?08/03 cp15 register 1, control access: read/write the cp15 register 1, or control register, contains the control bits of the arm920t. m[0]: mmu enable 0 = mmu disabled. 1 = mmu enabled. a[1]: alignment fault enable 0 = fault checking disabled. 1 = fault checking enabled. c[2]: dcache enable 0 = dcache disabled. 1 = dcache enabled. b[7]: endianness 0 = little endian mode. 1 = big endian mode. s[8]: system protection modifies the mmu protection system. for further details, see the arm920t technical reference manual, rev. ddi0151c. r[9]: rom protection modifies the mmu protection system. for further details, see the arm920t technical reference manual, rev. ddi0151c. i[12]: icache control 0 = icache disabled. 1 = icache enabled. v[13]: base location of exception register 0 = low address means 0x00000000. 1 = high address means 0xffff0000. rr[14]: round robin replacement 0 = random replacement. 1 = round robin replacement. 31 30 29 28 27 26 25 24 ianf------ 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -rrv i 0 0 r s 76543210 b1111cam
50 AT91RM9200 1768b?atarm?08/03 clocking mode[31:30] (ia and nf bits) ia nf clocking mode 00fast bus 0 1 synchronous 10reserved 1 1 asynchronous
51 AT91RM9200 1768b?atarm?08/03 cp15 register 2, ttb access: read/write the cp15 register 2, or translation table base (ttb) register, defines the first-level translation table. pointer[31:14] points to the first-level translation table base. read returns the currently active first-level translation table. write sets t he pointer to the first-level table to the written value. the non-defined bits should be zero when written and are unpredictable when read. 31 30 29 28 27 26 25 24 pointer 23 22 21 20 19 18 17 16 pointer 15 14 13 12 11 10 9 8 pointer ------ 76543210 --------
52 AT91RM9200 1768b?atarm?08/03 cp15 register 3, domain access control register access: read/write the cp 15 register 3, or domain access control register, defines the domain?s access permission. mmu accesses are priory controlled through the use of 16 domains. each field of register 3 is associated with one domain. d15 to d0: named domain access the 2-bit field value allows domain access as described in the table below. 31 30 29 28 27 26 25 24 d15 d14 d13 d12 23 22 21 20 19 18 17 16 d11 d10 d9 d8 d 15 14 13 12 11 10 9 8 d7 d6 d5 d4 76543210 d3 d2 d1 d0 value access description 0 0 no access any access generates a domain fault 0 1 client the users of domain (execute programs, access data), the domain access permission controlled the domain access. 1 0 reserved reserved 1 1 manager controls the behavior of the domain, no checking of the domain access permission is done
53 AT91RM9200 1768b?atarm?08/03 cp15 register 4, reserved any access (read or write) to this register causes unpredictable behavior. cp15 register 5, fa ult status register access: read/write reading the cp 15 register 5, or fault status register (fsr), returns the source of the last data fault, indicating the domain and type of access being attempted when the data abort occurred. in addition, the virtual address which caused the data abort is written into the fault address register (cp15 register 6). writing the cp 15 register 5, or fault status register (fsr), sets the fsr to the value of the data written. this is useful for a debugger to restore the value of the fsr. status[3:0]: fault type indicates the fault type. the status field is encoded by the mmu when a data abort occurs. the interpretation of the status field is dependant on the domain field and the mva associated with the data abort (stored in the far). domain[7:4]: domain indicates the domain (d15 - d0) being accessed when the fault occurred. the non-defined bits should be zero when written and are unpredictable when read. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- d 15 14 13 12 11 10 9 8 -------- 76543210 domain status
54 AT91RM9200 1768b?atarm?08/03 cp15 register 6, fault address register access: read/write the cp 15 register 6, or fault address register (far), contains the mva (modified virtual address) of the access being attempted when the last fault occurred. the far is only updated for data faults, not for prefetch faults. the ability to write to the far is provided to allow a debugger to restore a previous state. far[31:0]: fault address on reading: returns the value of the far. the far holds the virtual address of the access which was attempted when fault occurred. on writing: sets the far to the value of the written data. this is useful for a debugger to restore the value of the far. 31 30 29 28 27 26 25 24 far 23 22 21 20 19 18 17 16 far d 15 14 13 12 11 10 9 8 far 76543210 far
55 AT91RM9200 1768b?atarm?08/03 cp15 register 7, cache operation register access: write-only the cp15 register 7, or cache operation register, is used to manage the instruction cache (icache) and the data cache (dcache). the function of each cache operation is selected by the opcode_2 and crm fields in the mcr instruction used to write cp15 register 7. functions details wait for interrupt stops execution in low-power state until an interrupt occurs. invalidate the cache line (or lines) is marked as invalid, so no cache hits occur in that line until it is re-allocated to an address. clean applies to write-back data caches. if the cache line contains stored data that has not yet been written out to the main mem- ory, it is written to main memory immediately. drain write buffer stops the execution until all data in the write buffer has been stored in the main memory. prefetch the memory cache line at the specified virtual address is loaded into the cache. table 14. cache functions function data crm opcode_2 wait for interrupt sbz c0 4 invalidate icache sbz c5 0 invalidate icache single entry (using mva) mva format c5 1 invalidate dcache sbz c6 0 invalidate dcache single entry (using mva) mva format c6 1 invalidate icache and dcache sbz c7 0 clean dcache singe entry (using mva) mva format c10 1 clean dcache single entry (using index) index format c10 2 drain write buffer sbz c10 4 prefetch icache line (using mva) mva format c13 1 clean and invalidate dcache entry (using mva) mva format c14 1 clean and invalidate dcache entry (using index) index format c14 2
56 AT91RM9200 1768b?atarm?08/03 the operation carried out on a single cache line identifies the line using the data transferred in the mcr instruction. the data is interpreted as using one of the two formats: ?mva format ? index format below are the details of cp15 register 7, or cache function register, in mva format. mva[31:5]: modified virtual address the non-defined bits should be zero when written and are unpredictable when read. below the details of cp15 register 7, or cache function register, in index format: index[31:26]: line determines the cache line. set[7:5]: segment determines the cache segment. the non-defined bits should be zero when written and are unpredictable when read. writing other opcode_2 values or crm values is unpredictable. reading from cp15 register 7 is unpredictable. 31 30 29 28 27 26 25 24 mva 23 22 21 20 19 18 17 16 mva 15 14 13 12 11 10 9 8 mva 76543210 mva ----- 31 30 29 28 27 26 25 24 index - - 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 set -----
57 AT91RM9200 1768b?atarm?08/03 cp15 register 8, tlb operations register access: write-only the cp15 register 8, or translation lookaside buffer (tlb) operations register, is used to manage instruction tlbs and data tlbs. the tlb operation is selected by opcode_2 and crm fields in the mcr instruction used to write cp15 register 8. below are details of the cp15 register 8 for tlb operation on mva format and one single entry. mva[31:10]: modified virtual address the non-defined bits should be zero when written and are unpredictable when read. writing other opcode_2 values or crm values is unpredictable. reading from cp15 register 8 is unpredictable. table 15. tlb operations function data crm opcode_2 invalidate i tlb sbz 5 0 invalidate i tlb single entry (using mva) mva format 5 1 invalidate d tlb sbz 6 0 invalidate d tlb single entry (using mva) mva format 6 1 invalidate both instruction and data tlb sbz 7 31 30 29 28 27 26 25 24 mva 23 22 21 20 19 18 17 16 mva 15 14 13 12 11 10 9 8 mva - - 76543210 --------
58 AT91RM9200 1768b?atarm?08/03 cp15 register 9, cache lockdown register access: read/write the cp15 register 9, or cache lockdown register, is 0x0 on reset. the cache lockdown register allows software to con- trol which cache line in the icache or dcache is loaded for a linefill. it prevents lines in the icache or dcache from being evicted during a linefill, locking them into the cache. reading from the cp15 register 9 returns the value of the cache lockdown register that is the base pointer for all cache segments. only the bits[31:26] are returned; others are unpredictable. writing to the cp15 register 9 updates the cache lockdown register with both the base and the current victim pointers for all cache segments. index[31:26]: victim pointer current victim pointer that specifies the cache line to be used as victim for the next linefill. the non-defined bits should be zero when written and are unpredictable when read. table 16. cache lockdown functions function data crm opcode_2 read dcache lockdown base base 0 0 write dcache victim and lockdown base victim = base 0 0 read icache lockdown base base 0 1 write icache victim and lockdown base victim = base 0 1 31 30 29 28 27 26 25 24 index - - 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 --------
59 AT91RM9200 1768b?atarm?08/03 cp15 register 10, tlb lockdown register access: read/write the cp15 register 10, or tlb lockdown register, is 0x0 on reset. there is a tlsb lockdown register for each of the tlbs; the value of opcode_2 determines which tlb register to access: opcode_2 = 0x0 for d tlb register opcode_2 = 0x1 for i tlb register base[31:26]: base the tlb replacement strategy only uses the tlb entries numbered from base to 63. the victim field provided is in that range. victim[25:20]: victim counter specifies the tlb entry (line) being overwritten. p[0]: preserved if 0, the tlb entry can be invalidated. if 1, the tlb entry is protected. it cannot be invalidated during the invalidate all instruction. refer to ?cp15 register 8, tl b operations register? on page 57. the non-defined bits should be zero when written and are unpredictable when read. cp15 registers 11, 12, reserved any access (read or write) to these registers causes unpredictable behavior. table 17. tlb lockdown functions function data crm opcode_2 read d tlb lockdown tlb lockdown 0 0 write d tlb lockdown tlb lockdown 0 0 read i tlb lockdown tlb lockdown 0 1 write i tlb lockdown tlb lockdown 0 1 31 30 29 28 27 26 25 24 base 23 22 21 20 19 18 17 16 victim ---- d 15 14 13 12 11 10 9 8 -------- 76543210 -------p
60 AT91RM9200 1768b?atarm?08/03 cp15 register 13, fcse pid register access: read/write the cp15 register 13, or fast context switch extension (fcse) process identifier (pid) register, is set to 0x0 on reset. reading from cp15 register 13 returns the fcse pid value. writing to cp15 register 13 sets the fcse pid. the fcse pid sets the mapping between the arm9tdmi and the mmu of the cache memories. the addresses issued by the arm9tdmi are in the range of 0 to 32 mbytes and are translated via the fcse pid. fcsepid[31:25]: fcse pid the fcse pid modifies the behavior of the of the arm920t memory system. this modification allows multiple programs to run on the arm. the 4-gb virtual address is divided into 128 process blocks of 32 mbytes each. each process block can contain a program that has been compiled to use the address range 0x00000000 to 0x01ffffff. for each i = 0 to 127 process blocks, i runs from address i*0x20000000 to ad dress i*0x2000 0000 + 0x01ffffff. for further details, see the arm920t technical reference manual, rev. ddi0151c. the non-defined bits should be zero when written and are unpredictable when read. cp15 register 14, reserved any access (read or write) of these registers causes unpredictable behavior. cp15 register 15, test configuration register cp15 register 15, or test configuration register, is used for test purposed. any access (write or read) to this register causes unpredictable behavior. 31 30 29 28 27 26 25 24 fcsepid - 23 22 21 20 19 18 17 16 -------- d 15 14 13 12 11 10 9 8 -------- 76543210 --------
61 AT91RM9200 1768b?atarm?08/03 debug and test f eatures (dbg test) overview the AT91RM9200 features a number of complementary debug and test capabilities. a com- mon jtag/ice (in-circuit emulator) port is used for standard debugging functions such as downloading code and single-stepping through programs. an etm (embedded trace macro- cell) provides more sophisticated debug features such as address and data comparators, half- rate clock mode, counters, sequencer and fifo. the debug unit provides a two-pin uart that can be used to upload an application into internal sram. it manages the interrupt han- dling of the internal commtx and commrx signals that trace the activity of the debug communication channel. a set of dedicated debug and test input/output pins give direct access to these capabilities from a pc-based test environment. features of debug and test features are: integrated embedded in-circuit-emulator debug unit ?two-pin uart ? debug communication channel ? chip id register embedded trace macrocell: etm9 rev2a ? medium level implementation ? half-rate clock mode ? four pairs of address comparators ? two data comparators ? eight memory map decoder inputs ? two counters ? one sequencer ? one 18-byte fifo ieee1149.1 jtag boundary scan on all digital pins
62 AT91RM9200 1768b?atarm?08/03 block diagram figure 9. AT91RM9200 debug and test block diagram 2 etm ice arm9tdmi pdc dbgu pio drxd dtxd tpk0-tpk15 tps0-tps2 tsync tclk tms tck tdi ntrst jtagsel tdo tst0-tst1 nrst reset and test tap: test access port boundary port ice/jtag ta p arm920t
63 AT91RM9200 1768b?atarm?08/03 application examples debug environment figure 10 on page 63 shows a complete debug environment example. the ice/jtag inter- face is used for standard debugging functions such as downloading code and single-stepping through the program. the trace port interface is used for tracing information. a software debugger running on a personal computer provides the user interface for configuring a trace port interface utilizing the ice/jtag interface. figure 10. AT91RM9200-based application debug and trace environment example test environment figure 11 below shows a test environment example. test vectors are sent and interpreted by the tester. in this example, the ?board under test? is designed using many jtag compliant devices. these devices can be connected together to form a single scan chain. AT91RM9200-based application board ice/jtag interface trace port interface ice/jtag connector AT91RM9200 terminal trace connector rs232 connector host debugger
64 AT91RM9200 1768b?atarm?08/03 figure 11. AT91RM9200-based application ieee1149.1 test environment example debug and test pin description jtag interface at91rm920 ice/jtag connector AT91RM9200-based application board under test test adaptor tester chip n chip 2 chip 1 table 18. debug and test pin list pin name function type active level reset/test nrst microcontroller reset input low tst0 test mode select input tst1 test mode select input ice and jtag tck test clock input tdi test data in input tdo test data out output tms test mode select input ntrst test reset signal input low jtagsel jtag selection input etm (available only in bga package) tsync trace synchronization signal output tclk trace clock output tps0- tps2 trace arm pipeline status output tpk0 - tpk15 trace packet port output debug unit drxd debug receive data input drxd dtxd debug transmit data output dtxd
65 AT91RM9200 1768b?atarm?08/03 functional description test mode pins two dedicated pins (tst1, tst0) are used to define the test mode of the device. the user must make sure that these pins are both tied at low level to ensure normal operating condi- tions. other values associated to these pins are manufacturing test reserved. embedded in- circuit emulator the arm9tdmi embedded in-circuit emulator is supported via the ice/jtag port. it is con- nected to a host computer via an ice interface. debug support is implemented using an arm9tdmi core embedded within the arm920t. the internal state of the arm920t is exam- ined through an ice/jtag port which allows instructions to be serially inserted into the pipeline of the core without using the external data bus. therefore, when in debug state, a store-multiple (stm) can be inserted into the instruction pipeline. this exports the contents of the arm9tdmi registers. this data can be serially shifted out without affecting the rest of the system. there are six scan chains inside the arm920t processor which support testing, debugging, and programming of the embedded ice. the scan chains are controlled by the ice/jtag port. embedded ice mode is selected when jtagsel is low. it is not possible to switch directly between ice and jtag operations. a chip reset must be performed (nrst and ntrst) after jtagsel is changed. the test reset input to the embedded ice (ntrst) is provided sepa- rately to facilitate debug of the boot program. for further details on the embedded in-circuit-emulator, see the arm920t technical refer- ence manual, arm ltd, - ddi 0151c. debug unit the debug unit provides a two-pin (dxrd and txrd) uart that can be used for several debug and trace purposes and offers an ideal means for in-situ programming solutions and debug monitor communication. moreover, the link with two peripheral data controller channels provides packet handling of these tasks with processor time reduced to a minimum. the debug unit also manages the interrupt handling of the commtx and commrx signals that come from the ice and trace the activity of the debug communication channel. the debug unit allows blockage of access to the system through the ice interface. the debug unit can be used to upload an application into internal sram. it is activated by the boot program when no valid application is detected. the protocol used to load the application is xmodem. a specific register, the debug unit chip id register, informs about the product version and its internal configuration. AT91RM9200 debug unit chip id value is: 0x09290781, on 32-bit width. for further details on the debug unit, see the debug unit datasheet; atmel literature number, 2641. for further details on the debug unit and boot program, see the boot program specifications. embedded trace macrocell the AT91RM9200 features an embedded trace macrocell (etm), which is closely connected to the arm9tdmi processor. the embedded trace is a standard mid-level implementation and contains the following resources: four pairs of address comparators two data comparators
66 AT91RM9200 1768b?atarm?08/03 eight memory map decoder inputs two counters one sequencer four external inputs one external output one 18-byte fifo the embedded trace macrocell of the AT91RM9200 works in half-rate clock mode and thus integrates a clock divider. this assures that the maximum frequency of all the trace port sig- nals do not exceed one half of the arm920t clock speed. the embedded trace macrocell input and output resources are not used in the AT91RM9200. the embedded trace is a real-time trace module with the capability of tracing the arm9tdmi instruction and data. the embedded trace debug features are only accessible in the AT91RM9200 bga package. for further details on embedded trace macrocell, see the etm9 (rev2a) technical refer- ence manual, arm ltd. -ddi 0157e. trace port the trace port is made up of the following pins: tsync - the synchronization signal (indicates the start of a branch sequence on the trace packet port.) tclk - the trace port clock, half-rate of the arm920t processor clock. tps0 to tps2 - indicate the processor state at each trace clock edge. tpk0 to tpk15 - the trace packet data value. the trace packet information (address, data) is associated with the processor state indicated by tps. some processor states have no additional data associated with the trace packet port (i.e. failed condition code of an instruction). the packet is 8-bits wide, and up to two packets can be output per cycle. figure 12. etm9 block arm920t bus tracker tms tck tdi tdo scan chain 6 ta p controller trace control trigger, sequencer, counters fifo trace enable, view data tps-tps0 tpk15-tpk0 tsync etm9
67 AT91RM9200 1768b?atarm?08/03 implementation details this section gives an overview of the embedded trace resources. for further details, see the embedded trace macrocell specification, arm ltd. -ihi 0014h. three-state sequencer the sequencer has three possible next states (one dedicated to itself and two others) and can change on every clock cycle. the sate transition is controlled with internal events. if the user needs multiple-stage trigger schemes, the trigger event is based on a sequencer state. address comparator in single mode, address comparators compare either the instruction address or the data address against the user-programmed address. in range mode, the address comparators are arranged in pairs to form a virtual address range resource. details of the address comparator programming are: the first comparator is programmed with the range start address. the second comparator is programmed with the range end address. the resource matches if the address is within the following range: ? (address > = range start address) and (address < range end address) unpredictable behavior occurs if the two address comparators are not configurated in the same way. data comparator each full address comparator is associated with a specific data comparator. a data compara- tor is used to observe the data bus only when load and store operations occur. a data comparator has both a value register and a mask register, therefore it is possible to compare only certain bits of a preprogrammed value against the data bus. memory decoder inputs the eight memory map decoder inputs are connected to custom address decoders. the address decoders divide the memory into regions of on-chip sram, on-chip rom, and periph- erals. the address decoders also optimize the etm9 trace trigger. fifo an 18-byte fifo is used to store data tracing. the fifo is used to separate the pipeline status from the trace packet. so, the fifo can be used to buffer trace packets. a fifo overflow is detected by the embedded trace macrocell when the fifo is full or when the fifo has less bytes than the user-programmed number. for further details, see the etm9 (rev2a) technical reference manual, arm ltd. ddi 0157e. table 19. etm memory map inputs layout description region access type start_address end_address sram internal data 0x00000000 0x000fffff sram internal fetch 0x00000000 0x000fffff rom internal data 0x00100000 0x001fffff rom internal fetch 0x00100000 0x001fffff ncs0-ncs7 external data 0x10000000 0x8fffffff ncs0-ncs7 external fetch 0x10000000 0x8fffffff user peripheral internal data 0xf0000000 0xffffefff system peripheral internal data 0xfffff000 0xffffffff
68 AT91RM9200 1768b?atarm?08/03 half-rate clocking mode the etm9 is implemented in half-rate mode that allows both rising and falling edge data trac- ing of the trace clock. the half-rate mode is implemented to maintain the signal clock integrity of high speed systems (up to 100 mhz). figure 13. half-rate clocking mode care must be taken on the choice of the trace capture system as it needs to support half-rate clock functionality. application board restriction the tclk signal needs to be set with care, some timing parameters are required. refer to AT91RM9200 ?jtag/ice timings? on page 621 and ?etm timings? on page 624. the specified target system connector is the amp mictor connector. the connector must be oriented on the application board as described below in figure 14. the view of the pcb is shown from above with the trace connector mounted near the edge of the board. this allows the trace port analyzer to minimize the physical intrusiveness of the inter- connected target. figure 14. amp mictor connector orientation half-rate clocking mode trace clock tracedata arm920t clock half-rate clocking mode trace clock tracedata arm920t clock
69 AT91RM9200 1768b?atarm?08/03 ieee 1149.1 jtag boundary scan ieee 1149.1 jtag boundary scan allows pin-level access independent of the device packag- ing technology. ieee 1149.1 jtag boundary scan is enabled when jtagsel is high. the sample, extest and bypass functions are implemented. in ice debug mode, the arm processor responds with a non-jtag chip id that identifies the processor to the ice system. this is not ieee 1149.1 jtag-compliant. it is not possible to switch directly between jtag and ice operations. a chip reset must be performed (nrst and ntrst) after jtagsel is changed. two boundary scan descriptor language (bsdl) files are provided to set up testing. each bsdl file is dedicated to a specific packaging. jtag boundary scan register the boundary scan register (bsr) contains 449 bits which correspond to active pins and associated control signals. each AT91RM9200 input pin has a corresponding bit in the boundary scan register for observability. each AT91RM9200 output pin has a corresponding 2-bit register in the bsr. the output bit contains data which can be forced on the pad. the ctrl bit can put the pad into high impedance. each AT91RM9200 input/output pin corresponds to a 3-bit register in the bsr. the output bit contains data that can be forced on the pad. the input bit facilitates the observability of data applied to the pad. the ctrl bit selects the direction of the pad. table 20. jtag boundary scan register bit number pin name pin type associated bsr cells 449 a19 output output 448 a[19:16]/ba0/ba1 output ctrl 447 a20 output output 446 a[22:20]/nwe/nwr0 output ctrl 445 a21 output output 444 a22 output output 443 pc7/a23 i/o input 442 output 441 ctrl 440 pc8/a24 i/o input 439 output 438 ctrl 437 pc9/a25/cfrnw i/o input 436 output 435 ctrl 434 ncs0/bfcs output output 433 ncs[1:0]/noe/nrd/nub/ nwr1/nbs1/bfcs/sdcs output ctrl
70 AT91RM9200 1768b?atarm?08/03 432 ncs1/sdcs output output 431 ncs2 output output 430 ncs[2:3]/nbs3 output ctrl 429 ncs3 output output 428 noe/nrd output output 427 nwe/nwr0 output input 426 output 425 nub/nwr1/nbs1 output input 424 output 423 nbs3 output output 422 sdcke output output 421 sdcke/ras/cas/we/sda10 output ctrl 420 ras output output 419 cas output output 418 we output output 417 d0 i/o input 416 output 415 d[3:0] i/o ctrl 414 d1 i/o input 413 output 412 d2 i/o input 411 output 410 d3 i/o input 409 output 408 d4 i/o input 407 output 406 d[7:4] i/o ctrl 405 d5 i/o input 404 output 403 d6 i/o input 402 output 401 d7 i/o input 400 output 399 d8 i/o input 398 output table 20. jtag boundary scan register (continued) bit number pin name pin type associated bsr cells
71 AT91RM9200 1768b?atarm?08/03 397 d[11:8] i/o ctrl 396 d9 i/o input 395 output 394 d10 i/o input 393 output 392 d11 i/o input 391 output 390 d12 i/o input 389 output 388 d[15:12] i/o ctrl 387 d13 i/o input 386 output 385 d14 i/o input 384 output 383 d15 i/o input 382 output 381 pc16/d16 i/o input 380 output 379 ctrl 378 pc17d17 i/o input 377 output 376 ctrl 375 pc18/d18 i/o input 374 output 373 ctrl 372 pc19/d19 i/o input 371 output 370 ctrl 369 pc20/d20 i/o input 368 output 367 ctrl 366 pc21/d21 i/o input 365 output 364 ctrl table 20. jtag boundary scan register (continued) bit number pin name pin type associated bsr cells
72 AT91RM9200 1768b?atarm?08/03 363 pc22/d22 i/o input 362 output 361 ctrl 360 pc23/d23 i/o input 359 output 358 ctrl 357 pc24/d24 i/o input 356 output 355 ctrl 354 pc25/d25 i/o input 353 output 352 ctrl 351 pc26/d26 i/o input 350 output 349 ctrl 348 pc27/d27 i/o input 347 output 346 ctrl 345 pc28/d28 i/o input 344 output 343 ctrl 342 pc29/d29 i/o input 341 output 340 ctrl 339 pc30/d30 i/o input 338 output 337 ctrl 336 pc31/d31 i/o input 335 output 334 ctrl 333 pc10/ncs4/cfcs i/o input 332 output 331 ctrl table 20. jtag boundary scan register (continued) bit number pin name pin type associated bsr cells
73 AT91RM9200 1768b?atarm?08/03 330 pc11/ncs5/cfce1 i/o input 329 output 328 ctrl 327 pc12/ncs6/cfce2 i/o input 326 output 325 ctrl 324 pc13/ncs7 i/o input 323 output 322 ctrl 321 pc14 i/o input 320 output 319 ctrl 318 pc15 i/o input 317 output 316 ctrl 315 pc0/bcfk i/o input 314 output 313 ctrl 312 pc1/bfrdy/smoe i/o input 311 output 310 ctrl 309 pc2/bfavd i/o input 308 output 307 ctrl 306 pc3/bfbaa/smwe i/o input 305 output 304 ctrl 303 pc4/bfoe i/o input 302 output 301 ctrl 300 pc5/bfwe i/o input 299 output 298 ctrl table 20. jtag boundary scan register (continued) bit number pin name pin type associated bsr cells
74 AT91RM9200 1768b?atarm?08/03 297 pc6/nwait i/o input 296 output 295 ctrl 294 pa 0 / m i s o / p c k 3 i / o input 293 output 292 ctrl 291 pa1/mosi/pck0 i/o input 290 output 289 ctrl 288 pa2/spck/irq4 i/o input 287 output 286 ctrl 285 pa3/npcs0/irq5 i/o input 284 output 283 ctrl 282 pa4/npcs1/pck1 i/o input 281 output 280 ctrl 279 pa5/npcs2/txd3 i/o input 278 output 277 ctrl 276 pd0/etx0 i/o input 275 output 274 ctrl 273 pd1/etx1 i/o input 272 output 271 ctrl 270 pd2/etx2 i/o input 269 output 268 ctrl 267 pd3/etx3 i/o input 266 output 265 ctrl table 20. jtag boundary scan register (continued) bit number pin name pin type associated bsr cells
75 AT91RM9200 1768b?atarm?08/03 264 pd4/etxen i/o input 263 output 262 ctrl 261 pd5/etxer i/o input 260 output 259 ctrl 258 pd6/dtxd i/o input 257 output 256 ctrl 255 pa6/npcs3/rxd3 i/o input 254 output 253 ctrl 252 pa7/etxck/erefck/pck2 i/o input 251 output 250 ctrl 249 pa8/etxen/mccdb i/o input 248 output 247 ctrl 246 pa9/etx0/mcdb0 i/o input 245 output 244 ctrl 243 pa10/etx1/mcdb1 i/o input 242 output 241 ctrl 240 pa11/ecrs/ecrsdv/mcdb2 i/o input 239 output 238 ctrl 237 pa12/erx0/mcdb3 i/o input 236 output 235 ctrl 234 pa13/erx1/tclk0 i/o input 233 output 232 ctrl table 20. jtag boundary scan register (continued) bit number pin name pin type associated bsr cells
76 AT91RM9200 1768b?atarm?08/03 231 pa14/erxer/tclk1 i/o input 230 output 229 ctrl 228 pa15/emdc/tclk2 i/o input 227 output 226 ctrl 225 pa16/emdio/irq6 i/o input 224 output 223 ctrl 222 pa 1 7 / t x d 0 / t i o a 0 i / o input 221 output 220 ctrl 219 pa18/rxd0/tiob0 i/o input 218 output 217 ctrl 216 pa 1 9 / s c k 0 / t i o a 1 i / o input 215 output 214 ctrl 213 pa20/cts0/tiob1 i/o input 212 output 211 ctrl 210 pa21/rts0/tioa2 i/o input 209 output 208 ctrl 207 pa22/rxd2/tiob2 i/o input 206 output 205 ctrl 204 pa23/txd2/irq3 i/o input 203 output 202 ctrl 201 pa24/sck2/pck1 i/o input 200 output 199 ctrl table 20. jtag boundary scan register (continued) bit number pin name pin type associated bsr cells
77 AT91RM9200 1768b?atarm?08/03 198 pa25/twd/irq2 i/o input 197 output 196 ctrl 195 pa26/twck/irq1 i/o input 194 output 193 ctrl 192 pa27/mcck/tclk3 i/o input 191 output 190 ctrl 189 pa28/mccda/tclk4 i/o input 188 output 187 ctrl 186 pa29/mcda0/tclk5 i/o input 185 output 184 ctrl 183 pa30/drxd/cts2 i/o input 182 output 181 ctrl 180 pa31/dtxd/rts2 i/o input 179 output 178 ctrl 177 pb0/tf0/rts3 i/o input 176 output 175 ctrl 174 pb1/tk0/cts3 i/o input 173 output 172 ctrl 171 pb2/td0/sck3 i/o input 170 output 169 ctrl 168 pb3/rd0/mcda1 i/o input 167 output 166 ctrl table 20. jtag boundary scan register (continued) bit number pin name pin type associated bsr cells
78 AT91RM9200 1768b?atarm?08/03 165 pb4/rk0/mcda2 i/o input 164 output 163 ctrl 162 pb5/rf0/mcda3 i/o input 161 output 160 ctrl 159 pb6/tf1/tioa3 i/o input 158 output 157 ctrl 156 pb7/tk1/tiob3 i/o input 155 output 154 ctrl 153 pb8/td1/tioa4 i/o input 152 output 151 ctrl 150 pb9/rd1/tiob4 i/o input 149 output 148 ctrl 147 pb10/rk1/tioa5 i/o input 146 output 145 ctrl 144 pb11/rf1/tiob5 i/o input 143 output 142 ctrl 141 pb12/tf2/etx2 i/o input 140 output 139 ctrl 138 pb13/tk2/etx3 i/o input 137 output 136 ctrl 135 pb14/td2/etxer i/o input 134 output 133 ctrl table 20. jtag boundary scan register (continued) bit number pin name pin type associated bsr cells
79 AT91RM9200 1768b?atarm?08/03 132 pb15/rd2/erx2 i/o input 131 output 130 ctrl 129 pb16/rk2/erx3 i/o input 128 output 127 ctrl 126 pd7/pck0/tsync i/o input 125 output 124 ctrl 123 pd8/pck1/tclk i/o input 122 output 121 ctrl 120 pd9/pck2/tps0 i/o input 119 output 118 ctrl 117 pd10/pck3/tps1 i/o input 116 output 115 ctrl 114 pd11/tps2 i/o input 113 output 112 ctrl 111 pd12/tpk0 i/o input 110 output 109 ctrl 108 pb17/rf2/erxdv i/o input 107 output 106 ctrl 105 pb18/ri1/ecol i/o input 104 output 103 ctrl 102 pb19/dtr1/erxck i/o input 101 output 100 ctrl table 20. jtag boundary scan register (continued) bit number pin name pin type associated bsr cells
80 AT91RM9200 1768b?atarm?08/03 99 pb20/txd1 i/o input 98 output 97 ctrl 96 pb21/rxd1 i/o input 95 output 94 ctrl 93 pb22/sck1 i/o input 92 output 91 ctrl 90 pd13/tpk1 i/o input 89 output 88 ctrl 87 pd14/tpk2 i/o input 86 output 85 ctrl 84 pd15/td0/tpk3 i/o input 83 output 82 ctrl 81 pb23/dcd1 i/o input 80 output 79 ctrl 78 pb24/cts1 i/o input 77 output 76 ctrl 75 pb25/dsr1/ef100 i/o input 74 output 73 ctrl 72 pb26/rts1 i/o input 71 output 70 ctrl 69 pb27/pck0 i/o input 68 output 67 ctrl table 20. jtag boundary scan register (continued) bit number pin name pin type associated bsr cells
81 AT91RM9200 1768b?atarm?08/03 66 pd16/td1/tpk4 i/o input 65 output 64 ctrl 63 pd17/td2/tpk5 i/o input 62 output 61 ctrl 60 pd18/npcs1/tpk6 i/o input 59 output 58 ctrl 57 pd19/npcs2/tpk7 i/o input 56 output 55 ctrl 54 pd20/npcs3/tpk8 i/o input 53 output 52 ctrl 51 pd21/rts0/tpk9 i/o input 50 output 49 ctrl 48 pd22/rts1/tpk10 i/o input 47 output 46 ctrl 45 pd23/rts2/tpk11 i/o input 44 output 43 ctrl 42 pd24/rts3/tpk12 i/o input 41 output 40 ctrl 39 pd25/dtr1/tpk13 i/o input 38 output 37 ctrl 36 pd26/tpk14 i/o input 35 output 34 ctrl table 20. jtag boundary scan register (continued) bit number pin name pin type associated bsr cells
82 AT91RM9200 1768b?atarm?08/03 33 pd27/tpk15 i/o input 32 output 31 ctrl 30 pb28/fiq i/o input 29 output 28 ctrl 27 pb29/irq0 i/o input 26 output 25 ctrl 24 a0/nlb/nbs0 output ouput 23 a[3:0]/nlb/nwr2/nbs0 /nbs2 output ctrl 22 a1/nwr2/nbs2 output output 21 a2 output output 20 a3 output output 19 a4 output output 18 a[7:4] output ctrl 17 a5 output output 16 a6 output output 15 a7 output output 14 a8 output output 13 a[11:8] output ctrl 12 a9 output output 11 a10 output output 10 sda10 output output 9a11outputoutput 8a12outputoutput 7 a[15:12] output ctrl 6a13outputoutput 5a14outputoutput 4a15outputoutput 3 a16/ba0 output output 2 a17/ba1 output output 1a18outputoutput table 20. jtag boundary scan register (continued) bit number pin name pin type associated bsr cells
83 AT91RM9200 1768b?atarm?08/03 AT91RM9200 id code register access: read-only version[31:28]: product version number set to 0x0 = jtagsel is low. set to 0x1 = jtagsel is high. part number[27:14]: product part number set to 0x5b02. manufacturer identity[11:1] set to 0x01f. bit [0]: required by ieee std. 1149.1 set to 1. the AT91RM9200 id code value is 0x15b0203f (jtagsel is high). the AT91RM9200 id code value is 0x05b0203f (jtagsel is low). 31 30 29 28 27 26 25 24 version part number 23 22 21 20 19 18 17 16 part number 15 14 13 12 11 10 9 8 part number manufacturer identity 76543210 manufacturer identity 1
84 AT91RM9200 1768b?atarm?08/03
85 AT91RM9200 1768b?atarm?08/03 boot program overview the boot program downloads an application in any of the at91 products integrating a rom. it integrates a bootloader and a boot uploader to assure correct information download. the bootloader is activated first. it looks for a sequence of eight valid arm exception vectors in a dataflash connected to the spi, an eeprom connected to the two-wire interface (twi) or an 8-bit memory device connected to the ex ternal bus interface (ebi) (if device integrates ebi). all these vectors must be b-branch or ldr load register instructions except for the sixth instruction. this vector is used to store information, such as the size of the image to download and the type of dataflash device. if a valid sequence is found, code is downloaded into the internal sram. this is followed by a remap and a jump to the first address of the sram. if no valid arm vector sequence is found, the boot uploader is started. it initializes the debug unit serial port (dbgu) and the usb device port. it then waits for any transaction and down- loads a piece of code into the internal sram via a device firmware upgrade (dfu) protocol for usb and xmodem protocol for the dbgu. after the end of the download, it branches to the application entry point at the first address of the sram. the main features of the boot program are: default boot program stored in rom-based products downloads and runs an application from external storage media into internal sram downloaded code size depends on embedded sram size automatic detection of valid application bootloader supporting a wide range of non-volatile memories ? spi dataflash ? connected on spi npcs0 ? two-wire eeprom ? 8-bit parallel memories on ncs0 (if device integrates ebi) boot uploader in case no valid program is detected in external nvm and supporting several communication media serial communication on a dbgu (xmodem protocol) usb device port (dfu protocol)
86 AT91RM9200 1768b?atarm?08/03 flow diagram the boot program implements the algorithm presented in figure 15. figure 15. boot program algorithm flow diagram applicable only to parallel boot device interfaces timeout 10 ms timeout 40 ms device setup parallel boot spi dataflash boot twi eeprom boot download from dataflash download from eeprom download from 8-bit device dbgu serial download run run run run run or ye s ye s ye s *dfu = device firmware upgrade bootloader boot uploader usb download dfu* protocol
87 AT91RM9200 1768b?atarm?08/03 bootloader the boot program is started from address 0x0000_0000 (arm reset vector) when the on-chip boot mode is selected (bms high during the reset, only on devices with ebi integrated). the first operation is the search for a valid program in the off-chip non-volatile memories. if a valid application is found, this application is loaded into internal sram and executed by branching at address 0x0000_0000 after remap. this application may be the application code or a sec- ond-level bootloader. to optimize the downloaded application code size, the boot program embeds several func- tions that can be reused by the application. the boot program is linked at address 0x0010_0000 but the internal rom is mapped at both 0x0000_0000 and 0x0010_0000 after reset. all the call to functions is pc relati ve and does not use absolute addresses. the arm vectors are present at both addresses, 0x0000_0000 and 0x0010_0000. to access the functions in rom, a structure containing chip descriptor and function entry points is defined at a fixed address in rom. if no valid application is detected, the debug se rial port or the usb device port must be con- nected to allow the upload. a specific application provided by atmel (dfu uploader) loads the application into internal sram through the usb. to load the application through the debug serial port, a terminal application (hyperterminal) running the xmodem protocol is required. figure 16. remap action after download completion after reset, the code in internal rom is mapped at both addresses 0x0000_0000 and 0x0010_0000: 100000 ea00000b b 0x2c 00 ea00000b b 0x2c 100004 e59ff014 ldr pc,[pc,20] 04 e59ff014 ldr pc,[pc,20] 100008 e59ff014 ldr pc,[pc,20] 08 e59ff014 ldr pc,[pc,20] 10000c e59ff014 ldr pc,[pc,20] 0c e59ff014 ldr pc,[pc,20] 100010 e59ff014 ldr pc,[pc,20] 10 e59ff014 ldr pc,[pc,20] 100014 00001234 ldr pc,[pc,20] 14 00001234 ldr pc,[pc,20] 100018 e51fff20 ldr pc,[pc,-0xf20] 18 e51fff20 ldr pc,[pc,-0xf20] 10001c e51fff20 ldr pc,[pc,-0xf20] 1c e51fff20 ldr pc,[pc,-0xf20] remap internal sram internal rom internal rom internal sram 0x0020_0000 0x0000_0000 0x0010_0000 0x0000_0000
88 AT91RM9200 1768b?atarm?08/03 valid image detection the bootloader software looks for a valid application by analyzing the first 32 bytes corre- sponding to the arm exception vectors. these bytes must implement arm instructions for either branch or load pc with pc relative addressing. the sixth vector, at offset 0x18, contains the size of the image to download and the dataflash parameters. the user must replace this vector with his own vector. figure 17. ldr opcode figure 18. b opcode unconditional instruction: 0xe for bits 31 to 28 load pc with pc relative addressing instruction: ? rn = rd = pc = 0xf ?i==1 ?p==1 ? u offset added (u==1) or subtracted (u==0) ?w==1 example an example of valid vectors: 00 ea00000b b 0x2c 004 e59ff014 ldr pc, [pc,20] 08 e59ff014 ldr pc, [pc,20] 0c e59ff014 ldr pc, [pc,20] 10 e59ff014 ldr pc, [pc,20] 14 00001234 ldr pc, [pc,20] <- code size = 4660 bytes 18 e51fff20 ldr pc, [pc,-0xf20] 1c e51fff20 ldr pc, [pc,-0xf20] in download mode (dataflash, eeprom or 8-bit memory in device with ebi integrated), the size of the image to load into sram is contained in the location of the sixth arm vector. thus the user must replace this vector by the correct vector for his application. 31 28 27 24 23 20 19 16 15 12 11 0 111011 ipu1w0 rn rd 31 28 27 24 23 0 1 1 1 0 1 0 1 0 offset (24 bits)
89 AT91RM9200 1768b?atarm?08/03 structure of arm vector 6 the arm exception vector 6 is used to stor e information needed by the boot rom down- loader. this information is described below. figure 19. structure of the arm vector 6 the first eight bits contain the number of blocks to download. the size of a block is 512 bytes, allowing download of up to 128k bytes. the bits 13 to 16 determine the dataflash page number. ? dataflash page number = 2 (nb of pages) the last 15 bits contain the dataflash page size. example the following vector contains the information to describe a at45db642 dataflash which con- tains 11776 bytes to download. vector 6 is 0x0841a017 (00001000010000011010000000010111b): size to download: 0x17 * 512 bytes = 11776 bytes number pages (1101b): 13 ==> number of dataflash pages = 2 13 = 8192 dataflash page size(000010000100000b) = 1056 for download in the eeprom or 8-bit external memory (if device integrates ebi), only the size to be downloaded is decoded. 31 17 16 13 12 8 7 0 number of pages reserved nb of 512 bytes blocks to download dataflash page size table 21. dataflash device device density page size (bytes) number of pages at45db011b 1 mbit 264 512 at45db021b 2 mbits 264 1024 at45db041b 4 mbits 264 2048 at45db081b 8 mbits 264 4096 at45db161b 16 mbits 528 4096 at45db321b 32 mbits 528 8192 at45db642 64 mbits 1056 8192 at45db1282 128 mbits 1056 16384 at45db2562 256 mbits 2112 16384
90 AT91RM9200 1768b?atarm?08/03 bootloader sequence the boot program performs device initialization followed by the download procedure. if unsuc- cessful, the upload is done via the usb or debug serial port. device initialization initialization follows the steps described below: 1. pll setup ? pllb is initialized to generate a 48 mhz clock necessary to use the usb device. a register located in the power management controller (pmc) determines the frequency of the main oscillator and thus the correct factor for the pllb. table 22 defines the crystals supported by the boot program. 2. stacks setup for each arm mode 3. main oscillator frequency detection 4. interrupt controller setup 5. c variables initialization 6. branch main function download procedure the download procedure checks for a valid boot on several devices. the first device checked is a serial dataflash connected to the npcs0 of the spi, followed by the serial eeprom con- nected to the twi and by an 8-bit parallel memory connected on ncs0 of the external bus interface (if ebi is implemented in the product). table 22. crystals supported by software auto-detection (mhz) 3.0 3.2768 3.6864 3.84 4.0 4.433619 4.9152 5.0 5.24288 6.0 6.144 6.4 6.5536 7.159090 7.3728 7.864320 8.0 9.8304 10.0 11.05920 12.0 12.288 13.56 14.31818 14.7456 16.0 17.734470 18.432 20.0 24.0 25.0 28.224 32.0 33.0
91 AT91RM9200 1768b?atarm?08/03 serial dataflash download the boot program supports all atmel dataflash devices. table 21 summarizes the parame- ters to include in the arm vector 6 for all devices. the dataflash has a status register that determines all the parameters required to access the device. thus, to be compatible with the future design of the dataflash, parameters are coded in the arm vector 6. figure 20. serial dataflash download end memory uploader only for device without ebi integrated read the first 8 instructions (32 bytes). decode the sixth arm vector ye s read the two-wire eeprom into the internal sram (code size to read in vector 6) restore the reset value for the peripherals. set the pc to 0 and perform the remap to jump to the downloaded application send read command 8 vectors (except vector 6) are ldr or branch instruction ? ye s start device ack ? 8-bits parallel memory download only for device with ebi integrated no no
92 AT91RM9200 1768b?atarm?08/03 serial two-wire eeprom download generally, serial eeproms have no identification code. the bootloader checks for an acknowledgment on the first read. the device address on the two-wire bus must be 0x0. the bootloader supports the devices listed in table 23. figure 21. serial two-wire eeprom download table 23. supported eeprom devices device size organization at24c16a 16 kbits 16 bytes page write at24c164 16 kbits 16 bytes page write at24c32 32 kbits 32 bytes page write at24c64 64 kbits 32 bytes page write at24c128 128 kbits 64 bytes page write at24c256 256 kbits 64 bytes page write at24c512 528 kbits 128 bytes page write end memory uploader only for device without ebi integrated read the first 8 instructions (32 bytes). decode the sixth arm vector ye s read the two-wire eeprom into the internal sram (code size to read in vector 6) restore the reset value for the peripherals. set the pc to 0 and perform the remap to jump to the downloaded application send read command 8 vectors (except vector 6) are ldr or branch instruction ? ye s start device ack ? 8-bits parallel memory download only for device with ebi integrated no no
93 AT91RM9200 1768b?atarm?08/03 8-bit parallel flash download (applicable to devices with ebi) eight-bit parallel flash download is supported if the product integrates an external bus inter- face (ebi). all 8-bit memory devices supported by the ebi when ncs0 is configured in 8-bit data bus width are supported by the bootloader. figure 22. 8-bit parallel flash download end read the external memory into the internal sram (code size to read in vector 6) restore the reset value for the peripherals. set the pc to 0 and perform the remap to jump to the downloaded application setup memory controller 8 vectors (except vector 6) are ldr or branch instruction ? ye s start memory uploader no read the first 8 instructions (32 bytes). read the size in sixth arm vector
94 AT91RM9200 1768b?atarm?08/03 boot uploader if no valid boot device has been found during the bootloader sequence, initialization of serial communication devices (dbgu and usb device ports) is performed. ? initialization of the dbgu serial port (115200 bauds, 8, n, 1) and xmodem protocol start ? initialization of the usb device port and dfu protocol start ? download of the application the boot uploader performs the dfu and xmodem protocols to upload the application into internal sram at address 0x0020_0000. the boot program uses a piece of internal sram for variables and stacks. to prevent any upload error, the size of the application to upload must be less than the sram size minus 3k bytes. after the download, the peripheral registers are reset, the interrupts are disabled and the remap is performed. after the remap, the internal sram is at address 0x0000_0000 and the internal rom at address 0x0010_0000. the instruction setting the pc to 0 is the one just after the remap command. this instruction is fetched in the pipe before doing the remap and exe- cuted just after. this fetch cycle executes the downloaded image. external communication channels dbgu serial port the upload is performed through the dbgu serial port initialized to 115200 baud, 8, n, 1. the dbgu sends the character ?c? (0x43) to start an xmodem protocol. any terminal perform- ing this protocol can be used to send the application file to the target. the size of the binary file to send depends on the sram size embedded in the product (refer to the microcontroller datasheet to determine sram size embedded in the microcontroller). in all cases, the size of the binary file must be lower than sram size because the xmodem protocol requires some sram memory to work. xmodem protocol the xmodem protocol supported is the 128-byte length block. this protocol uses a two char- acter crc-16 to guarantee detection of a maximum bit error. xmodem protocol with crc is accurate provided both sender and receiver report successful transmission. each block of the transfer looks like: <255-blk #><--128 data bytes--> in which: ? = 01 hex ? = binary number, starts at 01, increments by 1, and wraps 0ffh to 00h (not to 01) ? <255-blk #> = 1?s complement of the blk#. ? = 2 bytes crc16 figure 23 shows a transmission using this protocol.
95 AT91RM9200 1768b?atarm?08/03 figure 23. xmodem transfer example usb device port a 48 mhz usb clock is necessary to use usb device port. it has been programmed earlier in the device initialization with pllb configuration. dfu protocol the dfu allows upgrade of the firmware of usb devices. the dfu algorithm is a part of the usb specification. for more details, refer to ?usb device firmware upgrade specification, rev. 1.0?. there are four distinct steps when carrying out a firmware upgrade: 1. enumeration: the device informs the host of its capabilities. 2. reconfiguration: the host and the device agree to initiate a firmware upgrade. 3. transfer: the host transfers the firmware image to the device. status requests are employed to maintain synchronization between the host and the device. 4. manifestation: once the device reports to the host that it has completed the reprogram- ming operations, the host issues a reset and the device executes the upgraded firmware. figure 24. dfu protocol host device soh 01 fe data[128] crc crc c ack soh 02 fd data[128] crc crc ack soh 03 fc data[100] crc crc ack eot ack host device prepare for an upgrade usb reset dfu mode activated download this firmware prepare to exit dfu mode usb reset
96 AT91RM9200 1768b?atarm?08/03 hardware and software constraints the software limitations of the boot program are: the downloaded code size is less than the sram size embedded in the product. the device address of the eeprom must be 0 on the twi bus. the code is always downloaded from the device address 0x0000_0000 (dataflash, eeprom) to the address 0x0000_0000 of the internal sram (after remap). the downloaded code must be position-independent or linked at address 0x0000_0000. the hardware limitations of the boot program are: the dataflash must be connected to npcs0 of the spi. the 8-bit parallel flash must be connected to ncs0 of the ebi (applicable for devices with integrated ebi). the spi and twi drivers use several pios in alternate functions to communicate with devices. care must be taken when these pios are used by the application. the devices connected could be unintentionally driven at boot time, and electrical conflicts between spi or twi output pins and the connected devices may appear. to assure correct functionality, it is recommended to plug in critical devices to other pins or to boot on an external 16-bit parallel memory (if product integrates an ebi) by setting bit bms. table 24 contains a list of pins that are driven during the boot program execution. these pins are driven during the boot sequence for a period of about 6 ms if no correct boot program is found. the download through the twi takes about 5 sec for 64k bytes due to the twi bit rate (100 kbits/s). for the dataflash driven by spck signal at 12 mhz, the time to download 64k bytes is reduced to 66 ms. before performing the jump to the application in internal sram, all the pios and peripherals used in the boot program are set to their reset state. note: 1. see ?peripheral multiplexing on pio lines? on page 18. table 24. pins driven during boot program execution pin used spi (dataflash) twi (eeprom) mosi (1) ox spck (1) ox npcs0 (1) ox twd (1) xi/o twck (1) xo
97 AT91RM9200 1768b?atarm?08/03 embedded software services overview an embedded software service is an independent software object that drives device resources for frequently implemented tasks. the object-or iented approach of the software provides an easy way to access services to build applications. an at91 service has several purposes: it gives software examples dedicated to the at91 devices. it can be used on several at91 device families. it offers an interface to the software stored in the rom. the main features of the software services are: compliant with atpcs compliant with ansi/iso standard c compiled in arm/thumb interworking rom entry service tempo, xmodem and dataflash services crc and sine tables service definition service structure structure definition a service structure is defined in c header files. this structure is composed of data members and pointers to functions (methods) and is similar to a class definition. there is no protection of data access or methods access. however, some functions can be used by the customer application or other services and so be considered as public methods. similarly, other functions are not invoked by them. they can be considered as private methods. this is also valid for data. methods in the service structure, pointers to functions are supposed to be initialized by default to the standard functions. only the default standard f unctions reside in rom. default methods can be overloaded by custom application methods. methods do not declare any static variables nor invoke global variables. all methods are invoked with a pointer to the service structure. a method can access and update service data without restrictions. similarly, there is no polling in the methods. in fact, there is a method to start the functionality (a read to give an example), a method to get the status (is the read achieved?), and a call- back, initialized by the start method. thus, usi ng service, the client application carries out a synchronous read by starting the read and polling the status, or an asynchronous read speci- fying a callback when starting the read operation. service entry point each at91 service, except for the rom entry service (see page 101), defines a function named at91f_open_ . it is the only entry point defined for a service. even if the functions at91f_open_ may be compared with object constructors, they do not act as constructors in that they initiate the service structure but they do not allocate it. thus the customer application must allocate it.
98 AT91RM9200 1768b?atarm?08/03 example // allocation of the service structure at91s_pipe pipe; // opening of the service at91ps_pipe ppipe = at91f_openpipe(&pipe, ?); method pointers in the service structure are initialized to the default methods defined in the at91 service. other fields in the service structure are initialized to default values or with the arguments of the function at91f_open_ . in summary, an application must know what the service structure is and where the function at91f_open_ is. the default function at91f_open_ may be redefined by the application or com- prised in an application-defined function. using a service opening a service the entry point to a service is established by initializing the service structure. an open function is associated with each service structure, except for the rom entry service (see page 101). thus, only the functions at91f_open_ are visible from the user side. access to the service methods is made via function pointers in the service structure. the function at91f_open_ has at least one argument: a pointer to the service structure that must be allocated elsewhere. it returns a pointer to the base service structure or a pointer to this service structure. the function at91f_open_ initializes all data members and method pointers. all function pointers in the service structure are set to the service?s functions. the advantage of this method is to offer a single entry point for a service. the methods of a service are initialized by the open function and each member can be overloaded. overloading a method default methods are defined for all services provided in rom. these methods may not be adapted to a project requirement. it is possi ble to overload default methods by methods defined in the project. a method is a pointer to a function. this pointer is initialized by the function at91f_open_ . to overload one or several methods in a service, the function pointer must be updated to the new method. it is possible to overload just one method of a service or all the methods of a service. in this latter case, the functionality of the service is user-defined, but still works on the same data structure. note: calling the default function at91f_open_ ensures that all methods and data are initialized.
99 AT91RM9200 1768b?atarm?08/03 this can be done by writing a new function my_openservice() . this new open function must call the library-defined function at91f_open_ , and then update one or sev- eral function pointers: table 25. overloading a method with the overloading of the open service function default service behavior in rom overloading at91f_childmethod by my_childmethod // defined in embedded_services.h typedef struct _at91s_service { char data; char (*mainmethod) (); char (*childmethod) (); } at91s_service, * at91ps_service; // defined in obj_service.c (in rom) char at91f_mainmethod () { } char at91f_childmethod () { } // init the service with default methods at91ps_service at91f_openservice( at91ps_service pservice) { pservice->data = 0; pservice->mainmethod =at91f_mainmethod; pservice->childmethod=at91f_childmethod; return pservice; } // my_childmethod will replace at91f_childmethod char my_childmethod () { } // overloading open service method at91ps_service my_openservice( at91ps_service pservice) { at91f_openservice(pservice); // overloading childmethod default value pservice->childmethod= my_childmethod; return pservice; } // allocation of the service structure at91s_service service; // opening of the service at91ps_service pservice = my_openservice(&service);
100 AT91RM9200 1768b?atarm?08/03 this also can be done directly by overloading the method after the use of at91f_open_ method: table 26. overloading a method without the overloading of the open service function. default service behavior in rom overloading at91f_childmethod by my_childmethod // defined in embedded_services.h typedef struct _at91s_service { char data; char (*mainmethod) (); char (*childmethod) (); } at91s_service, * at91ps_service; // defined in obj_service.c (in rom) char at91f_mainmethod () { } char at91f_childmethod () { } // init the service with default methods at91ps_service at91f_openservice( at91ps_service pservice) { pservice->data = 0; pservice->mainmethod =at91f_mainmethod; pservice->childmethod=at91f_childmethod; return pservice; } // my_childmethod will replace at91f_childmethod char my_childmethod () { } // allocation of the service structure at91s_service service; // opening of the service at91ps_service pservice = at91f_openservice(&service); // overloading childmethod default value pservice->childmethod= my_childmethod;
101 AT91RM9200 1768b?atarm?08/03 embedded software services definition several at91 products embed rom. in most cases, the rom integrates a bootloader and several services that may speed up the application and reduce the application code size. when software is fixed in the rom, the address of each object (function, constant, table, etc.) must be related to a customer application. this is done by providing an address table to the linker. for each version of rom, a new address table must be provided and all client applica- tions must be recompiled. the embedded software services offer another solution to access objects stored in rom. for each embedded service, the customer application requires only the address of the service entry point (see page 97). even if these services have only one entry point ( at91f_open_ function), they must be specified to the linker. the embedded software services solve this problem by providing a dedicated service: the rom entry service. the goal of this product-dedicated service is to provide just one address to access all rom functionalities. rom entry service the rom entry service of a product is a structure named at91s_romboot . some members of this structure point to the open functions of all services stored in rom (function at91f_open_ ) but also the crc and sine arrays. thus, only the address of the at91s_romboot has to be published. the application obtains the address of the rom entry service and initializes an instance of the at91s_romboot structure. to obtain the open service method of another service stored in rom, the application uses the appropriate member of the at91s_romboot structure. the address of the at91s_romboot can be found at the beginning of the rom, after the exception vectors. table 27. initialization of the rom entry service and use with an open service method application memory space rom memory space // init the rom entry service at91s_romboot const *pat91; pat91 = at91c_rom_boot_address; // allocation of the service structure at91s_ctltempo tempo; // call the service open method pat91->openctltempo(&tempo, ...); // use of tempo methods tempo.ctltempocreate(&tempo, ...); at91s_tempostatus at91f_openctltempo( at91ps_ctltempo pctltempo, void const *ptempotimer ) { ... } at91s_tempostatus at91f_ctltempocreate ( at91ps_ctltempo pctrl, at91ps_svctempo ptempo) { ... }
102 AT91RM9200 1768b?atarm?08/03 tempo service presentation the tempo service allows a single hardware system timer to support several software timers running concurrently. this works as an object notifier. there are two objects defined to control the tempo service : at91s_ctltempo and at91s_svctempo . the application declares one instance of at91s_ctltempo associated with the hardware system timer. additionally, it controls a list of instances of at91s_svctempo . each time the application requires another timer, it asks the at91s_ctltempo to create a new instance of at91s_svctempo , then the application initializes all the settings of at91s_svctempo . tempo service description table 28. tempo service methods associated function pointers & methods used by default description // typical use: pat91-> openctltempo (...); // default method: at91s_tempostatus at91f_openctltempo( at91ps_ctltempo pctltempo, void const *ptempotimer) member of at91s_romboot structure. corresponds to the open service method for the tempo service. input parameters: pointer on a control tempo object. pointer on a system timer descriptor structure. output parameters: returns 0 if openctrltempo successful. returns 1 if not. // typical use: at91s_ctltempo ctltempo; ctltempo. ctltempostart (...); // default method: at91s_tempostatus at91f_ststart(void * ptimer) member of at91s_ctltempo structure. start of the hardware system timer associated. input parameters: pointer on a void parameter corresponding to a system timer descriptor structure. output parameters: returns 2. // typical use: at91s_ctltempo ctltempo; ctltempo. ctltempoisstart (...); // default method: at91s_tempostatus at91f_stisstart( at91ps_ctltempo pctrl) member of at91s_ctltempo structure. input parameters: pointer on a control tempo object. output parameters: returns the status register of the system timer. // typical use: at91s_ctltempo ctltempo; ctltempo. ctltempocreate (...); // default method: at91s_tempostatus at91f_ctltempocreate ( at91ps_ctltempo pctrl, at91ps_svctempo ptempo) member of at91s_ctltempo structure. insert a software timer in the at91s_svctempo ?s list. input parameters: pointer on a control tempo object. pointer on a service tempo object to insert. output parameters: returns 0 if the software tempo was created. returns 1 if not.
103 AT91RM9200 1768b?atarm?08/03 note: at91s_tempostatus corresponds to an unsigned int. // typical use: at91s_ctltempo ctltempo; ctltempo. ctltemporemove (...); // default method: at91s_tempostatus at91f_ctltemporemove (at91ps_ctltempo pctrl, at91ps_svctempo ptempo) member of at91s_ctltempo structure. remove a software timer in the list. input parameters: pointer on a control tempo object. pointer on a service tempo object to remove. output parameters: returns 0 if the tempo was created. returns 1 if not. // typical use: at91s_ctltempo ctltempo; ctltempo. ctltempotick (...); // default method: at91s_tempostatus at91f_ctltempotick (at91ps_ctltempo pctrl) member of at91s_ctltempo structure. refresh all the software timers in the list. update their timeout and check if callbacks have to be launched. so, for example, this function has to be used when the hardware timer starts a new periodic interrupt if period interval timer is used. input parameters: pointer on a control tempo object. output parameters: returns 1. // typical use: at91s_svctempo svctempo; svctempo. start (...); // default method: at91s_tempostatus at91f_svctempostart ( at91ps_svctempo psvc, unsigned int timeout, unsigned int reload, void (*callback) (at91s_tempostatus, void *), void *pdata) member of at91s_svctempo structure. start a software timer. input parameters: pointer on a service tempo object. timeout to apply. number of times to reload the tempo after timeout completed for periodic execution. callback on a method to launch once the timeout completed. allows to have a hook on the current service. output parameters: returns 1. // typical use: at91s_svctempo svctempo; svctempo. stop (...); // default method: at91s_tempostatus at91f_svctempostop ( at91ps_svctempo psvc) member of at91s_svctempo structure. force to stop a software timer. input parameters: pointer on a service tempo object. output parameters: returns 1. table 28. tempo service methods (continued) associated function pointers & methods used by default description
104 AT91RM9200 1768b?atarm?08/03 using the service the first step is to find the address of the open service method at91f_openctltempo using the rom entry service. allocate one instance of at91s_ctltempo and at91s_svctempo in the application mem- ory space: // allocate the service and the control tempo at91s_ctltempo ctltempo; at91s_svctempo svctempo1; initialize the at91s_ctltempo instance by calling the at91f_openctltempo function: // initialize service pat91->openctltempo(&ctltempo, (void *) &(pat91->systimer_desc)); at this stage, the application can use the at91s_ctltempo service members. if the application wants to overload an object member, it can be done now. for example, if at91f_ctltempocreate( &ctltempo, &svctempo1 ) method is to be replaced by the applica- tion defined as my_ctltempocreate(...), the procedure is as follows: // overload at91f_ctltempocreate ctltempo.ctltempocreate = my_ctltempocreate; in most cases, initialize the at91s_svctempo object by calling the at91f_ctltempocreate method of the at91s_ctltempo service : // init the svctempo1, link it to the at91s_ctltempo object ctltempo.ctltempocreate(&ctltempo, &svctempo1); start the timeout by calling start method of the svctempo1 object. depending on the function parameters, either a callback is started at the end of the countdown or the status of the time- out is checked by reading the ticktempo member of the svctempo1 object. // start the timeout svctempo1.start(&svctempo1,100,0,null,null); // wait for the timeout of 100 (unity depends on the timer programmation) // no repetition and no callback. while (svctempo1.ticktempo); when the application needs another software timer to control a timeout, it: allocates one instance of at91s_svctempo in the application memory space // allocate the service at91s_svctempo svctempo2; initializes the at91s_svctempo object calling the at91f_ctltempocreate method of the at91s_ctltempo service : // init the svctempo2, link it to the at91s_ctltempo object ctltempo.ctltempocreate(&ctltempo, &svctempo2);
105 AT91RM9200 1768b?atarm?08/03 xmodem service presentation the xmodem service is an application of the communication pipe abstract layer. this layer is media-independent (usart, usb, etc.) and gives entry points to carry out reads and writes on an abstract media, the pipe. communication pipe service the pipe communication structure is a virtual structure that contains all the functions required to read and write a buffer, regardless of the communication media and the memory management. the pipe structure defines: a pointer to a communication service structure at91ps_svccomm a pointer to a buffer manager structure at91ps_buffer pointers on read and write functions pointers to callback functions associated to the read and write functions the following structure defines the pipe object: typedef struct _at91s_pipe { // a pipe is linked with a peripheral and a buffer at91ps_svccomm psvccomm; at91ps_buffer pbuffer; // callback functions with their arguments void (*writecallback) (at91s_pipestatus, void *); void (*readcallback) (at91s_pipestatus, void *); void *pprivatereaddata; void *pprivatewritedata; // pipe methods at91s_pipestatus (*write) ( struct _at91s_pipe *ppipe, char const * pdata, unsigned int size, void (*callback) (at91s_pipestatus, void *), void *privatedata); at91s_pipestatus (*read) ( struct _at91s_pipe *ppipe, char *pdata, unsigned int size, void (*callback) (at91s_pipestatus, void *), void *privatedata); at91s_pipestatus (*abortwrite) (struct _at91s_pipe *ppipe); at91s_pipestatus (*abortread) (struct _at91s_pipe *ppipe); at91s_pipestatus (*reset) (struct _at91s_pipe *ppipe); char (*iswritten) (struct _at91s_pipe *ppipe,char const *pvoid); char (*isreceived) (struct _at91s_pipe *ppipe,char const *pvoid); } at91s_pipe, *at91ps_pipe; the xmodem protocol implementation demonstrates how to use the communication pipe.
106 AT91RM9200 1768b?atarm?08/03 description of the buffer structure the at91ps_buffer is a pointer to the at91s_buffer structure manages the buffers. this structure embeds the following functions: pointers to functions that manage the read buffer pointers to functions that manage the write buffer all the functions can be overloaded by the application to adapt buffer management. a simple implementation of buffer management for the xmodem service is provided in the boot rom source code. typedef struct _at91s_buffer { struct _at91s_pipe *ppipe; void *pchild; // functions invoked by the pipe at91s_bufferstatus (*setrdbuffer) (struct _at91s_buffer *psbuffer, char *pbuffer, unsigned int size); at91s_bufferstatus (*setwrbuffer) (struct _at91s_buffer *psbuffer, char const *pbuffer, unsigned int size); at91s_bufferstatus (*rstrdbuffer) (struct _at91s_buffer *psbuffer); at91s_bufferstatus (*rstwrbuffer) (struct _at91s_buffer *psbuffer); char (*msgwritten) (struct _at91s_buffer *psbuffer, char const *pbuffer); char (*msgread) (struct _at91s_buffer *psbuffer, char const *pbuffer); // functions invoked by the peripheral at91s_bufferstatus (*getwrbuffer) (struct _at91s_buffer *psbuffer, char const **pdata, unsigned int *psize); at91s_bufferstatus (*getrdbuffer) (struct _at91s_buffer *psbuffer, char **pdata, unsigned int *psize); at91s_bufferstatus (*emptywrbuffer) (struct _at91s_buffer *psbuffer, unsigned int size); at91s_bufferstatus (*fillrdbuffer) (struct _at91s_buffer *psbuffer, unsigned int size); char (*iswrempty) (struct _at91s_buffer *psbuffer); char (*isrdfull) (struct _at91s_buffer *psbuffer); } at91s_buffer, *at91ps_buffer;
107 AT91RM9200 1768b?atarm?08/03 description of the svccomm structure the svccomm structure provides the interface between low-level functions and the pipe object. it contains pointers of functions initialized to the lower level functions (e.g. svcxmodem). the xmodem service implementation gives an example of svccomm use. typedef struct _at91s_service { // methods: at91s_svccommstatus (*reset) (struct _at91s_service *pservice); at91s_svccommstatus (*starttx)(struct _at91s_service *pservice); at91s_svccommstatus (*startrx)(struct _at91s_service *pservice); at91s_svccommstatus (*stoptx) (struct _at91s_service *pservice); at91s_svccommstatus (*stoprx) (struct _at91s_service *pservice); char (*txready)(struct _at91s_service *pservice); char (*rxready)(struct _at91s_service *pservice); // data: struct _at91s_buffer *pbuffer; // link to a buffer object void *pchild; } at91s_svccomm, *at91ps_svccomm;
108 AT91RM9200 1768b?atarm?08/03 description of the svcxmodem structure the svcxmodem service is a reusable implementation of the xmodem protocol. it supports only the 128-byte packet format and provides read and write functions. the svcxmodem structure defines: a pointer to a handler initialized to readhandler or writehandler a pointer to a function that processes the xmodem packet crc a pointer to a function that checks the packet header a pointer to a function that checks data with this structure, the xmodem protocol can be used with all media (usart, usb, etc.). only private methods may be overloaded to adapt the xmodem protocol to a new media. the default implementation of the xmodem uses a usart to send and receive packets. read and write functions implement peripheral data controller facilities to reduce interrupt overhead. it assumes the usart is initialized, the memory buffer allocated and the interrupts programmed. a periodic timer is required by the service to manage timeouts and the periodic transmission of the character ?c? (refer to xmodem protocol). this feature is provided by the tempo service. the following structure defines the xmodem service: typedef struct _at91ps_svcxmodem { // public methods: at91s_svccommstatus (*handler) (struct _at91ps_svcxmodem *, unsigned int); at91s_svccommstatus (*starttx) (struct _at91ps_svcxmodem *, unsigned int); at91s_svccommstatus (*stoptx) (struct _at91ps_svcxmodem *, unsigned int); // private methods: at91s_svccommstatus (*readhandler) (struct _at91ps_svcxmodem *, unsigned int csr); at91s_svccommstatus (*writehandler) (struct _at91ps_svcxmodem *, unsigned int csr); unsigned short (*getcrc) (char *ptr, unsigned int count); char (*checkheader) (unsigned char currentpacket, char *packet); char (*checkdata) (struct _at91ps_svcxmodem *); at91s_svccomm parent; // base class at91ps_usart pusart; at91s_svctempo tempo; // link to a at91s_tempo object char *pdata; unsigned int datasize; // = xmodem_data_stx or xmodem_data_soh char packetdesc[at91c_xmodem_packet_size]; unsigned char packetid; // current packet char packetstatus; char ispacketdesc; char eot; // end of transmition } at91s_svcxmodem, *at91ps_svcxmodem
109 AT91RM9200 1768b?atarm?08/03 xmodem service description table 29. xmodem service methods associated function pointers & methods used by default description // typical use: pat91-> opensvcxmodem (...); // default method: at91ps_svccomm at91f_opensvcxmodem( at91ps_svcxmodem psvcxmodem, at91ps_usart pusart, at91ps_ctltempo pctltempo) member of at91s_romboot structure. corresponds to the open service method for the xmodem service. input parameters: pointer on svcxmodem structure. pointer on a usart structure. pointer on a ctltempo structure. output parameters: returns the xmodem service pointer structure. // typical use: at91s_svcxmodem svcxmodem; svcxmodem. handler (...); // default read handler: at91s_svccommstatus at91f_svcxmodemreadhandler(at91ps_svcxmodem psvcxmodem, unsigned int csr) // default write handler: at91s_svccommstatus at91f_svcxmodemwritehandler(at91ps_svcxmodem psvcxmodem, unsigned int csr) member of at91s_svcxmodem structure. interrupt handler for xmodem read or write functionnalities input parameters: pointer on a xmodem service structure. csr: usart channel status register . output parameters: status for xmodem read or write.
110 AT91RM9200 1768b?atarm?08/03 using the service the following steps show how to initialize and use the xmodem service in an application: variables definitions: at91s_romboot const *pat91; // struct containing openservice functions at91s_sbuffer sxmbuffer; // xmodem buffer allocation at91s_svcxmodem svcxmodem; // xmodem service structure allocation at91s_pipe xmodempipe;// xmodem pipe communication struct at91s_ctltempo ctltempo; // tempo struct at91ps_buffer pxmbuffer; // pointer on a buffer structure at91ps_svccomm psvcxmodem; // pointer on a media structure initialisations // call open methods: pat91 = at91c_rom_boot_address; // openctltempo on the system timer pat91->openctltempo(&ctltempo, (void *) &(pat91->systimer_desc)); ctltempo.ctltempostart((void *) &(pat91->systimer_desc)); // xmodem buffer initialisation pxmbuffer = pat91->opensbuffer(&sxmbuffer); psvcxmodem = pat91->opensvcxmodem(&svcxmodem, at91c_base_dbgu, &ctltempo); // open communication pipe on the xmodem service pat91->openpipe(&xmodempipe, psvcxmodem, pxmbuffer); // init the dbgu peripheral // open pio for dbgu at91f_dbgu_cfgpio(); // configure dbgu at91f_us_configure ( (at91ps_usart) at91c_base_dbgu, // dbgu base address mck, // master clock at91c_us_async_mode, // mode register to be programmed baudrate , // baudrate to be programmed 0); // timeguard to be programmed // enable transmitter at91f_us_enabletx((at91ps_usart) at91c_base_dbgu); // enable receiver at91f_us_enablerx((at91ps_usart) at91c_base_dbgu); // initialize the interrupt for system timer and dbgu (shared interrupt) // initialize the interrupt source 1 for systimer and dbgu at91f_aic_configureit(at91c_base_aic, at91c_id_sys, at91c_aic_prior_highest, at91c_aic_srctype_int_level_sensitive, at91f_asm_st_dbgu_handler); // enable systimer and dbgu interrupt at91f_aic_enableit(at91c_base_aic, at91c_id_sys); xmodempipe.read(&xmodempipe, (char *) base_load_address, memory_size, xmodemprotocol, (void *) base_load_address);
111 AT91RM9200 1768b?atarm?08/03 dataflash service presentation the dataflash service allows the serial peripheral interface (spi) to support several serial dataflash and dataflash cards for reading, programming and erasing operations. this service is based on spi interrupts that are managed by a specific handler. it also uses the corresponding pdc registers. for more information on the commands available in the dataflash service, refer to the rele- vant dataflash documentation. dataflash service description table 30. dataflash service methods associated function pointers & methods used by default description // typical use: pat91-> opensvcdataflash (...); // default method: at91ps_svcdataflash at91f_opensvcdataflash ( const at91ps_pmc papmc, at91ps_svcdataflash psvcdataflash) member of at91s_romboot structure. corresponds to the open service method for the dataflash service. input parameters: pointer on a pmc register description structure. pointer on a dataflash service structure. output parameters: returns the dataflash service pointer structure. // typical use: at91s_svcdataflash svcdataflash; svcdataflash. handler (...); // default method: void at91f_dataflashhandler( at91ps_svcdataflash psvcdataflash, unsigned int status) member of at91s_svcdataflash structure. spi fixed peripheral c interrupt handler. input parameters: pointer on a dataflash service structure. status: corresponds to the interruptions detected and validated on spi (spi status register masked by spi mask register). has to be put in the interrupt handler for spi. output parameters: none. // typical use: at91s_svcdataflash svcdataflash; svcdataflash. status (...); // default method: at91s_svcdataflashstatus at91f_dataflashgetstatus(at91ps_dataflashdesc pdesc) member of at91s_svcdataflash structure. read the status register of the dataflash. input parameters: pointer on a dataflash descriptor structure (member of the service structure). output parameters: returns 0 if dataflash is busy. returns 1 if dataflash is ready. // typical use: at91s_svcdataflash svcdataflash; svcdataflash. abortcommand (...); // default method: void at91f_dataflashabortcommand(at91ps_dataflashdesc pdesc) member of at91s_svcdataflash structure allows to reset pdc & interrupts. input parameters: pointer on a dataflash descriptor structure (member of the service structure). output parameters: none.
112 AT91RM9200 1768b?atarm?08/03 // typical use: at91s_svcdataflash svcdataflash; svcdataflash. pageread (...); // default method: at91s_svcdataflashstatus at91f_dataflashpageread ( at91ps_svcdataflash psvcdataflash, unsigned int src, unsigned char *databuffer, int sizetoread ) member of at91s_svcdataflash structure read a page in dataflash. input parameters: pointer on dataflash service structure. dataflash address. data buffer destination pointer. number of bytes to read. output parameters: returns 0 if dataflash is busy. returns 1 if dataflash ready. // typical use: at91s_svcdataflash svcdataflash; svcdataflash. continuousread (...); // default method: at91s_svcdataflashstatus at91f_dataflashcontinuousread ( at91ps_svcdataflash psvcdataflash, int src, unsigned char *databuffer, int sizetoread ) member of at91s_svcdataflash structure. continuous stream read. input parameters: pointer on dataflash service structure. dataflash address. data buffer destination pointer. number of bytes to read. output parameters: returns 0 if dataflash is busy. returns 1 if dataflash is ready. // typical use: at91s_svcdataflash svcdataflash; svcdataflash. readbuffer (...); // default method: at91s_svcdataflashstatus at91f_dataflashreadbuffer ( at91ps_svcdataflash psvcdataflash, unsigned char buffercommand, unsigned int bufferaddress, unsigned char *databuffer, int sizetoread ) member of at91s_svcdataflash structure. read the internal dataflash sram buffer 1 or 2. input parameters: pointer on dataflash service structure. choose internal dataflash buffer 1 or 2 command. dataflash address. data buffer destination pointer. number of bytes to read. output parameters: returns 0 if dataflash is busy. returns 1 if dataflash is ready. returns 4 if dataflash bad command. returns 5 if dataflash bad address. // typical use: at91s_svcdataflash svcdataflash; svcdataflash. mainmemorytobuffertransfert (...); // default method: at91s_svcdataflashstatus at91f_mainmemorytobuffertransfert( at91ps_svcdataflash psvcdataflash, unsigned char buffercommand, unsigned int page) member of at91s_svcdataflash structure read a page in the internal sram buffer 1 or 2. input parameters: pointer on dataflash service structure. choose internal dataflash buffer 1 or 2 command. page to read. output parameters: returns 0 if dataflash is busy. returns 1 if dataflash is ready. returns 4 if dataflash bad command. table 30. dataflash service methods (continued) associated function pointers & methods used by default description
113 AT91RM9200 1768b?atarm?08/03 // typical use: at91s_svcdataflash svcdataflash; svcdataflash. pageread (...); // default method: at91s_svcdataflashstatus at91f_dataflashpageread ( at91ps_svcdataflash psvcdataflash, unsigned int src, unsigned char *databuffer, int sizetoread ) member of at91s_svcdataflash structure read a page in dataflash. input parameters: pointer on dataflash service structure. dataflash address. data buffer destination pointer. number of bytes to read. output parameters: returns 0 if dataflash is busy. returns 1 if dataflash ready. // typical use: at91s_svcdataflash svcdataflash; svcdataflash. continuousread (...); // default method: at91s_svcdataflashstatus at91f_dataflashcontinuousread ( at91ps_svcdataflash psvcdataflash, int src, unsigned char *databuffer, int sizetoread ) member of at91s_svcdataflash structure. continuous stream read. input parameters: pointer on dataflash service structure. dataflash address. data buffer destination pointer. number of bytes to read. output parameters: returns 0 if dataflash is busy. returns 1 if dataflash is ready. // typical use: at91s_svcdataflash svcdataflash; svcdataflash. readbuffer (...); // default method: at91s_svcdataflashstatus at91f_dataflashreadbuffer ( at91ps_svcdataflash psvcdataflash, unsigned char buffercommand, unsigned int bufferaddress, unsigned char *databuffer, int sizetoread ) member of at91s_svcdataflash structure. read the internal dataflash sram buffer 1 or 2. input parameters: pointer on dataflash service structure. choose internal dataflash buffer 1 or 2 command. dataflash address. data buffer destination pointer. number of bytes to read. output parameters: returns 0 if dataflash is busy. returns 1 if dataflash is ready. returns 4 if dataflash bad command. returns 5 if dataflash bad address. // typical use: at91s_svcdataflash svcdataflash; svcdataflash. mainmemorytobuffertransfert (...); // default method: at91s_svcdataflashstatus at91f_mainmemorytobuffertransfert( at91ps_svcdataflash psvcdataflash, unsigned char buffercommand, unsigned int page) member of at91s_svcdataflash structure read a page in the internal sram buffer 1 or 2. input parameters: pointer on dataflash service structure. choose internal dataflash buffer 1 or 2 command. page to read. output parameters: returns 0 if dataflash is busy. returns 1 if dataflash is ready. returns 4 if dataflash bad command. table 30. dataflash service methods (continued) associated function pointers & methods used by default description
114 AT91RM9200 1768b?atarm?08/03 // typical use: at91s_svcdataflash svcdataflash; svcdataflash. pagepgmbuf (...); // default method: at91s_svcdataflashstatus at91f_dataflashpagepgmbuf( at91ps_svcdataflash psvcdataflash, unsigned char buffercommand, unsigned char *src, unsigned int dest, unsigned int sizetowrite) member of at91s_svcdataflash structure page program through internal sram buffer 1 or 2. input parameters: pointer on dataflash service structure. choose internal dataflash buffer 1 or 2 command. source buffer. dataflash destination address. number of bytes to write. output parameters: returns 0 if dataflash is busy. returns 1 if dataflash is ready. returns 4 if dataflash bad command. // typical use: at91s_svcdataflash svcdataflash; svcdataflash. writebuffer (...); // default method: at91s_svcdataflashstatus at91f_dataflashwritebuffer ( at91ps_svcdataflash psvcdataflash, unsigned char buffercommand, unsigned char *databuffer, unsigned int bufferaddress, int sizetowrite ) member of at91s_svcdataflash structure. write data to the internal sram buffer 1 or 2. input parameters: pointer on dataflash service structure. choose internal dataflash buffer 1 or 2 command. pointer on data buffer to write. address in the internal buffer. number of bytes to write. output parameters: returns 0 if dataflash is busy. returns 1 if dataflash is ready. returns 4 if dataflash bad command. returns 5 if dataflash bad address. // typical use: at91s_svcdataflash svcdataflash; svcdataflash. writebuffertomain (...); // default method: at91s_svcdataflashstatus at91f_writebuffertomain ( at91ps_svcdataflash psvcdataflash, unsigned char buffercommand, unsigned int dest ) member of at91s_svcdataflash structure. write internal buffer to the dataflash main memory. input parameters: pointer on dataflash service structure. choose internal dataflash buffer 1 or 2 command. main memory address on dataflash. output parameters: returns 0 if dataflash is busy. returns 1 if dataflash is ready. table 30. dataflash service methods (continued) associated function pointers & methods used by default description
115 AT91RM9200 1768b?atarm?08/03 note: at91s_svcdataflashstatus corresponds to an unsigned int. // typical use: at91s_svcdataflash svcdataflash; svcdataflash. pageerase (...); // default method: at91s_svcdataflashstatus at91f_pageerase ( at91ps_svcdataflash psvcdataflash, unsigned int pagenumber) member of at91s_svcdataflash structure. erase a page in dataflash. input parameters: pointer on a service dataflash object. page to erase. output parameters: returns 0 if dataflash is busy. returns 1 if dataflash ready. // typical use: at91s_svcdataflash svcdataflash; svcdataflash. blockerase (...); // default method: at91s_svcdataflashstatus at91f_blockerase ( at91ps_svcdataflash psvcdataflash, unsigned int blocknumber ) member of at91s_svcdataflash structure. erase a block of 8 pages. input parameters: pointer on a service dataflash object. block to erase. output parameters: returns 0 if dataflash is busy. returns 1 if dataflash ready. // typical use: at91s_svcdataflash svcdataflash; svcdataflash. mainmemorytobuffercompare (...); // default method: at91s_svcdataflashstatus at91f_mainmemorytobuffercompare( at91ps_svcdataflash psvcdataflash, unsigned char buffercommand, unsigned int page) member of at91s_svcdataflash structure. compare the contents of a page and one of the internal sram buffer. input parameters: pointer on a service dataflash object. internal sram dataflash buffer to compare command. page to compare. output parameters: returns 0 if dataflash is busy. returns 1 if dataflash ready. returns 4 if dataflash bad command. table 30. dataflash service methods (continued) associated function pointers & methods used by default description
116 AT91RM9200 1768b?atarm?08/03 using the service the first step is to find the address of the open service method at91f_opensvcdataflash using the rom entry service. 1. allocate one instance of at91s_svcdataflash and at91s_dataflash in the application memory space: // allocate the service and a device structure. at91s_svcdataflash svcdataflash; at91s_dataflash device; // member of at91s_svcdataflash service then initialize the at91s_svcdataflash instance by calling the at91f_opensvcdataflash function: // initialize service pat91->opensvcdataflash (at91c_base_pmc, &svcdataflash); 2. initialize the spi interrupt : // initialize the spi interrupt at91_irq_open ( at91c_base_aic,at91c_id_spi,3, at91c_aic_srctype_int_level_sensitive ,at91f_spi_asm_handler); 3. configure the dataflash structure with its correct features and link it to the device structure in the at91s_svcdataflash service structure: // example with an atmel at45db321b dataflash device.pages_number = 8192; device.pages_size = 528; device.page_offset = 10; device.byte_mask = 0x300; // link to the service structure svcdataflash.pdevice = &device; 4. now the different methods can be used. following is an example of a page read of 528 bytes on page 50: // result of the read operation in rxbufferdataflash unsigned char rxbufferdataflash[528]; svcdataflash.pageread(&svcdataflash, (50*528),rxbufferdataflash,528);
117 AT91RM9200 1768b?atarm?08/03 crc service presentation this ?service? differs from the preceding ones in that it is structured differently: it is composed of an array and some methods directly accessible via the at91s_romboot structure. crc service description table 31. crc service description methods and array available description // typical use: pat91-> crc32 (...); // default method: void calculatecrc32( const unsigned char *address, unsigned int size, unsigned int *crc) this function provides a table driven 32bit crc generation for byte data. this crc is known as the ccitt crc32. input parameters: pointer on the data buffer. the size of this buffer. a pointer on the result of the crc. output parameters: none. // typical use: pat91-> crc16 (...); // default method: void calculatecrc16( const unsigned char *address, unsigned int size, unsigned short *crc) this function provides a table driven 16bit crc generation for byte data. this crc is calculated with the polynome 0x8005 input parameters: pointer on the data buffer. the size of this buffer. a pointer on the result of the crc. output parameters: none. // typical use: pat91-> crchdlc (...); // default method: void calculatecrchdlc( const unsigned char *address, unsigned int size, unsigned short *crc) this function provides a table driven 16bit crc generation for byte data. this crc is known as the hdlc crc. input parameters: pointer on the data buffer. the size of this buffer. a pointer on the result of the crc. output parameters: none. // typical use: pat91-> crcccitt (...); // default method: void calculatecrc16ccitt( const unsigned char *address, unsigned int size, unsigned short *crc) this function provides a table driven 16bit crc generation for byte data. this crc is known as the ccitt crc16 (polynome = 0x1021). input parameters: pointer on the data buffer. the size of this buffer. a pointer on the result of the crc. output parameters: none. // typical use: char reverse_byte; reverse_byte = pat91-> bit_reverse_array [...]; // array embedded: const unsigned char bit_rev[256] bit reverse array: array which allows to reverse one octet. frequently used in mathematical algorithms. used for example in the crc16 calculation.
118 AT91RM9200 1768b?atarm?08/03 using the service compute the crc16 ccitt of a 256-byte buffer and save it in the crc16 variable: // compute crc16 ccitt unsigned char buffertocompute[256]; short crc16; ... (buffertocompute treatment) pat91->crcccitt(&buffertocompute,256,&crc16); sine service presentation this ?service? differs from the preceding one in that it is structured differently: it is composed of an array and a method directly accessible through the at91s_romboot structure. sine service description table 32. sine service description method and array available description // typical use: pat91-> sine (...); // default method: short at91f_sinus(int step) this function returns the amplitude coded on 16 bits, of a sine waveform for a given step. input parameters: step of the sine. corresponds to the precision of the amplitude calculation. depends on the sine array used. here, the array has 256 values (thus 256 steps) of amplitude for 180 degrees. output parameters: amplitude of the sine waveform. // typical use: short sinus; sinus = pat91-> sinetab [...]; // array embedded: const short at91c_sinus180_tab[256] sine array with a resolution of 256 values for 180 degrees.
119 AT91RM9200 1768b?atarm?08/03 AT91RM9200 reset controller overview this chapter describes the AT91RM9200 reset signals and how to use them in order to assure correct operation of the device. the AT91RM9200 has two reset input lines ca lled nrst and ntrst. each line provides, respectively: initialization of the user interface registers (defined in the user interface of each peripheral) and: ? sample the signals needed at bootup ? compel the processor to fetch the next instruction at address zero. initialization of the embedded ice tap controller. the nrst signal must be considered as the system reset signal and the reader must take care when designing the logic to drive this reset signal. ntrst is typically used by the hard- ware debug interface which uses the in-circuit emulator unit and initializes it without affecting the normal operation of the arm ? processor. this line shall also be driven by an on board logic. both nrst and ntrst are active low si g nals that as y nchronousl y reset the lo g ic in the AT91RM92000. reset conditions nrst conditions nrst is the active low reset input. when power is first applied to the system, a power - on reset (also denominated as ?cold? reset) must be applied to the AT91RM9200. during this transient state, it is mandatory to hold the reset signal low long enough for the power supply to reach a working nominal level and for the oscillator to reach a stable operati ng frequency. typically, these features are provided by every power s upply supervisor which, under a threshold volt- age limit, the electrical environment is considered as not nominal. power-up is not the only event to be be considered as power-down or a brownout are also occurrences that assert the nrst signal. the threshold voltage must be selected according to the minimum operating voltage of the AT91RM9200 power supply lines marked as vdd in figure 25. (see ?dc char- acteristics? on page 596.) the choice of the reset holding delay depends on the start-up time of the low frequency oscil- lator as shown below in figure 25. (see ?32 khz oscillator characteristics? on page 599.) figure 25. cold reset and oscillator start-up relationship note: 1. vdd is applicable to vdd iom , vdd iop , vdd pll , vdd osc and vdd core oscillator stabilization after power-up v dd (1) nrst xin32 v dd(min)
120 AT91RM9200 1768b?atarm?08/03 nrst can also be asserted in circumstances other than the power-up sequence, such as a manual command. this assertion can be performed asynchronously, but exit from reset is synchronized internally to the default active clock. during normal operation, nrst must be active for a minimum delay time to ensure correct behavior. see figure 26 and table 33. figure 26. nrst assertion ntrst assertion as with the nrst signal, at power-up, the ntrst signal must be valid while the power supply has not obtained the the minimum recommended working level. (see ?dc characteristics? on page 596.). a clock on tck is not required to validate this reset request. as with the nrst signal, ntrst can also be asserted in circumstances other than the power- up sequence, such as a manual command or an ice interface action. this assertion and de- assertion can be performed asynchronously but must be active for a minimum delay time. (see ?jtag/ice timings? on page 621.) reset management system reset the system reset functionality is provided through the nrst signal. this reset signal is used to compel the microcontroller unit to assume a set of initial conditions: sample the boot mode select (bms) logical state. restore the default states (default values) of the user interface. require the processor to perform the next instruction fetch from address zero. with the exception of the program counter and the current program status register, the pro- cessor?s registers do not have defined reset states. when the microcontroller?s nrst input is asserted, the processor immediately stops execution of the current instruction independently of the clock. the system reset circuitry must take two types of reset requests into account: the cold reset needed for the power-up sequence. the user reset request. both have the same effect but can have different assertion time requirements regarding the nrst pin. in fact, the cold reset assertion has to overlap the start-up time of the system. the user reset request requires a shorter assertion delay time than does cold reset. test reset test reset functionality is provided through the ntrst signal. table 33. reset minimum pulse width symbol parameter min. pulse width unit rst1 nrst minimum pulse width 92 s nrst rst1
121 AT91RM9200 1768b?atarm?08/03 the ntrst control pin initializes the selected tap controller. the tap controller involved in this reset is determined according to the initial logical state applied on the jtagsel pin after the last valid nrst. in boundary scan mode, after a ntrst assertion, the idcode instruction is set onto the out- put of the instruction register in the test-logic-reset controller state. otherwise, in ice mode, the reset action is as follows: ? the core exits from debug mode. ? the idcore instruction is requested. in either boundary scan or ice mode a reset can be performed from the same or different cir- cuitry, as shown in figure 27 below, upon system reset at power-up or upon user request. figure 27. separate or common reset management notes: 1. nrst and ntrst handing in debug mode during development. 2. nrst and ntrst handling during production. in order to benefit the most regarding the separation of nrst and ntrst during the debug phase of development, the user must independently manage both signals as shown in exam- ple (1) of figure 27 above. however, once debug is completed, both signals are easily managed together during production as shown in example (2) of figure 27 above. required features for the reset controller the following table presents the features required of a reset controller in order to obtain an optimal system with the AT91RM9200 processor. nrst ntrst AT91RM9200 reset controller reset controller (1) (2) nrst ntrst AT91RM9200 reset controller table 34. reset controller functions synthesis feature description power supply monitoring overlaps the transient state of the system during power-up/down and brownout. reset active timeout period overlaps the start-up time of the boot-up oscillator by holding the reset signal during this delay. manual reset command asserts the reset signal from a logic command and holds the reset signal with a shorter delay than that of the ?reset active timeout period?.
122 AT91RM9200 1768b?atarm?08/03
123 AT91RM9200 1768b?atarm?08/03 memory controller(mc) overview the memory controller (mc) manages the asb bus and controls access by up to four mas- ters. it features a bus arbiter and an address decoder that splits the 4g bytes of address space into areas to access the embedded sram and rom, the embedded peripherals and the external memories through the external bus interface (ebi). it also features an abort sta- tus and a misalignment detector to assist in application debug. the memory controller allows booting from the embedded rom or from an external non-vola- tile memory connected to the chip select 0 of the ebi. the remap command switches addressing of the arm vectors (0x0 - 0x20) on the embedded sram. key features of the rm9200 memory controller are: programmable bus arbiter handling four masters ? internal bus is shared by arm920t, pdc, usb host port and ethernet mac masters ? each master can be assigned a priority between 0 and 7 address decoder provides selection for ? eight external 256-mbyte memory areas ? four internal 1-mbyte memory areas ? one 256-mbyte embedded peripheral area boot mode select option ? non-volatile boot memory can be internal or external ? selection is made by bms pin sampled at reset abort status registers ? source, type and all parameters of the access leading to an abort are saved misalignment detector ? alignment checking of all data accesses ? abort generation in case of misalignment remap command ? provides remapping of an internal sram in place of the boot nvm
124 AT91RM9200 1768b?atarm?08/03 block diagram figure 28. memory controller block diagram arm920t processor bus arbiter peripheral data controller memory controller abort asb abort status address decoder user interface peripheral 0 peripheral 1 internal memories apb apb bridge misalignment detector from master to slave memory controller interrupt peripheral n external bus interface emac dma uhp dma bms aic
125 AT91RM9200 1768b?atarm?08/03 functional description the memory controller (mc) handles the internal asb bus and arbitrates the accesses of up to four masters. it is made up of: a bus arbiter an address decoder an abort status a misalignment detector the memory controller handles only little-endian mode accesses. all masters must work in lit- tle-endian mode only. bus arbiter the memory controller has a user-programmable bus arbiter. each master can be assigned a priority between 0 and 7, where 7 is the highest level. the bus arbiter is programmed in the register mc_mpr (master priority register). the same priority level can be assigned to more than one master. if requests occur from two masters having the same priority level, the following default priority is used by the bus arbiter to determine the first to serve: master 0, master 1, master 2, master 3. the masters are: the arm920t as the master 0 the peripheral data controller as the master 1 the usb host port as the master 2 the ethernet mac as the master 3 address decoder the memory controller features an address decoder that first decodes the four highest bits of the 32-bit address bus and defines 11 separate areas: one 256-mbyte address space for the internal memories eight 256-mbyte address spaces, each assigned to one of the eight chip select lines of the external bus interface one 256-mbyte address space reserved for the embedded peripherals an undefined address space of 1536m bytes that returns an abort if accessed
126 AT91RM9200 1768b?atarm?08/03 external memory areas figure 29 shows the assignment of the 256-mbyte memory areas. figure 29. external memory areas internal memory mapping within the internal memory address space, the address decoder of the memory controller decodes eight more address bits to allocate 1-mbyte address spaces for the embedded memories. the allocated memories are accessed all along the 1-mbyte address space and so are repeated n times within this address space, n equaling 1m byte divided by the size of the memory. when the address of the access is undefined within the internal memory area, i.e. over the address 0x0040 0000, the address decoder returns an abort to the master. 0x0000 0000 0x0fff ffff 0x1000 0000 0x1fff ffff 0x2000 0000 0x2fff ffff 0x3000 0000 0x3fff ffff 0x4000 0000 0x4fff ffff 0x5000 0000 0x5fff ffff 0x6000 0000 0x6fff ffff 0x7000 0000 0x7fff ffff 0x8000 0000 0x8fff ffff 0x9000 0000 0xefff ffff 0xf000 0000 0xffff ffff 256m bytes 256m bytes 256m bytes 256m bytes 256m bytes 256m bytes 256m bytes 256m bytes 256m bytes 256m bytes 6 x 256m bytes 1,536 bytes internal memories chip select 0 chip select 1 chip select 2 chip select 3 chip select 4 chip select 5 chip select 6 chip select 7 undefined (abort) peripherals ebi external bus interface
127 AT91RM9200 1768b?atarm?08/03 figure 30. internal memory mapping after remap internal memory area 0 depending on the bms pin state at reset and as a function of the remap command, the mem- ory mapped at address 0x0 is different. before execution of the remap command the on-chip rom (bms = 1) or the non-volatile memory connected to external chip select zero (bms = 0) is mapped into internal memory area 0. after the remap command, the internal sram at address 0x0020 0000 is mapped into internal memory area 0. the memory mapped into inter- nal memory area 0 is accessible in both its original location and at address 0x0. the first 32 bytes of internal memory area 0 contain the arm processor exception vectors. boot mode select the bms pin state allows the device to boot out of an internal or external boot memory, actu- ally the input level on the bms pin during the last 2 clock cycles, before the reset selects the type of boot memory according to the following conditions: if high, the internal rom, which is generally mapped within the internal memory area 1, is also accessible through the internal memory area 0 if low, the external memory area 0, which is generally accessible from address 0x1000 0000, is also accessible through the internal memory area 0. the bms pin is multiplexed with an i/o line. after reset, this pin can be used as any standard pio line. remap command after execution, the remap command causes the internal sram to be accessed through the internal memory area 0. as the arm vectors (reset, abort, data abort, prefetch abort, undefined instruction, inter- rupt, and fast interrupt) are mapped from address 0x0 to address 0x20, the remap command allows the user to redefine dynamically these vectors under software control. the remap command is accessible through the memory controller user interface by writing the mc_rcr (remap control register) rcb field to one. 256m bytes internal memory area 0 undefined area (abort) 0x0000 0000 0x000f ffff 0x0010 0000 0x001f ffff 0x0020 0000 0x002f ffff 0x0030 0000 0x0fff ffff 1m byte 1m byte 1m byte 252m bytes internal memory area 1 internal rom internal memory area 2 internal sram internal memory area 3 usb host port 0x003f ffff 0x0040 0000 1m byte table 35. internal memory area depending on bms and the remap command bms state before remap after remap 10x internal memory area 0 internal rom external memory area 0 internal sram
128 AT91RM9200 1768b?atarm?08/03 the remap command can be cancelled by writing the mc_rcr rcb field to one, which acts as a toggling command. this allows easy debug of the user-defined boot sequence by offering a simple way to put the chip in the same configuration as just after a reset. table 35 on page 127 is provided to summarize the effect of these two key features on the nature of the memory mapped to the address 0x0. abort status there are two reasons for an abort to occur: an access to an undefined address an access to a misaligned address. when an abort occurs, a signal is sent back to all the masters, regardless of which one has generated the access. however, only the master having generated the access leading to the abort takes this signal into account. the abort signal generates directly an abort on the arm9tdmi. note that, from the processor perspective, an abort can also be generated by the memory management unit of the arm920t, but this is obviously not managed by the memory controller and not discussed in this section. the peripheral data controller does not handle the abort input signal (and that?s why the con- nection is not represented in figure 28). the uhp reports an unrecoverable error in the hcinterruptstatus register and resets its operations. the emac reports the abort to the user through the abt bit in its status register, which might generate an interrupt. to facilitate debug or for fault analysis by an operating system, the memory controller inte- grates an abort status register set. the full 32-bit wide abort address is saved in the abort address status register (mc_aasr). parameters of the access are saved in the abort status register (mc_asr) and include: the size of the request (abtsz field) the type of the access, whether it is a data read or write or a code fetch (abttyp field) whether the access is due to accessing an undefined address (undadd bit) or a misaligned address (misadd bit) the source of the access leading to the last abort (mst0, mst1, mst2 and mst3 bits) whether or not an abort occurred for each master since the last read of the register (svmst0, svmst1, svmst2 and svmst3 bits) except if it is traced in the mst bits. in case of data abort from the processor, the address of the data access is stored. this is probably the most useful, as finding which address has generated the abort would require dis- assembling the instruction and full knowledge of the processor context. however, in case of prefetch abort, the address might have changed, as the prefetch abort is pipelined in the arm processor. the arm processor takes the prefetch abort into account only if the read instruction is actually execut ed and it is probable that several aborts have occurred during this time. so, in this case, it is preferable to use the content of the abort link register of the arm processor. misalignment detector the memory controller features a misalignment de tector that checks the consistency of the accesses. for each access, regardless of the master, the size of access and the 0 and 1 bits of the address bus are checked. if the type of access is a word (32-bit) and the 0 and 1 bits are not 0, or if the type of the access is a half-word (16-bit) and the 0 bit is not 0, an abort is returned to the master and the access is cancelled. note that the accesses of the arm processor when it is fetching instructions are not checked.
129 AT91RM9200 1768b?atarm?08/03 the misalignments are generally due to software errors leading to wrong pointer handling. these errors are particularly difficult to detect in the debug phase. as the requested address is saved in the abort status and the address of the instruction gen- erating the misalignment is saved in the abort link register of the processor, detection and correction of this kind of software error is simplified. memory controller interrupt the memory controller itself does not generate any interrupt. however, as indicated in figure 28, the memory controller receives an interrupt signal from the external bus interface, which might be activated in case of refresh error detected by the sdram controller. this interrupt signal just transits through the memory controller, which can neither enable/disable it nor return its activity. this memory controller interrupt signal is ored with the other system peripheral interrupt lines (rtc, st, dbgu, pmc) to provide the system interrupt on source 1 of the advanced interrupt controller. user interface base address : 0xffffff00 table 36. rm9200 memory controller memory map offset register name access reset state 0x00 mc remap control register mc_rcr write-only 0x04 mc abort status register mc_asr read-only 0x0 0x08 mc abort address status register mc_aasr read-only 0x0 0x0c mc master priority register mc_mpr read/write 0x3210 0x10 - 0x5c reserved 0x60 ebi configuration registers see ebi datasheet, literature number 1759
130 AT91RM9200 1768b?atarm?08/03 mc remap control register register name : mc_rcr access type :write-only absolute address : 0xffff ff00 rcb: remap command bit 0: no effect. 1: this command bit acts on a toggle basis: writing a 1 alternatively cancels and restores the remapping of the page zero memory devices. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????rcb
131 AT91RM9200 1768b?atarm?08/03 mc abort status register register name :mc_asr access type : read-only reset value :0x0 absolute address : 0xffff ff04 undadd: undefined address abort status 0: the last abort was not due to the access of an undefined address in the address space. 1: the last abort was due to the access of an undefined address in the address space. misadd: misaligned address abort status 0: the last aborted access was not due to an address misalignment. 1: the last aborted access was due to an address misalignment. abtsz: abort size status abttyp: abort type status mst0: arm920t abort source 0: the last aborted access was not due to the arm920t. 1: the last aborted access was due to the arm920t. mst1: pdc abort source 0: the last aborted access was not due to the pdc. 1: the last aborted access was due to the pdc. 31 30 29 28 27 26 25 24 ? ? ? ? svmst3 svmst2 svmst1 svmst0 23 22 21 20 19 18 17 16 ? ? ? ? mst3 mst2 mst1 mst0 15 14 13 12 11 10 9 8 ???? abttyp abtsz 76543210 ??????misaddundadd abtsz abort size 00 byte 01 half-word 10 word 11 reserved abttyp abort type 0 0 data read 01 data write 1 0 code fetch 11 reserved
132 AT91RM9200 1768b?atarm?08/03 mst2: uhp abort source 0: the last aborted access was not due to the uhp. 1: the last aborted access was due to the uhp. mst3: emac abort source 0: the last aborted access was not due to the emac. 1: the last aborted access was due to the emac. svmst0: saved arm920t abort source 0: no abort due to the arm920t occurred since the last read of mc_asr or it is notified in the bit mst0. 1: at least one abort due to the arm920t occurred since the last read of mc_asr. svmst1: saved pdc abort source 0: no abort due to the pdc occurred since the last read of mc_asr or it is notified in the bit mst1. 1: at least one abort due to the pdc occurred since the last read of mc_asr. svmst2: saved uhp abort source 0: no abort due to the uhp occurred since the last read of mc_asr or it is notified in the bit mst2. 1: at least one abort due to the uhp occurred since the last read of mc_asr. svmst3: saved emac abort source 0: no abort due to the emac occurred since the last read of mc_asr or it is notified in the bit mst3. 1: at least one abort due to the emac occurred since the last read of mc_asr.
133 AT91RM9200 1768b?atarm?08/03 mc abort address status register register name : mc_aasr access type : read-only reset value :0x0 absolute address : 0xffff ff08 abtadd: abort address this field contains the address of the last aborted access. 31 30 29 28 27 26 25 24 abtadd 23 22 21 20 19 18 17 16 abtadd 15 14 13 12 11 10 9 8 abtadd 76543210 abtadd
134 AT91RM9200 1768b?atarm?08/03 mc master priority register register name :mc_mpr access type : read/write reset value : 0x3210 absolute address : 0xffff ff0c mstp0: arm920t priority mstp1: pdc priority mstp2: uhp priority mstp3: emac priority 000: lowest priority 111: highest priority in the case of equal priorities, master 0 has highest and master 3 has lowest priority. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? mstp3 ? mstp2 76543210 ? mstp1 ? mstp0
135 AT91RM9200 1768b?atarm?08/03 external bus interface (ebi) overview the external bus interface (ebi) is designed to ensure the successful data transfer between several external devices and the embedded memory controller of an arm ? -based device. the static memory, sdram and burst flash controllers are all featured external memory controllers on the ebi. these external memory controllers are capable of handling several types of external memory and peripheral devices, such as sram, prom, eprom, eeprom, flash, sdram and burst flash. the ebi also supports the compactflash and the smartmedia protocols via integrated cir- cuitry that greatly reduces the requirements for external components. furthermore, the ebi handles data transfers with up to eight external devices, each assigned to eight address spaces defined by the embedded memory controller. data transfers are performed through a 16-bit or 32-bit data bus, an address bus of up to 26 bits, up to eight chip select lines (ncs[7:0]) and several control pins that are generally multiplexed between the different exter- nal memory controllers. features of the ebi are: integrates three external memory controllers: ? static memory controller ? sdram controller ? burst flash controller additional logic for smartmedia tm and compactflash tm support optimized external bus: ? 16- or 32-bit data bus ? up to 26-bit address bus, up to 64-mbytes addressable ? up to 8 chip selects, each reserved to one of the eight memory areas ? optimized pin multiplexing to reduce latencies on external memories configurable chip select assignment: ? burst flash controller or static memory controller on ncs0 ? sdram controller or static memory controller on ncs1 ? static memory controller on ncs3, optional smartmedia support ? static memory controller on ncs4 - ncs6, optional compactflash support ? static memory controller on ncs7
136 AT91RM9200 1768b?atarm?08/03 block diagram figure 31 below shows the organization of the external bus interface. figure 31. organization of the external bus interface external bus interface d[15:0] a[15:2], a[22:18] pio mux logic smartmedia logic compactflash logic user interface chip select assignor static memory controller sdram controller burst flash controller memory controller apb asb address decoder a16/ba0 a0/nbs0 a1/nwr2/nbs2 a17/ba1 ncs0/bfcs ncs3/smcs nrd/noe/cfoe ncs1/sdcs ncs2 nwr0/nwe/cfwe nwr1/nbs1/cfior nwr3/nbs3/cfiow sdck sdcke ras cas sdwe d[31:16] a[24:23] a25/cfrnw ncs4/cfcs ncs5/cfce1 ncs6/cfce2 ncs7 bfck bfavd bfbaa/smwe bfoe bfrdy/smoe bfwe nwait sda10
137 AT91RM9200 1768b?atarm?08/03 i/o lines description table 37. i/o lines description name function type active level ebi d[31:0] data bus i/o a[25:0] address bus output smc ncs[7:0] chip select lines output low nwr[1:0] write signals output low noe output enable output low nrd read signal output low nbs1 nub: upper byte select output low nbs0 nlb: lower byte select output low nwe write enable output low ebi for compactflash support cfce[2:1] compactflash chip enable output low cfoe compactflash output enable output low cfwe compactflash write enable output low cfior compactflash i/o read signal output low cfiow compactflash i/o write signal output low cfrnw compactflash read not write signal output cfcs compactflash chip select line output low nwait compactflash wait signal input low ebi for smartmedia support smcs smartmedia chip select line output low smoe smartmedia output enable output low smwe smartmedia write enable output low sdram controller sdck sdram clock output sdcke sdram clock enable output high sdcs sdram controller chip select line output low ba[1:0] bank select output sdwe sdram write enable output low ras - cas row and column signal output low nwr[3:0] write signals output low nbs[3:0] byte mask signals output low sda10 sdram address 10 line output
138 AT91RM9200 1768b?atarm?08/03 the connection of some signals through the mux logic is not direct and depends on the mem- ory controller in use at the moment. table 38 below details the connections between the three memory controllers and the ebi pins. burst flash controller bfck burst flash clock output bfcs burst flash chip select line output low bfavd burst flash address valid signal output low bfbaa burst flash address advance signal output low bfoe burst flash output enable output low bfrdy burst flash ready signal input high bfwe burst flash write enable output low table 37. i/o lines description (continued) name function type active level table 38. ebi pins and memory controllers i/o line connections ebi pins sdramc i/o lines bfc i/o lines smc i/o lines nwr1/nbs1/cfior nbs1 not supported nwr1/nub a0/nbs0 not supported not supported a0/nlb a1 not supported a0 a1 a[11:2] a[9:0] a[10:1] a[11:2] sda10 a10 not supported not supported a12 not supported a11 a12 a[14:13] a[12:11] a[13:12] a[14:13] a[25:15] not supported a[24:14] a[25:15] d[31:16] d[31:16] not supported not supported d[15:0] d[15:0] d[15:0] d[15:0]
139 AT91RM9200 1768b?atarm?08/03 application example hardware interface table 39 below details the connections to be applied between the ebi pins and the external devices for each memory controller. table 39. ebi pins and external device connections pin pins of the interfaced device 8-bit static device 2 x 8-bit static devices 16-bit static device burst flash device sdram compactflash smartmedia or nand flash controller smc bfc sdramc smc d0 - d7 d0 - d7 d0 - d7 d0 - d7 d0 - d7 d0 - d7 d0 - d7 ad0 - ad7 d8 - d15 ? d8 - d15 d8 - d15 d8 - d15 d8 - d15 d8 - 15 ? d16 - d31 ? ? ? ? d16 - d31 ? ? a0/nbs0 a0 ? nlb ? dqm0 a0 ? a1/nwr2/nbs2 a1 a0 a0 a0 dqm2 a1 ? a2 - a9 a2 - a9 a1 - a8 a1 - a8 a1 - a8 a0 - a7 a2 - a9 ? a10 a10 a9 a9 a9 a8 a10 ? a11 a11 a10 a10 a10 a9 ? ? sda10 ? ? ? ? a10 ? ? a12 a12 a11 a11 a11 ? ? ? a13 - a15 a13 - a15 a12 - a14 a12 - a14 a12 - a14 a11 - a13 ? ? a16/ba0 a16 a15 a15 a15 ba0 ? ? a17/ba1 a17 a16 a16 a16 ba1 ? ? a18 - a20 a18 - a20 a17 - a19 a17 - a19 a17 - a19 ? ? ? a21 a21 a20 a20 a20 ? ? cle (4) a22 a22 a21 a21 a21 ? reg (3) ale (4) a23 - a24 a23 - a24 a22 - a23 a22 - a23 a22 - a23 ? ? ? a25 a25 a24 a24 a24 ? cfrnw (1) ? ncs0/bfcs cs cs cs cs ? ? ? ncs1/sdcs cs cs cs ? cs ? ? ncs2 cs cs cs ? ? ? ? ncs3/smcs cs cs c s ? ? ? ? ncs4/cfcs cs cs cs ? ? cfcs (1) ? ncs5/cfce1 cs cs cs ? ? ce1 ? ncs6/cfce2 cs cs cs ? ? ce2 ? nrd/noe/cfoe oe oe oe ? ? oe nwr0/nwe/cfwe we we (5) we ? ? we nwr1/nbs1/cfior we we (5) nub ? dqm1 ior ?
140 AT91RM9200 1768b?atarm?08/03 notes: 1. not directly connected to the compactflash slot. permits the control of the bidirectional buffer between the ebi data b us and the compactflash slot. 2. any pio line. 3. the reg signal of the compactflash can be driven by any of the following address bits: a24, a22 to a11. for details, see ?compactflash support? on page 143. 4. the cle and ale signals of the smartmedia device may be driven by any address bit. for details, see ?smartmedia and nand flash support? on page 146. 5. nwr1 enables upper byte writes. nwr0 enables lower byte writes. nwr3/nbs3/cfiow ? ? ? ? dqm3 iow ? bfck ? ? ? ck ? ? ? bfavd ? ? ? avd ? ? ? bfbaa/smwe ? ? ? baa ? ? we bfoe ? ? ? oe ? ? ? bfrdy/smoe ? ? ? rdy ? ? oe bfwe ? ? ? we ? ? ? sdck ? ? ? ? clk ? ? sdcke ? ? ? ? cke ? ? ras ? ? ? ? ras ? ? cas ? ? ? ? cas ? ? sdwe ? ? ? ? we ? ? nwait ??? ?? wait ? pxx (2) ? ? ? ? ? cd1 or cd2 ? pxx (2) ?? ? ? ? ? ce pxx (2) ?? ? ? ? ? rdy table 39. ebi pins and external device connections (continued) pin pins of the interfaced device 8-bit static device 2 x 8-bit static devices 16-bit static device burst flash device sdram compactflash smartmedia or nand flash controller smc bfc sdramc smc
141 AT91RM9200 1768b?atarm?08/03 connection examples figure 32 below shows an example of connections between the ebi and external devices. figure 32. ebi connections to memory devices ebi d0-d31 a2-a15 ras cas sdck sdcke sdwe a0/nbs0 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 nwr1/nbs1 a1/nwr2/nbs2 nwr3/nbs3 ncs1/sdcs d0-d7 d8-d15 a16/ba0 a17/ba1 a18-a25 a10 sda10 sda10 a2-a11, a13 ncs0/bfcs ncs2 ncs3 ncs4 ncs5 ncs6 ncs7 a16/ba0 a17/ba1 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 a10 sda10 a2-a11, a13 a16/ba0 a17/ba1 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 d16-d23 d24-d31 a10 sda10 a2-a11, a13 a16/ba0 a17/ba1 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 a10 sda10 a2-a11, a13 a16/ba0 a17/ba1 nbs0 nbs1 nbs3 nbs2 2m x 16 burst flash d0-d15 oe ce we nrd/noe nwr0/nwe a0-a20 avd rdy a1-a21 bfavd bfoe bfrdy bfclk bfwe 128k x 8 sram 128k x 8 sram d0-d7 d0-d7 a0-a16 a0-a16 a1-a17 a1-a17 d0-d15 cs cs oe we d0-d7 d8-d15 oe we nrd/noe a0/nwr0/nbs0 nrd/noe nwr1/nbs1 sdwe sdwe sdwe sdwe clk
142 AT91RM9200 1768b?atarm?08/03 product dependencies i/o lines the pins used for interfacing the external bus interface may be multiplexed with the pio lines. the programmer must first program the pio controller to assign the external bus interface pins to their peripheral function. if i/o lines of the external bus interface are not used by the application, they can be used for other purposes by the pio controller. functional description the ebi transfers data between the internal asb bus (handled by the memory controller) and the external memories or peripheral devices. it controls the waveforms and the parameters of the external address, data and control busses and is composed of the following elements: the static memory controller (smc) the sdram controller (sdramc) the burst flash controller (bfc) a chip select assignment feature that assigns an asb address space to the external devices. a multiplex controller circuit that shares the pins between the different memory controllers. programmable compactflash support logic programmable smartmedia and nand flash support logic bus multiplexing the ebi offers a complete set of control signals that share the 32-bit data lines, the address lines of up to 26 bits and the control signals through a multiplex logic operating in function of the memory area requests. multiplexing is specifically organized in order to guarantee the maintenance of the address and output control lines at a stable state while no external access is being performed. multi- plexing is also designed to respect the data float times defined in the memory controllers. furthermore, refresh cycles of the sdram are executed independently by the sdram con- troller without delaying the other external memor y controller accesses. lastly, it prevents burst accesses on the same page of a burst flash from being interrupted which avoids the need to restart a high-latency first access. pull-up control the ebi permits enabling of on-chip pull-up resistors on the data bus lines not multiplexed with the pio controller lines. the pull-up resistors are enabled after reset. setting the dbpuc bit disables the pull-up resistors on the d0 to d15 lines. enabling the pull-up resistor on the d16 - d31 lines can be performed by programming the appropriate pio controller. static memory controller for information on the static memory controller, refer to the smc ?overview? on page 151. sdram controller for information on the sdram controller, refer to the sdramc description on ?overview? on page 135. burst flash controller for information on the burst flash controller, refer to the bfc ?overview? on page 209.
143 AT91RM9200 1768b?atarm?08/03 compactflash support the external bus interface integrates circuitry that interfaces to compactflash devices. the compactflash logic is driven by the static memory controller (smc) on the ncs4 address space. programming the cs4a field of the chip select assignment register (see ?ebi chip select assignment register? on page 149.) to the appropriate value enables this logic. access to an external compactflash device is then made by accessing the address space reserved to ncs4 (i.e., between 0x5000 0000 and 0x5fff ffff). when multiplexed with cfce1 and cfce 2 signals, the ncs5 and ncs6 signals become unavailable. performing an access within the address space reserved to ncs5 and ncs6 (i.e., between 0x6000 0000 and 0x7fff ffff) may lead to an unpredictable outcome. the true ide mode is not supported and in i/o mode, the signal _iois16 is not managed. i/o mode, common memory mode and attribute memory mode within the ncs4 address space, the current transfer address is used to distinguish i/o mode, common memory mode and attribute memory mode. more precisely, the a23 bit of the trans- fer address is used to select i/o mode. any ebi address bit not required by the compactflash device (i.e., bit a24 or bits a22 to a11) can be used to separate common memory mode and attribute memory mode. using the a22 bit, for example, leads to the address map in figure 33 below. in this figure, ?i? stands for any hexadecimal digit. figure 33. address map example note: in the above example, the a22 pin of the ebi can be used to drive the reg signal of the com- pactflash device. read/write signals in i/o mode, the compactflash logic drives the read and write command signals of the smc on cfior and cfiow signals, while the cfoe and cfwe signals are deactivated. likewise, in common memory mode and attribute memory mode, the smc signals are driven on the cfoe and cfwe signals, while the cfior and cfiow are deactivated. figure 34 on page 144 demonstrates a schematic representation of this logic. attribute memory mode, common memory mode and i/o mode are supported by setting the address setup and hold time on the ncs4 chip select to the appropriate values. for details on these signal waveforms, please refer to the section: ?setup and hold cycles? on page 164 of the static memory controller documentation. 0x5i00 0000 0x5ibf ffff 0x5i80 0000 0x5i7f ffff common memory mode i/o mode attribute memory mode 0x5i40 0000 0x5i3f ffff a23 = 1 a22 = 0 a23 = 0 a22 = 1 a23 = 0 a22 = 0
144 AT91RM9200 1768b?atarm?08/03 figure 34. compactflash read/write control signals access type the cfce1 and cfce2 signals enable upper- and lower-byte access on the data bus of the compactflash device in accordance with table 40 below. the odd byte access on the d[7:0] bus is only possible when the smc is configured to drive 8-bit memory devices on the ncs4 pin. the chip select register (dbw field in ?smc chip select registers? on page 186) of the ncs4 address space must be set as shown in table 40 to enable the required access type. the cfce1 and cfce2 waveforms are identical to the ncs4 waveform. for details on these waveforms and timings, refer to the static memory controller ?overview? on page 151. multiplexing of compactflash signals on ebi pins table 41 below and table 42 on page 145 illustrate the multiplexing of the compactflash logic signals with other ebi signals on the ebi pins. the ebi pins in table 41 are strictly dedicated to the compactflash interface as soon as the cs4a field of the chip select assignment reg- ister is set (see ?ebi chip select assignment register? on page 149.). these pins must not be used to drive any other memory devices. the ebi pins in table 42 on page 145 remain shared between all memory areas when the compactflash interface is enabled (cs4a = 1). smc nrd_noe nwr0_nwe a23 cfior cfiow cfoe cfwe 1 1 1 1 compactflash logic external bus interface table 40. upper- and lower-byte access access cfce2 cfce1 a0 d[15:8] d[7:0] smc_csr4 (dbw) byte r/w access 1 0 0 don?t care/high z even byte 8-bit or 16-bit 1 0 1 don?t care/high z odd byte 8-bit odd byte r/w access 0 1 x odd byte don?t care/high z 16-bit half-word r/w access 0 0 x odd byte even byte 16-bit table 41. dedicated compactflash interface multiplexing pins cs4a = 1 cs4a = 0 compactflash signals ebi signals ncs4/cfcs cfcs ncs4 ncs5/cfce1 cfce1 ncs5 ncs6/cfce2 cfce2 ncs6
145 AT91RM9200 1768b?atarm?08/03 compactflash application example figure 35 below illustrates an example of a compactflash application. cfcs and cfrnw signals are not directly connected to the com pactflash slot, but do control the direction and the output enable of the buffers between the ebi and the compactflash device. the timing of the cfcs signal is identical to the ncs4 signal. moreover, the cfrnw signal remains valid throughout the transfer, as does the address bus. the compactflash _wait signal is con- nected to the nwait input of the static memory controller. for details on these waveforms and timings, refer to the static memory controller ?overview? on page 135. figure 35. compactflash application example table 42. shared compactflash interface multiplexing pins access to compactflash device access to other ebi devices compactflash signals ebi signals noe/nrd/cfoe cfoe nrd/noe nwr0/nwe/cfwe cfwe nwr0/nwe nwr1/nbs1/cfior cfior nwr1/nbs1 nwr3/nbs3/cfiow cfiow nwr3/nbs3 a25/cfrnw cfrnw a25 compactflash connector ebi d[15:0] /oe dir _cd1 _cd2 /oe d[15:0] a25/cfrnw ncs4/cfcs cd (pio) a[10:0] a22/reg noe/cfoe a[10:0] _reg _oe _we _iord _iowr _ce1 _ce2 nwe/cfwe nwr1/cfior nwr3/cfiow ncs5/cfe1 ncs6/cfe2 _wait nwait
146 AT91RM9200 1768b?atarm?08/03 smartmedia and nand flash support the ebi integrates circuitry that interfaces to smartmedia and nand flash devices. the smartmedia logic is driven by the static memory controller on the ncs3 address space. programming the cs3a field in the chip select assignment register to the appropriate value enables the smartmedia logic (see ?ebi chip select assignment register? on page 149.). access to an external smartmedia device is then made by accessing the address space reserved to ncs3 (i.e., between 0x4000 0000 and 0x4fff ffff). the smartmedia logic drives the read and write command signals of the smc on the smoe and smwe signals when the ncs3 signal is active. smoe and smwe are invalidated as soon as the transfer address fails to lie in the ncs3 address space. for details on these wave- forms, refer to the static memory controller ?overview? on page 151. the smwe and smoe signals are multiplexed with bfrdy and bfbaa signals of the burst flash controller. this multiplexing is controlled in the mux logic part of the ebi by the cs3a field of the chip select assignment register (see ?ebi chip select assignment register? on page 149.). this logic also controls the direction of the bfrdy/smoe pad. figure 36. smartmedia signal multiplexing on ebi pins the address latch enable and command latch enable signals on the smartmedia device are driven by address bits a22 and a21 of the ebi address bus. the user should note that any bit on the ebi address bus can also be used for this purpose. the command, address or data words on the data bus of the smartmedia devic e are distinguished by using their address within the ncs3 address space. the chip enable (ce) signal of the device and the ready/busy (r/b) signals are connected to pio lines. the ce signal then remains asserted even when ncs3 is not selected, preventing the device from returning to standby mode. some functional limitation with the supported burst flash device will occur when the smartmedia device is acti- vated due to the fact that the smoe and smwe signals are multiplexed with bfrdy and bfbaa signals respectively. smc nrd_noe nwr0_nwe smoe smwe smartmedia logic ncs3 mux logic ebi user interface cs3a bfc bfrdy bfbaa bfbaa_smwe bfrdy_smoe
147 AT91RM9200 1768b?atarm?08/03 figure 37. smartmedia application example d[7:0] ale bfbaa/smwe bfrdy/smoe noe nwe a[22:21] cle ad[7:0] pio r/b ebi ce smartmedia pio ncs3/smcs not connected
148 AT91RM9200 1768b?atarm?08/03 external bus interface (ebi) user interface AT91RM9200 ebi user interface base address: 0xffff ff60 table 43. external bus interface memory map offset register name access reset state 0x00 chip select assignment register ebi_csa read/write 0x0 0x04 configuration register ebi_cfgr read/write 0x0 0x08 reserved ? 0x0c reserved ? 0x10 - 0x2c smc user interface see ?static memory controller (smc) user interface? on page 185 0x30 - 0x5c sdramc user interface see ?sdram controller (sdramc) user interface? on page 201. 0x60 bfc user interface see ?burst flash controller (bfc) user interface? on page 221. 0x64 - 0x9c reserved
149 AT91RM9200 1768b?atarm?08/03 ebi chip select assignment register register name: ebi_csa access type: read/write reset value: 0x0 offset: 0x0 absolute address: 0xffff ff60 cs0a: chip select 0 assignment 0 = chip select 0 is assigned to the static memory controller. 1 = chip select 0 is assigned to the burst flash controller. cs1a: chip select 1 assignment 0 = chip select 1 is assigned to the static memory controller. 1 = chip select 1 is assigned to the sdram controller. cs3a: chip select 3 assignment 0 = chip select 3 is only assigned to the static memory controller and ncs3 behaves as defined by the smc. 1 = chip select 3 is assigned to the static memory controller and the smartmedia logic is activated. cs4a: chip select 4 assignment 0 = chip select 4 is assigned to the static memory controller and ncs4, ncs5 and ncs6 behave as defined by the smc. 1 = chip select 4 is assigned to the static memory controller and the compactflash logic is activated. accessing the address space reserved to ncs5 and ncs6 may lead to an unpredictable outcome. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ? cs4a cs3a ? cs1a cs0a
150 AT91RM9200 1768b?atarm?08/03 ebi configurat ion register register name: ebi_cfgr access type: read/write reset value: 0x0 offset: 0x04 absolute address: 0xffff ff64 dbpuc: data bus pull-up configuration 0 = [d15:0] data bus bits are internally pulled-up to the vddiom power supply. 1 = [d15:0] data bus bits are not internally pulled-up. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????? dbpuc
151 AT91RM9200 1768b?atarm?08/03 static memory controller (smc) overview the static memory controller (smc) generates the signals that control the access to external static memory or peripheral devices. the smc is fully programmable and can address up to 512m bytes. it has eight chip selects and a 26-bit address bus. the 16-bit data bus can be configured to interface with 8- or 16-bit external devices. separate read and write control sig- nals allow for direct memory and peripheral interfacing. the smc supports different access protocols allowing single clock cycle memory accesses. it also provides an external wait request capability. the main features of the smc are: external memory mapping, 512-mbyte address space up to 8 chip select lines 8- or 16-bit data bus remap of boot memory multiple access modes supported ? byte write or byte select lines ? two different read protocols for each memory bank multiple device adaptability ? compliant with lcd module ? programmable setup time read/write ? programmable hold time read/write multiple wait state management ? programmable wait state generation ? external wait request ? programmable data float time
152 AT91RM9200 1768b?atarm?08/03 block diagram figure 38. static memory controller block diagram multiplexed signals are listed in table 45 with their functions. table 44. i/o lines description name description type active level ncs[7:0] static memory controller chip select lines output low nrd/noe read/output enable signal output low nwr0/nwe write 0/write enable signal output low nwr1/nub write1/upper byte select signal output low a0/nlb address bit 0/lower byte select signal output low a[25:1] address bus output d[15:0] data bus i/o nwait external wait signal input low table 45. static memory controller multiplexed signals multiplexed signals related function a0 nlb 8-bit or 16-bit data bus, see ?data bus width? on page 155. nrd noe byte-write or byte-select access, see ?write access type? on page 156. nwr0 nwe byte-write or byte-select access, see ?write access type? on page 156. nwr1 nub byte-write or byte-select access, see ?write access type? on page 156. apb ncs[7:0] nwr0/nwe smc pio controller nwr1/nub nrd/noe a0/nlb a[25:1] d[15:0] nwait user interface pmc mck memory controller smc chip select
153 AT91RM9200 1768b?atarm?08/03 application example hardware interface figure 39 shows an example of static memory device connection to the smc. figure 39. smc connections to static memory devices product dependencies i/o lines the pins used for interfacing the static memory controller may be multiplexed with the pio lines. the programmer must first program the pio controller to assign the static memory con- troller pins to their peripheral function. if i/o lines of the static memory controller are not used by the application, they can be used for other purposes by the pio controller. static memory controller d0-d15 a1-a25 a0/nlb nwr1/nub ncs1 ncs0 ncs2 ncs3 ncs4 ncs5 ncs6 ncs7 nrd/noe nwr0/nwe 128k x 8 sram 128k x 8 sram d0-d7 d0-d7 a0-a16 a0-a16 a1-a17 a1-a17 cs cs oe we d0-d7 d8-d15 oe we nrd/noe nwr0/nwe nrd/noe nwr1/nub
154 AT91RM9200 1768b?atarm?08/03 functional description external memory interface external memory mapping the memory map is defined by hardware and associates the internal 32-bit address space with the external 26-bit address bus. note that a[25:0] is only significant for 8-bit memory. a[25:1] is used for 16-bit memory. if the physical memory device is smaller than the page size, it wraps around and appears to be repeated within the page. the smc correctly handles any valid access to the memory device within the page. see figure 40. figure 40. case of an external memory smaller than page size chip select lines the static memory controller provides up to eight chip select lines: ncs0 to ncs7. figure 41. memory connections for eight external devices (1) note: 1. the maximum address space per device is 512m bytes 1m byte device 1m byte device 1m byte device 1m byte device memory map hi low hi low hi low hi low base base + 1m byte base + 2m bytes base + 3m bytes base + 4m bytes repeat 1 repeat 2 repeat 3 nrd nwr[1:0] a[25:0] d[15:0] 8 or 16 memory enable memory enable memory enable memory enable memory enable memory enable memory enable memory enable output enable write enable a[25:0] d[15:0] or d[7:0] ncs3 ncs0 ncs1 ncs2 ncs7 ncs4 ncs5 ncs6 ncs[7:0] smc
155 AT91RM9200 1768b?atarm?08/03 data bus width a data bus width of 8 or 16 bits can be selected for each chip select. this option is controlled by the dbw field in the smc_csr for the corresponding chip select. see ?smc chip select registers? on page 186. figure 42 shows how to connect a 512k x 8-bit memory on ncs2 (dbw = 10). figure 42. memory connection for an 8-bit data path device figure 43 shows how to connect a 512k x 16-bit memory on ncs2 (dbw = 01). figure 43. memory connection for a 16-bit data path device smc a0 nwr0 nrd ncs2 a0 write enable output enable memory enable nwr1 d[7:0] d[7:0] d[15:8] a[25:1] a[25:1] smc nlb nwe noe ncs2 low byte enable write enable output enable memory enable nub high byte enable d[7:0] d[7:0] d[15:8] d[15:8] a[25:1] a[24:0]
156 AT91RM9200 1768b?atarm?08/03 write access write access type each chip select with a 16-bit data bus can operate with one of two different types of write access: byte write access supports two byte write and a single read signal. byte select access selects upper and/or lower byte with two byte select lines, and separate read and write signals. this option is controlled by the bat field in the smc_csr for the corresponding chip select. see ?smc chip select registers? on page 186. byte write access byte write access is used to connect 2 x 8-bit devices as a 16-bit memory page. the signal a0/nlb is not used. the signal nwr1/nub is used as nwr1 and enables upper byte writes. the signal nwr0/nwe is used as nwr0 and enables lower byte writes. the signal nrd/noe is used as nrd and enables half-word and byte reads. figure 44 shows how to connect two 512k x 8-bit devices in parallel on ncs2 (bat = 0) figure 44. memory connection for 2 x 8-bit data path devices byte select access byte select access is used to connect 16-bit devices in a memory page. the signal a0/nlb is used as nlb and enables the lower byte for both read and write operations. the signal nwr1/nub is used as nub and enables the upper byte for both read and write operations. the signal nwr0/nwe is used as nwe and enables writing for byte or half-word. the signal nrd/noe is used as noe and enables reading for byte or half-word. smc a0 nwr0 nrd ncs2 write enable read enable memory enable nwr1 write enable read enable memory enable d[7:0] d[7:0] d[15:8] d[15:8] a[24:1] a[18:0] a[18:0]
157 AT91RM9200 1768b?atarm?08/03 figure 45 shows how to connect a 16-bit device with byte and half-word access (e.g., sram device type) on ncs2 (bat = 1). figure 45. connection to a 16-bit data path device with byte and half-word access figure 46 shows how to connect a 16-bit device without byte access (e.g., flash device type) on ncs2 (bat = 1). figure 46. connection to a 16-bit data path device without byte write capability smc nlb nwe noe ncs2 low byte enable write enable output enable memory enable nub high byte enable d[7:0] d[7:0] d[15:8] d[15:8] a[19:1] a[18:0] smc d[7:0] d[7:0] d[15:8] d[15:8] a[19:1] nlb nwe noe ncs2 write enable output enable memory enable nub a[18:0]
158 AT91RM9200 1768b?atarm?08/03 write data hold time during write cycles, data output becomes valid after the rising edge of mck and remains valid after the rising edge of nwe. during a write access, the data remain on the bus 1/2 period of mck after the rising edge of nwe. see figure 47 and figure 48. figure 47. write access with 0 wait state figure 48. write access with 1 wait state a[25:0] ncs2 mck nwe d[15:0] a[25:0] ncs2 nwe mck d[15:0]
159 AT91RM9200 1768b?atarm?08/03 read access read protocols the smc provides two alternative protocols for external memory read accesses: standard and early read. the difference between the two protocols lies in the behavior of the nrd signal. for write accesses, in both protocols, nwe has the same behavior. in the second half of the master clock cycle, nwe always goes low (see figure 56 on page 164). the protocol is selected by the drp field in smc_csr (see ?smc chip select registers? on page 186.). standard read protocol is the default protocol after reset. note: in the following waveforms and descriptions, nrd represents nrd as well as noe since the two signals have the same waveform. likewise, nwe represents nwe, nwr0 and nwr1 unless nwr0 and nwr1 are otherwise represented. in addition, ncs represents ncs[7:0] (see ?i/o lines? on page 153, table 44 and table 45). standard read protocol standard read protocol implements a read cycle during which nrd and nwe are similar. both are active during the second half of the clock cycle. the first half of the clock cycle allows time to ensure completion of the previous access as well as the output of address lines and ncs before the read cycle begins. during a standard read protocol, ncs is set low and address lines are valid at the beginning of the external memory access, while nrd goes low only in the second half of the master clock cycle to avoid bus conflict. see figure 49. figure 49. standard read protocol a[25:0] ncs mck nrd d[15:0]
160 AT91RM9200 1768b?atarm?08/03 early read protocol early read protocol provides more time for a read access from the memory by asserting nrd at the beginning of the clock cycle. in the case of successive read cycles in the same memory, nrd remains active continuously. since a read cycle normally limits the speed of operation of the external memory system, early read protocol can allow a faster clock frequency to be used. however, an extra wait state is requir ed in some cases to avoid contentions on the external bus. figure 50. early read protocol a[25:0] ncs mck nrd d[15:0]
161 AT91RM9200 1768b?atarm?08/03 wait state management the smc can automatically insert wait states. the different types of wait states managed are listed below: standard wait states external wait states data float wait states chip select change wait states early read wait states standard wait states each chip select can be programmed to insert one or more wait states during an access on the corresponding memory area. this is done by setting the wsen field in the corresponding smc_csr (see ?smc chip select registers? on page 186.). the number of cycles to insert is programmed in the nws field in the same register. below is the correspondence between the number of standard wait states programmed and the number of clock cycles during which the nwe pulse is held low: 0 wait states 1/2 clock cycle 1 wait state 1 clock cycle for each additional wait state programmed, an additional cycle is added. figure 51. one standard wait state access notes: 1. early read protocol 2. standard read protocol external wait states the nwait input pin is used to insert wait states beyond the maximum standard wait states programmable or in addition to. if nwait is asserted low, then the smc adds a wait state and no changes are made to the output signals, the internal counters or the state. when nwait is de-asserted, the smc completes the access sequence. the input of the nwait signal is an asynchronous input. to avoid any metastability problems, nwait is synchronized before using it. this operation results in a two-cycle delay. nws must be programmed as a function of synchronization time and delay between nwait falling and control signals falling (nrd/nwe), otherwise smc will not function correctly. if nwait is asserted during a setup or hold timing, the smc does not function correctly. a[25:0] ncs nwe mck 1 wait state access nrd (1) (2) nws wait delay from nrd/nwe external_nwait synchronization delay 1 ++ >
162 AT91RM9200 1768b?atarm?08/03 figure 52. nwait behaviour in read access notes: 1. early read protocol 2. standard read protocol figure 53. nwait behaviour in write access data float wait states some memory devices are slow to release the external bus. for such devices, it is necessary to add wait states (data float wait states) after a read access before starting a write access or a read access to a different external memory. the data float output time (t df ) for each external memory device is programmed in the tdf field of the smc_csr register for the corresponding chip select (see ?smc chip select reg- isters? on page 186.). the value of tdf indicates the number of data float wait cycles (between 0 and 15) to be inserted and represents the time allowed for the data output to go to high impedance after the memory is disabled. data float wait states do not delay internal memory accesses. hence, a single access to an external memory with long t df will not slow down the execution of a program from internal memory. a[25:0] nwait nwait internally synchronized nrd ncs (1) (2) wait delay from nrd nwait synchronization delay mck a[25:0] nwait nwait internally synchronized nwe d[15:0] wait delay from nwe nwait synchronization delay mck
163 AT91RM9200 1768b?atarm?08/03 to ensure that the external memory system is not accessed while it is still busy, the smc keeps track of the programmed external data float time during internal accesses. internal memory accesses and consecutive read accesses to the same external memory do not add data float wait states. figure 54. data float output delay notes: 1. early read protocol 2. standard read protocol chip select change wait state a chip select wait state is automatically inserted when consecutive accesses are made to two different external memories (if no other type of wait state has already been inserted). if a wait state has already been inserted (e.g., data float wait state), then no more wait states are added. figure 55. chip select wait state notes: 1. early read protocol 2. standard read protocol a[25:0] nrd d[15:0] mck t df (1) (2) ncs ncs1 ncs2 mck mem 1 chip select wait mem 2 nrd nwe (1) (2) a[25:0] addr mem 1 addr mem 2
164 AT91RM9200 1768b?atarm?08/03 early read wait state in early read protocol, an early read wait state is automatically inserted when an external write cycle is followed by a read cycle to allow time for the write cycle to end before the subsequent read cycle begins (see figure 56). this wait state is generated in addition to any other pro- grammed wait states (i.e., data float wait state). no wait state is added when a read cycle is followed by a write cycle, between consecutive accesses of the same type, or between external and internal memory accesses. figure 56. early read wait states setup and hold cycles the smc allows some memory devices to be interfaced with different setup, hold and pulse delays. these parameters are programmable and define the timing of each portion of the read and write cycles. however, it is not possible to use this feature in early read protocol. if an attempt is made to program the setup parameter as not equal to zero and the hold parameter as equal to zero with wsen = 0 (0 standard wait state), the smc does not operate correctly. if consecutive accesses are made to two different external memories and the second memory is programmed with setup cycles, then no chip select change wait state is inserted (see figure 61 on page 166). when a data float wait state (t df ) is programmed on the first memory bank and when the sec- ond memory bank is programmed with setup cycles, the smc behaves as follows: if the number of t df is higher or equal to the number of setup cycles, the number of setup cycles inserted is equal to 0 (see figure 62 on page 167). if the number of the setup cycle is higher than the number of t df, the number of t df inserted is 0 (see figure 63 on page 167). read access the read cycle can be divided into a setup, a pulse length and a hold. the setup parameter can have a value between 1.5 and 7.5 clock cycles, the hold parameter between 0 and 7 clock cycles and the pulse length between 1.5 and 128.5 clock cycles, by increments of one. a[25:0] ncs nwe mck write cycle early read wait read cycle nrd d[15:0]
165 AT91RM9200 1768b?atarm?08/03 figure 57. read access with setup and hold figure 58. read access with setup write access the write cycle can be divided into a setup, a pulse length and a hold. the setup parameter can have a value between 1.5 and 7.5 clock cycles, the hold parameter between 0.5 and 7 clock cycles and the pulse length between 1 and 128 clock cycles by increments of one. figure 59. write access with setup and hold nrd setup pulse length nrd a[25:0] nrd hold mck nrd setup pulse length nrd a[25:0] mck nwr setup pulse length nwe a[25:0] nwr hold d[15:0] mck
166 AT91RM9200 1768b?atarm?08/03 figure 60. write access with setup data float wait states with setup cycles figure 61. consecutive accesses with setup programmed on the second access nwr setup pulse length nwe a[25:0] nwr hold d[15:0] mck setup ncs1 a[25:0] mck ncs2 nrd nwe
167 AT91RM9200 1768b?atarm?08/03 figure 62. first access with data float wait states (tdf = 2) and second access with setup (nrdsetup = 1) figure 63. first access with data float wait states (tdf = 2) and second access with setup (nrdsetup = 3) setup ncs1 a[25:0] mck ncs2 d[15:0] nrd data float time setup ncs1 a[25:0] mck ncs2 d[15:0] nrd data float time
168 AT91RM9200 1768b?atarm?08/03 lcd interface mode the smc can be configured to work with an external liquid crystal display (lcd) controller by setting the acss (address to chip select setup) bit in the smc_csr registers (see ?smc chip select registers? on page 186.). in lcd mode, ncs is shortened by one/two/three clock cycles at the leading and trailing edges, providing positive address setup and hold. for read accesses, the data is latched in the smc when ncs is raised at the end of the access. additionally, wsen must be set and nws programmed with a value of two or more superior to acss. in lcd mode, it is not recommended to use rwhold or rwsetup. if the above con- ditions are not satisfied, smc does not operate correctly. figure 64. read access in lcd interface mode figure 65. write access in lcd interface mode nrd a[25:0] ncs data from lcd controller acss acss = 3, nwen = 1, nws = 10 acss mck nwe a[25:0] accs = 2, nwen = 1, nws = 10 accs accs ncs d[15:0] mck
169 AT91RM9200 1768b?atarm?08/03 memory access waveforms read accesses in standard and early protocols figure 66 on page 169 through figure 69 on page 172 show examples of the alternatives for external memory read protocol. figure 66. standard read protocol without t df read mem 1 write mem 1 read mem 1 read mem 2 write mem 2 read mem 2 chip select change wait a[25:0] nrd nwe ncs1 ncs2 d[15:0] (mem 1) d[15:0] (mem 2) d[15:0] (to write) mck t whdx t whdx
170 AT91RM9200 1768b?atarm?08/03 figure 67. early read protocol without t df read mem 1 write mem 1 early read wait cycle read mem 1 read mem 2 write mem 2 early read wait cycle read mem 2 chip select change wait long t whdx a[25:0] nrd nwe ncs1 ncs2 d[15:0] (mem 1) d[15:0] (mem 2) d[15:0] (to write) mck t whdx
171 AT91RM9200 1768b?atarm?08/03 figure 68. standard read protocol with t df read mem 1 write mem 1 data float wait read mem 1 data float wait read mem 2 read mem 2 data float wait write mem 2 write mem 2 t whdx t df t df t df a[25:0] nrd nwe ncs1 ncs2 d[15:0] (mem 1) d[15:0] (mem 2) d[15:0] mck (t df = 2) (t df = 1) (t df = 1 ) (to write)
172 AT91RM9200 1768b?atarm?08/03 figure 69. early read protocol with t df read mem 1 write mem 1 data float wait early read wait read mem 1 data float wait read mem 2 read mem 2 data float wait write mem 2 write mem 2 t df t df t df a[25:0] nrd nwe ncs1 ncs2 d[15:0] (mem 1) d[15:0] (mem 2) d[15:0] mck (t df = 2) (to write)
173 AT91RM9200 1768b?atarm?08/03 accesses with setup and hold figure 70 and figure 71 show an example of read and write accesses with setup and hold cycles. figure 70. read accesses in standard read protocol with setup and hold (1) note: 1. read access memory data bus width = 8, rwsetup = 1, rwhold = 1,wsen= 1, nws = 0 figure 71. write accesses with setup and hold (1) note: 1. write access, memory data bus width = 8, rwsetup = 1, rwhold = 1, wsen = 1, nws = 0 mck a[25:1] a0/nlb nrd/noe nwr0/nwe nwr1/nub ncs d[15:0] 00d2b 00028 00d2c e59f zz01 zz02 hold setup setup hold mck a[25:1] a0/nlb nrd/noe nwr0/nwe nwr1/nub ncs d[15:0] 008cb 00082 008cc 3000 e3a0 0605 0606 setup hold setup hold
174 AT91RM9200 1768b?atarm?08/03 accesses using nwait input signal figure 72 on page 174 through figure 75 on page 177 show examples of accesses using nwait. figure 72. write access using nwait in byte select type access (1) note: 1. write access memory, data bus width = 16 bits, wsen = 1, nws = 6 a[25:1] nrd/noe nwr0/nwe a0/nlb nwr1/nub ncs d[15:0] mck nwait nwait internally synchronized 000008a 1312 wait delay falling from nwr0/nwe chip select wait
175 AT91RM9200 1768b?atarm?08/03 figure 73. write access using nwait in byte write type access (1) note: 1. write access memory, data bus width = 16 bits, wsen = 1, nws = 5 a[25:1] nrd/noe nwr0/nwe a0/nlb nwr1/nub ncs d[15:0] mck nwait nwait internally synchronized 000008c 1716 wait delay falling from nwr0/nwe/nwr1/nub chip select wait
176 AT91RM9200 1768b?atarm?08/03 figure 74. write access using nwait (1) note: 1. write access memory, data bus width = 8 bits, wsen = 1, nws = 4 ncs a[25:1] nrd/noe nwr0/nwe a0/nlb nwr1/nub d[15:0] mck nwait nwait internally synchronized 0000033 0403 wait delay falling from nwr0/nwe chip select wait
177 AT91RM9200 1768b?atarm?08/03 figure 75. read access in standard protocol using nwait (1) note: 1. read access, memory data bus width = 16, nws = 5, wsen = 1 memory access example waveforms figure 76 on page 178 through figure 82 on page 184 show the waveforms for read and write accesses to the various associated external memory devices. the configurations described are shown in table 46. ncs a[25:1] nrd/noe nwr0/nwe a0/nlb nwr1/nub d[15:0] mck nwait nwait internally synchronized 0002c44 0003 wait delay falling from nrd/noe table 46. memory access waveforms figure number number of wait states bus width size of data transfer figure 76 0 16 word figure 77 1 16 word figure 78 1 16 half-word figure 79 0 8 word figure 80 1 8 half-word figure 81 1 8 byte figure 82 0 16 byte
178 AT91RM9200 1768b?atarm?08/03 figure 76. 0 wait state, 16-bit bus width, word transfer b 2 b 1 b 4 b 3 b 2 b 1 b 4 b 3 b 2 b 1 b 4 b 3 mck ncs nrd read access nrd write access nwe d[15:0] nlb nub standard read protocol early read protocol byte write/ byte select option d[15:0] d[15:0] a[25:1] addr addr+1
179 AT91RM9200 1768b?atarm?08/03 figure 77. 1 wait state, 16-bit bus width, word transfer b 2 b 1 b 4 b 3 1 wait state 1 wait state b 4 b 3 b 2 b 1 b 4 b 3 b 2 b 1 mck ncs nrd read access nrd write access nwe d[15:0] nlb nub standard read protocol early read protocol byte write/ byte select option d[15:0] d[15:0] a[25:1] addr addr+1
180 AT91RM9200 1768b?atarm?08/03 figure 78. 1 wait state, 16-bit bus width, half-word transfer b 2 b 1 1 wait state b 2 b 1 b 2 b 1 mck ncs nrd read access nrd write access nwe d[15:0] nlb nub standard read protocol early read protocol byte write/ byte select option d[15:0] d[15:0] a[25:1]
181 AT91RM9200 1768b?atarm?08/03 figure 79. 0 wait state, 8-bit bus width, word transfer addr x b 1 addr+2 addr+3 x b 2 x b 3 x b 4 x b 1 x b 2 x b 3 x b 4 x b 1 x b 2 x b 3 x b 4 addr+1 mck ncs nrd read access nrd write access nwr1 d[15:0] standard read protocol early read protocol d[15:0] d[15:0] a[25:0] nwr0
182 AT91RM9200 1768b?atarm?08/03 figure 80. 1 wait state, 8-bit bus width, half-word transfer addr x b 1 1 wait state addr+1 1 wait state x b 2 x b 1 x b 2 x b 1 x b 2 mck ncs nrd read access nrd write access nwr1 d[15:0] standard read, protocol early read protocol d[15:0] d[15:0] a[25:0] nwr0
183 AT91RM9200 1768b?atarm?08/03 figure 81. 1 wait state, 8-bit bus width, byte transfer xb 1 1 wait state x b 1 x b 1 mck ncs nrd read access nrd write access nwr1 d[15:0] standard read protocol early read protocol d[15:0] d[15:0] a[25:0] nwr0
184 AT91RM9200 1768b?atarm?08/03 figure 82. 0 wait state, 16-bit bus width, byte transfer x b 1 b 2 x addr x x x 0 addr x x x 0 addr x x x 0 addr x x x 1 xb 1 b 2 x b 1 b 1 b 2 b 2 mck ncs nrd read access nrd write access nwr1 d[15:0] standard read protocol early read protocol d[15:0] d[15:0] a[25:1] nwr0 byte write option byte select option internal address bus nlb nub nwe
185 AT91RM9200 1768b?atarm?08/03 static memory controller (smc) user interface the static memory controller is programmed using the regi sters listed in table 47. eight chip select registers (smc_csr0 to smc_csr7) are used to program the parameters for the individual external memories. table 47. static memory controller register mapping offset register name access reset state 0x00 smc chip select register 0 smc_csr0 read/write 0x00002000 0x04 smc chip select register 1 smc_csr1 read/write 0x00002000 0x08 smc chip select register 2 smc_csr2 read/write 0x00002000 0x0c smc chip select register 3 smc_csr3 read/write 0x00002000 0x10 smc chip select register 4 smc_csr4 read/write 0x00002000 0x14 smc chip select register 5 smc_csr5 read/write 0x00002000 0x18 smc chip select register 6 smc_csr6 read/write 0x00002000 0x1c smc chip select register 7 smc_csr7 read/write 0x00002000
186 AT91RM9200 1768b?atarm?08/03 smc chip select registers register name: smc_csr0..smc_csr7 access type: read/write reset value: see table 47 on page 185 nws: number of wait states this field defines the read and write signal pulse length from 1 cycle up to 128 cycles. note: when wsen is 0, nws will be read to 0 whichever the previous programmed value should be. wsen: wait state enable 0: wait states are disabled. 1: wait states are enabled. tdf: data float time the external bus is marked occupied and cannot be used by another chip select during tdf cycles. up to 15 cycles can be defined. bat: byte access type this field is used only if dbw defines a 16- or 32-bit data bus. 0: chip select line is connected to two 8-bit wide devices or four 8-bit wide devices. 1: chip select line is connected to a 16-bit wide device. dbw: data bus width drp: data read protocol 0: standard read protocol is used. 1: early read protocol is used. 31 30 29 28 27 26 25 24 ? rwhold ? rwsetup 23 22 21 20 19 18 17 16 ?????? acss 15 14 13 12 11 10 9 8 drp dbw bat tdf 76543210 wsen nws dbw data bus width 0 0 reserved (32-bit) 0116-bit 108-bit 11reserved
187 AT91RM9200 1768b?atarm?08/03 acss: address to chip select setup rwsetup: read and write signal setup time see definition and description below. rwhold: read and write signal hold time see definition and description below notes: 1. in standard read protocol. 2. in early read protocol. (it is not possible to use the parameters rwsetup or rwhold in this mode) notes: 1. for a visual description, please refer to ?setup and hold cycles? on page 164 and the diagrams in figure xx and figure yy and figure zz. 2. wsen is considered to be 1. acss chip select waveform 0 0 standard, asserted at the beginning of the access and deasserted at the end. 0 1 one cycle less at the beginning and the end of the access. 1 0 two cycles less at the beginning and the end of the access. 1 1 three cycles less at the beginning and the end of the access. rwsetup nrd setup nwr setup rwhold nrd hold nwr hold 000? cycle (1) or 0 cycles (2) ? cycle 0 0 0 0 ? cycle 0 0 1 1 + ? cycles 1 + ? cycles 0 0 1 1 cycles 1 cycle 0 1 0 2 + ? cycles 2 + ? cycles 0 1 0 2 cycles 2 cycles 0 1 1 3 + ? cycles 3 + ? cycles 0 1 1 3 cycles 3 cycles 1 0 0 4 + ? cycles 4 + ? cycles 1 0 0 4 cycles 4 cycles 1 0 1 5 + ? cycles 5 + ? cycles 1 0 1 5 cycles 5 cycles 1 1 0 6 + ? cycles 6 + ? cycles 1 1 0 6 cycles 6 cycles 1 1 1 7 + ? cycles 7 + ? cycles 1 1 1 7 cycles 7 cycles nws (2) nrd pulse length nwr pulse length 0 1 + ? cycles 1 cycles 1 2 + ? cycles 2 cycles up to x = 127 x + 1+ ? cycles x + 1 cycle
188 AT91RM9200 1768b?atarm?08/03 figure 83. read/write setup figure 84. read hold figure 85. write hold nrd/noe a[25:0] mck rwsetup nwe nrd/noe a[25:0] mck rwhold nwe a[25:0] mck rwhold d[15:0]
189 AT91RM9200 1768b?atarm?08/03 sdram controller (sdramc) overview the sdram controller (sdramc) extends the memory capabilities of a chip by providing the interface to an external 16-bit or 32-bit sd ram device. the page size supports ranges from 2048 to 8192 and the number of columns from 256 to 2048. it supports byte (8-bit), half-word (16-bit) and word (32-bit) accesses. the sdram controller supports a read or write burst length of one location. it does not sup- port byte read/write bursts or half-word write bursts. it keeps track of the active row in each bank, thus maximizing sdram performance, e.g., the application may be placed in one bank and data in the other banks. so as to optimize performance, it is advisable to avoid accessing different rows in the same bank. features of the sdramc are: numerous configurations supported ? 2k, 4k, 8k row address memory parts ? sdram with two or four internal banks ? sdram with 16- or 32-bit data path programming facilities ? word, half-word, byte access ? automatic page break when memory boundary has been reached ? multibank ping-pong access ? timing parameters specified by software ? automatic refresh operation, refresh rate is programmable energy-saving capabilities ? self-refresh and low-power modes supported error detection ? refresh error interrupt sdram power-up initialization by software latency is set to two clocks (cas latency of 1, 3 not supported) auto precharge command not used
190 AT91RM9200 1768b?atarm?08/03 block diagram figure 86. sdram controller block diagram i/o lines description memory controller apb sdramc interrupt sdck sdcs a[12:0] sdramc pio controller ba[1:0] sdcke ras cas sdwe nbs[3:0] user interface pmc mck d[31:0] sdramc chip select table 48. i/o line description name description type active level sdck sdram clock output sdcke sdram clock enable output high sdcs sdram controller chip select output low ba[1:0] bank select signals output ras row signal output low cas column signal output low sdwe sdram write enable output low nbs[3:0] data mask enable signals output low a[12:0] address bus output d[31:0] data bus i/o
191 AT91RM9200 1768b?atarm?08/03 application example hardware interface figure 87 shows an example of sdram device connection to the sdram controller by using a 32-bit data bus width. figure 88 shows an example of sdram device connection by using a 16-bit data bus width. care should be taken, as these examples are given for a direct connec- tion of the devices to the sdram controller, without external bus interface, nor pio controller multiplexing. figure 87. sdram controller connections to sdram devices: 32-bit data bus width figure 88. sdram controller connections to sdram devices: 16-bit data bus width sdram controller d0-d31 a0-a12 ras cas sdck sdcke sdwe nbs0 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 nbs1 nbs2 nbs3 sdcs d0-d7 d8-d15 ba0 ba1 a10 a10 a0-a9, a11 ba0 ba1 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 a10 a10 a0-a9, a11 ba0 ba1 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 d16-d23 d24-d31 a10 a10 a0-a9, a11 ba0 ba1 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 a10 a10 a0-a9, a11 ba0 ba1 nbs0 nbs1 nbs3 nbs2 sdwe sdwe sdwe sdwe sdram controller d0-d31 a0-a12 ras cas sdck sdcke sdwe nbs0 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 nbs1 sdcs d0-d7 d8-d15 ba0 ba1 a10 a10 a0-a9, a11 ba0 ba1 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 a10 a10 a0-a9, a11 ba0 ba1 nbs0 nbs1 sdwe sdwe
192 AT91RM9200 1768b?atarm?08/03 software interface the sdram controller?s function is to make the sdram device access protocol transparent to the user. table 49 to table 54 illustrate the sdram device memo ry mapping therefore seen by the user in correlation with the device structure. various configurations are illustrated. 32-bit memory data bus width notes: 1. m[1:0] is the byte address inside a 32-bit word. 2. bk[1] = ba1, bk[0] = ba0. table 49. sdram configuration mapping: 2k rows, 256/512/1024/2048 columns cpu address line 2726252423222120191817161514131211109876543210 bk[1:0] row[10:0] column[7:0] m[1:0] bk[1:0] row[10:0] column[8:0] m[1:0] bk[1:0] row[10:0] column[9:0] m[1:0] bk[1:0] row[10:0] column[10:0] m[1:0] table 50. sdram configuration mapping: 4k rows, 256/512/1024/2048 columns cpu address line 2726252423222120191817161514131211109876543210 bk[1:0] row[11:0] column[7:0] m[1:0] bk[1:0] row[11:0] column[8:0] m[1:0] bk[1:0] row[11:0] column[9:0] m[1:0] bk[1:0] row[11:0] column[10:0] m[1:0] table 51. sdram configuration mapping: 8k rows, 256/512/1024/2048 columns cpu address line 2726252423222120191817161514131211109876543210 bk[1:0] row[12:0] column[7:0] m[1:0] bk[1:0] row[12:0] column[8:0] m[1:0] bk[1:0] row[12:0] column[9:0] m[1:0] bk[1:0] row[12:0] column[10:0] m[1:0]
193 AT91RM9200 1768b?atarm?08/03 16-bit memory data bus width notes: 1. m0 is the byte address inside a 16-bit half-word. 2. bk[1] = ba1, bk[0] = ba0. table 52. sdram configuration mapping: 2k rows, 256/512/1024/2048 columns cpu address line 2726252423222120191817161514131211109876543210 bk[1:0] row[10:0] column[7:0] m0 bk[1:0] row[10:0] column[8:0] m0 bk[1:0] row[10:0] column[9:0] m0 bk[1:0] row[10:0] column[10:0] m0 table 53. sdram configuration mapping: 4k rows, 256/512/1024/2048 columns cpu address line 2726252423222120191817161514131211109876543210 bk[1:0] row[11:0] column[7:0] m0 bk[1:0] row[11:0] column[8:0] m0 bk[1:0] row[11:0] column[9:0] m0 bk[1:0] row[11:0] column[10:0] m0 table 54. sdram configuration mapping: 8k rows, 256/512/1024/2048 columns cpu address line 2726252423222120191817161514131211109876543210 bk[1:0] row[12:0] column[7:0] m0 bk[1:0] row[12:0] column[8:0] m0 bk[1:0] row[12:0] column[9:0] m0 bk[1:0] row[12:0] column[10:0] m0
194 AT91RM9200 1768b?atarm?08/03 product dependencies sdram devices initialization the initialization sequence is generated by software. the sdram devices are initialized by the following sequence: 1. a minimum pause of 200 s is provided to precede any signal toggle. 2. an all banks precharge command is issued to the sdram devices. 3. eight auto-refresh (cbr) cycles are provided. 4. a mode register set (mrs) cycle is issued to program the parameters of the sdram devices, in particular cas latency and burst length. 5. a normal mode command is provided, 3 clocks after t mrd is met. 6. write refresh rate into the count field in the sdramc refresh timer register. (refresh rate = delay between refresh cycles). after these six steps, the sdram devices are fully functional. the commands (nop, mrs, cbr, normal mode) are generated by programming the com- mand field in the sdramc mode register figure 89. sdram devices initialization sequence c k :0] 10 1 1] c s a s a s w e b s inputs stable for 200 sec precharge all banks 1st auto-refresh 8th auto-refresh mrs command valid command k e t rp t rc t mrd
195 AT91RM9200 1768b?atarm?08/03 i/o lines the pins used for interfacing the sdram controller may be multiplexed with the pio lines. the programmer must first program the pio controller to assign the sdram controller pins to their peripheral function. if i/o lines of the sdram controller are not used by the application, they can be used for other purposes by the pio controller. interrupt the sdram controller interrupt (refresh error notification) is connected to the memory con- troller. this interrupt may be ored with other system peripheral interrupt lines and is finally provided as the system interrupt source (source 1) to the aic (advanced interrupt controller). using the sdram controller interrupt requires the aic to be programmed first. functional description sdram controller write cycle the sdram controller allows burst access or single access. to initiate a burst access, the sdram controller uses the transfer type signal provided by the master requesting the access. if the next access is a sequential write access, writing to the sdram device is carried out. if the next access is a write-sequential access, but the current access is to a boundary page, or if the next access is in another row, then the sdram controller generates a precharge com- mand, activates the new row and initiates a write command. to comply with sdram timing parameters, additional clock cycles are inserted between precharge/active (t rp ) commands and active/write (t rcd ) commands. for definition of these timing parameters, refer to the ?sdramc configuration register? on page 204. this is described in figure 90 below. figure 90. write burst, 32-bit sdram access sdck sdcs ras cas a[12:0] d[31:0] t rcd = 3 dna sdwe dnb dnc dnd dne dnf dng dnh dni dnj dnk dnl row n col a col b col c col d col e col f col g col h col i col j col k col l
196 AT91RM9200 1768b?atarm?08/03 sdram controller read cycle the sdram controller allows burst access or single access. to initiate a burst access, the sdram controller uses the transfer type signal provided by the master requesting the access. if the next access is a sequential read access, reading to the sdram device is carried out. if the next access is a sequential read access, but the current access is to a boundary page, or if the next access is in another row, then the sdram controller generates a precharge com- mand, activates the new row and initiates a read command. to comply with sdram timing parameters, an additional clock cycle is inserted between the precharge/active (t rp ) command and the active/read (t rcd ) command, after a read command, additional wait states are gener- ated to comply with cas latency. the sdram controller supports a cas latency of two. for definition of these timing parameters, refer to ?sdramc configuration register? on page 204. this is described in figure 91 below. figure 91. read burst, 32-bit sdram access sdck sdcs ras cas a[12:0] d[31:0] (input) t rcd = 3 dna sdwe dnb dnc dnd dne dnf row n col a col b col c col d col e col f cas = 2
197 AT91RM9200 1768b?atarm?08/03 border management when the memory row boundary has been reached, an automatic page break is inserted. in this case, the sdram controller generates a precharge command, activates the new row and initiates a read or write command. to comply with sdram timing parameters, an additional clock cycle is inserted between the precharge/active (t rp ) command and the active/read (t rcd ) command. this is described in figure 92 below. figure 92. read burst with boundary row access sdck sdcs ras cas a[12:0] d[31:0] t rp = 3 sdwe row m col a col a col b col c col d col e dna dnb dnc dnd t rcd = 3 cas = 3 col b col c col d dma dmb dmc dmd row n dme
198 AT91RM9200 1768b?atarm?08/03 sdram controller refresh cycles an auto-refresh command is used to refresh the sdram device. refresh addresses are gen- erated internally by the sdram device and incremented after each auto-refresh automatically. the sdram controller generates these auto-refresh commands periodically. a timer is loaded with the value in the register sdramc _tr that indicates the number of clock cycles between refresh cycles. a refresh error interrupt is generated when the previous auto-refresh command did not per- form. it will be acknowledged by reading the interrupt status register (sdramc_isr). when the sdram controller initiates a refresh of the sdram device, internal memory accesses are not delayed. however, if the cpu tries to access the sdram, the slave will indi- cate that the device is busy and the arm bwait signal will be asserted. see figure 93 below. figure 93. refresh cycle followed by a read access sdck sdcs ras cas a[12:0] d[31:0] (input) t rp = 3 sdwe dnb dnc dnd col c col d cas = 2 row m col a t rc = 8 t rcd = 3 dma row n
199 AT91RM9200 1768b?atarm?08/03 power management self-refresh mode self-refresh mode is used in power-down mode, i.e., when no access to the sdram device is possible. in this case, power consumption is very low. the mode is activated by programming the self-refresh command bit (srcb) in sdramc_srr. in self-refresh mode, the sdram device retains data without external clocking and provides its own internal clocking, thus per- forming its own auto-refresh cycles. all the inputs to the sdram device become ?don?t care? except sdcke, which remains low. as soon as the sdram device is selected, the sdram controller provides a sequence of commands and exits self-refresh mode, so the self-refresh command bit is disabled. to re-activate this mode, the self-refresh command bit must be re-programmed. the sdram device must remain in self-refresh mode for a minimum period of t ras and may remain in self-refresh mode for an indefinite period. this is described in figure 94 below. figure 94. self-refresh mode behavior sdck sdcs ras cas a[12:0] self refresh mode sdwe row t xsr = 3 sdcke write sdramc_srr srcb = 1 access request to the sdram controller
200 AT91RM9200 1768b?atarm?08/03 low-power mode low-power mode is used in power-down mode, i.e., when no access to the sdram device is possible. in this mode, power consumption is greater than in self-refresh mode. this state is similar to normal mode (no low-power mode/no self-refresh mode), but the sdcke pin is low and the input and output buffers are deactivat ed as soon as the sdram device is no longer accessible. in contrast to self-refresh mode, the sdram device cannot remain in low-power mode longer than the refresh period (64 ms for a whole device refresh operation). as no auto- refresh operations are performed in this mode, the sdram controller carries out the refresh operation. in order to exit low-power mode, a nop command is required. the exit procedure is faster than in self-refresh mode. when self-refresh mode is enabled, it is recommended to avoid enabling low-power mode. when low-power mode is enabled, it is recommended to avoid enabling self-refresh mode. this is described in figure 95 below. figure 95. low-power mode behavior sdck sdcs ras cas a[12:0] d[31:0] (input) t rcd = 3 dna dnb dnc dnd dne dnf row n col a col b col c col d col e col f cas = 2 sdcke low power mode
201 AT91RM9200 1768b?atarm?08/03 sdram controller (sdramc) user interface table 55. sdram controller memory map offset register name access reset state 0x00 sdramc mode register sdramc_mr read/write 0x00000010 0x04 sdramc refresh timer register sdramc_tr read/write 0x00000800 0x08 sdramc configuration register sdramc_cr read/write 0x2a99c140 0x0c sdramc self refresh register sdramc_srr write-only ? 0x10 sdramc low power register sdramc_lpr read/write 0x0 0x14 sdramc interrupt enable register sdramc_ier write-only ? 0x18 sdramc interrupt disable register sdramc_idr write-only ? 0x1c sdramc interrupt mask register sdramc_imr read-only 0x0 0x20 sdramc interrupt status register sdramc_isr read-only 0x0
202 AT91RM9200 1768b?atarm?08/03 sdramc mode register register name : sdramc_mr access type : read/write reset value : 0x00000010 mode: sdramc command mode this field defines the command issued by the sdram controller when the sdram device is accessed. dbw: data bus width 0: data bus width is 32 bits. 1: data bus width is 16 bits. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???dbw mode mode description 0000normal mode. any access to the sdram is decoded normally. 0001the sdram controller issues a nop command when the sdram device is accessed regardless of the cycle. 0010the sdram controller issues an ?all banks precharge? command when the sdram device is accessed regardless of the cycle. 0011the sdram controller issues a ?load mode register? command when the sdram device is accessed regardless of the cycle. the address offset with respect to the sdram device base address is used to program the mode register. for instance, when this mode is activated, an access to the ?sdram_base + offset? address generates a ?load mode register? command with the value ?offset? written to the sdram device mode register. 0100the sdram controller issues a ?refresh? command when the sdram device is accessed regardless of the cycle. previously, an ?all banks precharge? command must be issued.
203 AT91RM9200 1768b?atarm?08/03 sdramc refresh timer register register name : sdramc_tr access type : read/write reset value : 0x00000800 count: sdramc refresh timer count this 12-bit field is loaded into a timer that generates the refresh pulse. each time the refresh pulse is generated, a refresh burst is initiated. the value to be loaded depends on the sdramc clock frequency (mck: master clock), the refresh rate of the sdram device and the refresh burst length where 15.6 s per row is a typical value for a burst of length one. to refresh the sdram device even if the reset value is not equal to 0, this 12-bit field must be written. if this condition is not satisfied, no refresh command is issued and no refresh of the sdram device is carried out. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? ? ? count 76543210 count
204 AT91RM9200 1768b?atarm?08/03 sdramc configuration register register name : sdramc_cr access type : read/write reset value : 0x2a99c140 nc: number of column bits reset value is 8 column bits. nr: number of row bits reset value is 11 row bits. nb: number of banks reset value is two banks. 31 30 29 28 27 26 25 24 ? txsr tras 23 22 21 20 19 18 17 16 tras trcd trp 15 14 13 12 11 10 9 8 trp trc twr 76543210 twr cas nb nr nc nc column bits 008 019 1010 1111 nr row bits 00 11 01 12 10 13 11 reserved nb number of banks 02 14
205 AT91RM9200 1768b?atarm?08/03 cas: cas latency reset value is two cycles. in the sdramc, only a cas latency of two cycles is managed. in any case, another value must be programmed. twr: write recovery delay reset value is two cycles. this field defines the write recovery time in number of cycles. number of cycles is between 2 and 15. if twr is less than or equal to 2, two clock periods are inserted by default. trc: row cycle delay reset value is eight cycles. this field defines the delay between a refresh and an activate command in number of cycles. number of cycles is between 2 and 15. if trc is less than or equal to 2, two clock periods are inserted by default. trp: row precharge delay reset value is three cycles. this field defines the delay between a precharge command and another command in number of cycles. number of cycles is between 2 and 15. if trp is less than or equal to 2, two clock periods are inserted by default. trcd: row to column delay reset value is three cycles. this field defines the delay between an activate comma nd and a read/write command in number of cycles. number of cycles is between 2 and 15. if trcd is less than or equal to 2, two clock periods are inserted by default. tras: active to precharge delay reset value is five cycles. this field defines the delay between an activate command and a precharge command in number of cycles. number of cycles is between 2 and 15. if tras is less than or equal to 2, two clock periods are inserted by default. txsr: exit self refresh to active delay reset value is five cycles. this field defines the delay between scke set high and an ac tivate command in number of cycles. number of cycles is between 1/2 and 15.5. if txsr is equal to 0, 1/2 clock period is inserted by default. cas cas latency (cycles) 00 reserved 01 reserved 10 2 11 reserved
206 AT91RM9200 1768b?atarm?08/03 sdramc self-refresh register register name : sdramc_srr access type :write-only srcb: self-refresh command bit 0: no effect. 1: the sdram controller issues a self-refresh command to the sdram device, the sdck clock is inactivated and the sdcke signal is set low. the sdram device leaves self-refresh mode when accessed again. sdramc low-power register register name : sdramc_lpr access type : read/write reset value :0x0 lpcb: low-power command bit 0: the sdram controller low-power feature is inhibited: no low-power command is issued to the sdram device. 1: the sdram controller issues a low-power command to the sdram device after each burst access, the sdcke signal is set low. the sdram device will leave low-power mode when accessed and enter it after the access. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????srcb 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????lpcb
207 AT91RM9200 1768b?atarm?08/03 sdramc interrupt enable register register name : sdramc_ier access type :write-only res: refresh error status 0: no effect. 1: enables the refresh error interrupt. sdramc interrupt disable register register name : sdramc_idr access type :write-only res: refresh error status 0: no effect. 1: disables the refresh error interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????res 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????res
208 AT91RM9200 1768b?atarm?08/03 sdramc interrupt mask register register name : sdramc_imr access type : read-only res: refresh error status 0: the refresh error interrupt is disabled. 1: the refresh error interrupt is enabled. sdramc interrupt status register register name : sdramc_isr access type : read-only res: refresh error status 0: no refresh error has been detected since the register was last read. 1: a refresh error has been detected since the register was last read. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????res 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????res
209 AT91RM9200 1768b?atarm?08/03 burst flash controller (bfc) overview the burst flash controller (bfc) provides an interface for external 16-bit burst flash devices and handles an address space of 256m bytes. it supports byte, half-word and word aligned accesses and can access up to 32m bytes of burst flash devices. the bfc also supports data bus and address bus multiplexing. the burst flash interface supports only continuous burst reads. programmable burst lengths of four or eight words are not possible. the bfc never generates an abort signal, regardless of the requested address within the 256m bytes of address space. the bfc can operate with two burst read protocols depending on whether or not the address increment of the burst flash device is signal controlled. the burst flash controller mode reg- ister (bfc_mr) located in the bfc user interface is used in programming asynchronous or burst operating modes. in burst mode, the read protocol, clock controlled address advance, automatically increments the address at each clock cycle. whereas in signal controlled address advance protocol the address is incremented only when the burst address advance signal is active. when address and data bus multiplexing mode is chosen, the sixteen lowest address bits are multiplexed with the data bus. the bfc clock speed is programmable to be either master clock or master clock divided by 2 or 4. page size handling (16 bytes to 1024 bytes) is required by some burst flash devices unable to handle continuous burst read. the number of latency cycles after address valid goes up to sixteen cycles. the number of latency cycles after output enable runs between one and three cycles. the burst flash controller can also be programmed to suspend and maintain the current burst. this attribute gives other devices the possibility to share the bfc busses without any loss of efficiency. in burst mode, the bfc can restart a sequential access without any additional latency. features of the burst flash controller are: multiple access modes supported ? asynchronous or burst mode byte, half-word or word read accesses ? asynchronous mode half-word write accesses adaptability to different device speed grades ? programmable burst flash clock rate ? programmable data access time ? programmable latency after output enable adaptability to different device access protocols and bus interfaces ? two burst read protocols: clock control address advance or signal controlled address advance ? multiplexed or separate address and data busses ? continuous burst and page mode accesses supported
210 AT91RM9200 1768b?atarm?08/03 block diagram figure 96. burst flash controller block diagram i/o lines description apb bfck bfavd d[15:0] bfc pio controller bfbaa bfcs bfoe bfwe bfrdy a[24:0] user interface pmc mck memory controller bfc chip select table 56. i/o lines description name description type active level bfck burst flash clock output bfcs burst flash chip select output low bfavd burst flash address valid output low bfbaa burst flash address advance output low bfoe burst flash output enable output low bfwe burst flash write enable output low bfrdy burst flash ready input high a[24:0] address bus output d[15:0] data bus i/o
211 AT91RM9200 1768b?atarm?08/03 application example burst flash interface the burst flash interface provides control, address and data signals to the burst flash mem- ory. these signals are detailed in the ?functional description? on page 212 which describes the bfc functionality and operating modes. figure 97 below presents an illustration of the possible connections of the bfc to some popular burst flash memories. figure 97. burst flash controller connection example bfc at49sn6416a at49sn3208a [d0:d15] [d0:d15] [a0:a22] [a0:a22] clk avd/adv ce we oe rdy/wait bfc am29dbs643d am29bds323d [d0:d15] [ad0:ad15] [a16:a21] [a16:a21] bfck clk bfavd avd bfcs ce bfwe we bfoe oe bfrdy rdy bfc at49bn1604 [d0:d15] [d0:d15] [a0:a19] [a0:a19] bfck clk bfavd avd/lba bfcs ce bfwe we bfoe oe bfrdy rdy/ind bfc at49bp1604 [d0:d15] [ad0:ad15] [a16:a19] [a16:a19] bfbaa baa clock controlled address advance multiplexed bus disabled clock controlled address advance multiplexed bus enabled signal controlled address advance multiplexed bus disabled signal controlled address advance multiplexed bus enabled bfck bfavd bfcs bfwe bfoe bfrdy bfbaa clk avd ce we oe rdy baa bfck bfavd bfcs bfwe bfoe bfrdy
212 AT91RM9200 1768b?atarm?08/03 product dependencies supported burst flash devices the burst flash controller is designed to preferentially support the following atmel burst flash devices: at49sn6416a and at49sn6416at (64 mbits x 16) at49sn3208a and at49sn3208at (32 mbits x 16) at49bn3208 and at49bn3208t (32 mbits x 16) i/o lines the pins used for interfacing the burst flash controller may be multiplexed with the pio lines. the programmer must first program the pio controller to assign the burst flash controller pins to their peripheral function. if i/o lines of the burst flash controller are not used by the application, they can be used for other purposes by the pio controller. functional description the burst flash controller drives the following signals: address valid (bfavd), to latch the addresses clock (bfck), to supply the burst clock burst advance address (bfbaa), to control the burst flash memory address advance when programmed to operate in signal controlled burst advance write enable (bfwe), to write to the burst flash device output enable (bfoe), to enable the external device data drive on the data bus when enabled, the bfc also drives the address bus, the data bus and the chip select (bfcs) line. the ready signal (bfrdy) is taken as an input and used as an indicator for the next data availability. burst flash controller reset state after reset, the bfc is disabled and, therefore, must be enabled by programming the field bfcom. see ?burst flash controller mode register? on page 221. at this time, the burst flash controller operates in asynchronous mode. the burst flash memory can be pro- grammed by writing and reading in asynchronous mode. burst flash controller clock selection the bfc clock rate is programmable to be either master clock, master clock divided by 2 or master clock divided by 4. the clock selection is necessary in burst mode as well as in asyn- chronous mode. the latency fields in the mode register and all burst flash control signal waveforms are related to the burst flash clock (bfck) period. the bfc clock rate is selected by the bfcc field. see ?burst flash controller mode register? on page 221. figure 98. burst flash clock rates mck bfc clock bfcc = 1 mck bfc clock bfcc = 2 mck bfc clock bfcc = 3
213 AT91RM9200 1768b?atarm?08/03 burst flash controller asynchronous mode in asynchronous mode, the burst flash controller clock is off. the bfck signal is driven low. the bfc performs read access to bytes (8-bits), half-words (16-bits), and words (32-bits). in the last case, the bfc autonomously transforms the word read request into two separate half- word reads. this is fully transparent to the user. the bfc performs only half-word write requests. write requests for bytes or words are ignored by the bfc. for any access in the address space, the address is driven on the address bus while a pulse is driven on the bfavd signal (see figure 99 on page 214, and figure 100 on page 215). the burst flash address is also driven on the data bus if the multiplexed data and address bus options are enabled. (figure 99 on page 214). for write access, the signal bfwe is asserted in the following bfck clock cycle. for read access, the signal bfoe is asserted one cycle later. this additional cycle in read accesses has been inserted to switch the i/o pad direction so as to avoid conflict on the burst flash data bus when address and data busses are multiplexed. the address valid latency (avl) determines the length of the pulses as a number of master clock cycles. the avl field (see ?burst flash controller mode register? on page 221.) is coded as the address valid latency minus 1. waveforms in figure 99 on page 214 and figure 100 on page 215 show the avl field definition in read and write accesses. in read access, the access finishes with the rising edge of bfoe. in write access, data and address lines are released one half cycle after the rising edge of bfwe. after a read access to the burst flash, it takes output enable latency (oel) cycles for the burst flash device to release the data bus. the oel field (see ?burst flash controller mode register? on page 221.) gives the oel expressed in bfck clock cycles. this prevents other memory controllers from using the data bus until it is released by the burst flash device. in figure 99 on page 214 (multiplexed address and data busses), one idle cycle (oel = 1) is inserted between the read and write accesses. the burst flash device must release the data bus before the bfc can drive the address. as shown in figure 100 on page 215, where bus- ses are not multiplexed, the write access can start as soon as the read access ends. in the same way, the oel has no impact when a read follows a write access. waveforms in figure 99 on page 214 below and figure 100 on page 215 are related to the burst flash controller clock even though the bfck pin is driven low in asynchronous mode. the bfcc field (see ?burst flash controller mode register? on page 221.) is used as a mea- sure of the burst flash speed and must also be programmed in asynchronous mode.
214 AT91RM9200 1768b?atarm?08/03 figure 99. asynchronous read and write accesses with multiplexed address and data buses bfck bfcs bfavd bfoe d[15:0] output bfwe a[24:0] write address data read address d[15:0] input data read address write address asynchronous read access asynchronous write access avl avl oel = 1 address valid latency = 4 bfck cycles (avl field = 3) output enable latency (oel) = 1 bfck cycle
215 AT91RM9200 1768b?atarm?08/03 figure 100. asynchronous read and write accesses with non-multiplexed address and data burst flash controller synchronous mode writing the burst flash controller operating mode field (bfcom) to 2 (see ?burst flash con- troller mode register? on page 221) puts the bfc in burst mode. the bfc clock is driven on the bfck pin. only read accesses are treated and write accesses are ignored. the bfc sup- ports read access of bytes, half-words or words. burst read protocols the bfc supports two burst read protocols: clock controlled address advance, the internal address of the burst flash is automatically incremented at each bfck cycle. signal controlled address advance, the internal address of the burst flash is incremented only when the bfbaa signal is active. read access in burst mode when a read access is requested in burst mode, the requested address is registered in the bfc. for subsequent read accesses, the address is compared to the previous one. then the two following cases are considered: 1. in case of a non-sequential access, the current burst is broken and the bfc launches a new burst by performing an address latch cycle. the address is presented on the address bus in any case and on the data bus if the multiplexed bus option is enabled. bfck bfcs bfavd bfoe d[15:0] output bfwe a[24:0] write address data d[15:0] input data read address asynchronous read access asynchronous write access avl avl oel = 1 address valid latency = 4 bfck cycles (avl field = 3) output enable latency (oel) = 1 bfck cycle
216 AT91RM9200 1768b?atarm?08/03 this new address is registered in the bfc and is then used as reference for further accesses. 2. in case of sequential access, and provided that the bfoeh mode is selected in the mode register (see ?burst flash controller mode register? on page 221.), the internal burst address is incremented: ? through the bfbaa pin, if the signal controlled address advance is enabled. ? by enabling the clock during one clock cycle in clock controlled address advance mode. these protocols are illustrated in figure 101 below and figure 102 on page 217. the address valid latency (avl+1, see ?burst flash controller mode register? on page 221) gives the number of cycles from the first rising clock edge when bfavd is asserted to the rising edge that causes the read of data d1. note: this rising edge is also used to latch d0 in the bfc. figure 101. burst suspend and resume with signal control address advance bfck bfcs bfavd bfoe d[15:0] output bfwe a[24:0] address (1) d[15:0] input address (d0) avl (1) only if multiplexed address & data buses address valid latency = 4 bfck cycles (avl field = 3) output enable latency (oel) = 2 bfck cycles d0 d1 d2 d3 bfbaa d4 oel = 2 d4 d5 d6 burst suspend burst resume burst suspend and resume (bfoeh = 1) signal control address advance (baaen = 1) d0 sampling d5 sampling d4 sampling d3 sampling d2 sampling d1 sampling internal bfc selection signal
217 AT91RM9200 1768b?atarm?08/03 figure 102. burst suspend and resume with clock control address advance burst suspension for transfer enabling the bfc can suspend a burst to enable other internal transfers, or other memory controllers to use the memory address and data busses if they are shared. two modes are provided on the bfoeh bit (burst flash output enable handling, see ?burst flash controller mode regis- ter? on page 221): bfoeh = 1: the bfc suspends the burst when it is no longer selected and the bfoe pin is deasserted. when a new sequential access on the burst flash device is requested, the burst is resumed and the bfoe pin is asserted again. the data is available on the data bus after oel cycles. this mode provides a minimal access latency. (refer to figure 101 on page 216 and figure 102 above). bfoeh = 0: the bfc suspends the burst when it is no longer selected and the bfoe pin is deasserted. when a new access to the burst flash device is requested, either sequential or not, a new burst is initialized and the next data is available as defined by the avl latency field in the mode register. this mode is provided for burst flash devices for which the deassertion of the bfoe signal causes an irreversible break of the burst. figure 103 on page 218 shows the access request to the bfc and the deassertion of the bfoe signal due to a deselection of the bfc (suspend). when the bfc is requested again, a new burst is started even though the requested address is sequential to the previously requested address. bfck bfcs bfavd bfoe d[15:0] output bfwe a[24:0] address (1) d[15:0] input address (d0) avl (1) only if multiplexed address & data buses address valid latency = 4 bfck cycles (avl = 3) output enable latency (oel) = 2 bfck cycles d0 d1 d2 d3 d4 oel = 2 d4 d5 d6 burst suspend burst resume burst suspend and resume (bfoeh = 1) clock control address advance (baaen = 0) d0 sampling d5 sampling d4 sampling d3 sampling d2 sampling d1 sampling internal bfc selection signal
218 AT91RM9200 1768b?atarm?08/03 figure 103. burst flash controller with no burst enable handling continuous burst reads the bfc performs continuous burst reads. it is also possible to program page sizes from 16 bytes up to 1024 bytes. this is done by setting the appropriate value in the pages field of the ?burst flash controller mode register? on page 221. page mode in page mode, the bfc stops the current burst and starts a new burst each time the requested address matches a page boundary. figure 104 on page 219 illustrates a 16-byte page size. data d0 to d10 belong to two separate pages and are accessed through two burst accesses. this mode is provided for burst flash devices that cannot handle continuous burst read (in which case, a continuous burst access to address d0 would cause the burst flash internal bfck bfcs bfavd bfoe output bfwe a[24:0] address (1) d[15:0] input address (d0) avl (1) only if multiplexed address & data busses (2) master clock mode (bfcc =1) address valid latency = 4 bfck cycles output enable latency (oel) = 1 bfck cycle d0 d1 d2 d0 sampling d1 sampling oel = 1 d2 d3 d4 d2 sampling d3 sampling address (1) avl bfbaa address (d2) no burst output enable handling (bfoeh = 0) signal control advance address (baaen = 1) d[15:0] internal clock (2) a0 a1 a2 a3 internal bfc selection signal internal address bus begin new burst burst suspend
219 AT91RM9200 1768b?atarm?08/03 address to wrap around address d0). page mode can be disabled by programming a null value in the pages field of the ?burst flash controller mode register? on page 221. figure 104. burst read in page mode ready enable mode in ready enable mode (bit rdyen in the ?burst flash controller mode register? on page 221), the bfc uses the ready signal (bfrdy) from the burst flash device as an indicator of the next data availability. the bfrdy signal must be asserted one bfck cycle before data is valid. in figure 105 on page 220 below, the bfrdy signal indicates on edge (a) that the expected d4 data will not be available on the next rising bfck edge. the bfrdy signal remains low until rising at edge (b). d4 is then sampled on edge (c). when the rdyen mode is disabled (rdyen = 0), the bfrdy signal at the bfc input inter- face is ignored. this mode is provided for burst flash devices that do not handle the bfrdy signal. ?.. ?.. bfck bfcs bfavd bfoe d[15:0] output bfwe a[24:0] d[15:0] input address (d0) avl address valid latency = 3 bfck cycles (avl field = 2) output enable latency (oel) = 1 bfck cycle page size = 16 bytes d0 d1 d6 d7 d8 d9 d10 avl bfbaa address (d8) d0 d0 sampling d7 sampling 16-byte page d8 sampling 16-byte page burst read in page mode (16 bytes) signal control advance address (baaen = 1) 16-byte page boundary (8 accesses of 2 bytes each) (8 accesses of 2 bytes each) (1) a new page begins at d8 (1) (1) (1)
220 AT91RM9200 1768b?atarm?08/03 figure 105. burst read using bfrdy signal bfck bfcs bfavd bfoe a[24:0] d[15:0] input address (d0) avl address valid latency = 4 bfck cycles (avl field = 3) output enable latency (oel) = 1 bfck cycle d0 d1 d2 d3 bfbaa d0 sampling burst read signal control advance address (baaen = 1) bfrdy d1 d2 d3 d4 d6 d5 d7 (a) (b) (c) d4 d5 d6 d7
221 AT91RM9200 1768b?atarm?08/03 burst flash controller (bfc) user interface burst flash controller mode register register name: bfc_mr access type: read/write reset value: 0x0 bfcom: burst flash controller operating mode bfcc: burst flash controller clock avl: address valid latency the address valid latency is defined as the number of bfc clock cycles from the first bfck rising edge when bfavd is asserted to the bfck rising edge that samples read data. the latency is equal to avl + 1. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ? ? ? ? rdyen muxen bfoeh baaen 15 14 13 12 11 10 9 8 ?? oel pages 76543210 avl bfcc bfcom bfcom bfc operating mode 0 0 disabled. 0 1 asynchronous 1 0 burst read 11reserved bfcc bfc clock 00reserved 0 1 master clock 1 0 master clock divided by 2 1 1 master clock divided by 4
222 AT91RM9200 1768b?atarm?08/03 pages: page size this field defines the page size handling and the page size. oel: output enable latency this field defines the number of idle cycles inserted after each level change on the bfoe output enable signal. oel range is 1 to 3. baaen: burst address advance enable 0: the burst clock is enabled to increment the burst address or, disabled to remain at the same address. 1: the burst clock is continuous and the burst address advance is controlled with the bfbaa pin. bfoeh: burst flash output enable handling 0: no burst resume in burst mode. when the bfc is deselected, this causes an irreversible break of the burst. a new burst will be initiated for the next access. 1: burst resume. when the bfc is deselected, the burst is suspended. it will be resumed if the next access is sequential to the last one. muxen: multiplexed bus enable 0: the address and data busses operate independently. 1: the address and data busses are multiplexed. actually, the address is presented on both the data bus and the address bus when the bfavd signal is asserted. rdyen: ready enable mode 0: the bfrdy input signal at the bfc input interface is ignored. 1: the bfrdy input signal is used as an indicator of data availability in the next cycle. pages page size 0 0 0 no page handling. the ready signal (bfrdy) is sampled to check if the next data is available. 0 0 1 16 bytes page size 0 1 0 32 bytes page size 0 1 1 64 bytes page size 1 0 0 128 bytes page size 1 0 1 256 bytes page size 1 1 0 512 bytes page size 1 1 1 1024 bytes page size
223 AT91RM9200 1768b?atarm?08/03 peripheral data controller (pdc) overview the peri p heral data controller ( pdc ) transfers data between on-chi p serial p eri p herals such as the uart, usart, ssc, spi, mci and the on- and off-chi p memories. usin g the peri p heral data contoller avoids p rocessor intervention and removes the p rocessor interru p t-handlin g overhead.this si g nificantl y reduces the number of clock c y cles re q uired for a data transfer and, as a result, im p roves the p erformance of the microcontroller and makes it more p ower efficient. the pdc channels are im p lemented in p airs, each p air bein g dedicated to a p articular p eri p h- eral. one channel in the p air is dedicated to the receivin g channel and one to the transmittin g channel of each uart, usart, ssc and spi. the user interface of a pdc channel is inte g rated in the memor y s p ace of each p eri p heral. it contains: a 32-bit memory pointer register a 16-bit transfer count register a 32-bit register for next memory pointer a 16-bit register for next transfer count the p eri p heral tri gg ers pdc transfers usin g transmit and receive si g nals. when the p ro- g rammed data is transferred, an end of transfer interru p t is g enerated b y the corres p ondin g p eri p heral. important features of the pdc are: generates transfers to/from peripherals such as dbgu, usart, ssc, spi and mci supports up to twenty channels (product dependent) one master clock cycle needed for a transfer from memory to peripheral two master clock cycles needed for a transfer from peripheral to memory block diagram figure 106. block diagram control pdc channel 0 pdc channel 1 thr rhr control status & control peripheral peripheral data controller memory controller
224 AT91RM9200 1768b?atarm?08/03 functional description configuration the pdc channels user interface enables the user to configure and control the data transfers for each channel. the user interface of a pdc channel is integrated into the user interface of the peripheral (offset 0x100), which it is related to. per peripheral, it contains four 32-bit pointer registers (rpr, rnpr, tpr, and tnpr) and four 16-bit counter registers (rcr, rncr, tcr, and tncr). the size of the buffer (number of transfers) is configured in an internal 16-bit transfer counter register, and it is possible, at any moment, to read the number of transfers left for each channel. the memory base address is configured in a 32-bit memory pointer by defining the location of the first address to access in the memory. it is possible, at any moment, to read the location in memory of the next transfer and the number of remaining transfers. the pdc has dedicated status registers which indicate if the transfer is enabled or disabled for each channel. the sta- tus for each channel is located in the periphe ral status register. transfers can be enabled and/or disabled by setting txten/txtdis and rxten/rxtdis in pdc transfer control register. these control bits enable reading the pointer and counter registers safely without any risk of their changing between both reads. the pdc sends status flags to the peripheral visible in its status-register (endrx, endtx, rxbuff, and txbufe). endrx flag is set when the periph_rcr register reaches zero. rxbuff flag is set when both periph_rcr and periph_rncr reach zero. endtx flag is set when the periph_tcr register reaches zero. txbufe flag is set when both periph_tcr and periph_tncr reach zero. these status flags are described in the peripheral status register. memory pointers each peripheral is connected to the pdc by a receiver data channel and a transmitter data channel. each channel has an internal 32-bit memory pointer. each memory pointer points to a location anywhere in the memory space (on-chip memory or external bus interface memory). depending on the type of transfer (byte, half-word or word), the memory pointer is incre- mented by 1, 2 or 4, respectively for peripheral transfers. if a memory pointer is reprogrammed while the pdc is in operation, the transfer address is changed, and the pdc performs transfers using the new address. transfer counters there is one internal 16-bit transfer counter for each channel used to count the size of the block already transferred by its associated channel. these counters are decremented after each data transfer. when the counter reaches zero, the transfer is complete and the pdc stops transferring data. if the next counter register is equal to zero, the pdc disables the trigger while activating the related peripheral end flag. if the counter is reprogrammed while the pdc is operating, the number of transfers is updated and the pdc counts transfers from the new value. programming the next counter/pointer registers chains the buffers. the counters are decre- mented after each data transfer as stated above, but when the transfer counter reaches zero,
225 AT91RM9200 1768b?atarm?08/03 the values of the next counter/pointer are loaded into the counter/pointer registers in order to re-enable the triggers. for each channel, two status bits indicate the end of the current buffer (endrx, entx) and the end of both current and next buffer (rxbuff, txbufe). these bits are directly mapped to the peripheral status register and can trigger an interrupt request to the aic. the peripheral end flag is automatically cleared when one of the counter-registers (counter or next counter register) is written. note: when the next counter register is loaded into the counter register, it is set to zero. data transfers the peripheral triggers pdc transfers using transmit (txrdy) and receive (rxrdy) signals. when the peripheral receives an external charac ter, it sends a receive ready signal to the pdc which then requests access to the system bus. when access is granted, the pdc starts a read of the peripheral receive holding register (rhr) and then triggers a write in the memory. after each transfer, the relevant pdc memory pointer is incremented and the number of trans- fers left is decremented. when the memory block size is reached, a signal is sent to the peripheral and the transfer stops. the same procedure is followed, in reverse, for transmit transfers. priority of pdc transfer requests the peripheral data controller handles transfer requests from the channel according to priori- ties fixed for each product.these priorities are defined in the product datasheet. if simultaneous requests of the same type (receiver or transmitter) occur on identical peripher- als, the priority is determined by the numbering of the peripherals. if transfer requests are not simultaneous, th ey are treated in the order they occurred. requests from the receivers are handled first and then followed by transmitters requests.
226 AT91RM9200 1768b?atarm?08/03 peripheral data controller (pdc) user interface note: 1. periph: ten registers are mapped in the peripheral memory space at the same offset. these can be defined by the user according to the function and the peripheral desired (dbgu, usart, ssc, spi, mci etc). pdc receive pointer register register name: periph _ rpr access type: read/write rxptr: receive pointer address address of the next receive transfer. table 57. register mapping offset register register name read/write reset 0x100 pdc receive pointer register periph (1) _rpr read/write 0x0 0x104 pdc receive counter register periph_rcr read/write 0x0 0x108 pdc transmit pointer register periph_tpr read/write 0x0 0x10c pdc transmit counter register periph_tcr read/write 0x0 0x110 pdc receive next pointer register periph_rnpr read/write 0x0 0x114 pdc receive next counter register periph_rncr read/write 0x0 0x118 pdc transmit next pointer register periph_tnpr read/write 0x0 0x11c pdc transmit next counter register periph_tncr read/write 0x0 0x120 pdc transfer control register periph_ptcr write-only - 0x114 pdc transfer status register periph_ptsr read-only 0x0 31 30 29 28 27 26 25 24 rxptr 23 22 21 20 19 18 17 16 rxptr 15 14 13 12 11 10 9 8 rxptr 76543210 rxptr
227 AT91RM9200 1768b?atarm?08/03 pdc receive counter register register name: periph _ rcr access type: read/write rxctr: receive counter value number of receive transfers to be performed. pdc transmit pointer register register name: periph _ tpr access type: read/write txptr: transmit pointer address address of the transmit buffer. pdc transmit counter register register name: periph _ tcr access type: read/write txctr: transmit counter value txctr is the size of the transmit transfer to be performed. at zero, the peripheral data transfer is stopped. 31 30 29 28 27 26 25 24 -- 23 22 21 20 19 18 17 16 -- 15 14 13 12 11 10 9 8 rxctr 76543210 rxctr 31 30 29 28 27 26 25 24 txptr 23 22 21 20 19 18 17 16 txptr 15 14 13 12 11 10 9 8 txptr 76543210 txptr 31 30 29 28 27 26 25 24 -- 23 22 21 20 19 18 17 16 -- 15 14 13 12 11 10 9 8 txctr 76543210 txctr
228 AT91RM9200 1768b?atarm?08/03 pdc receive next pointer register register name: periph _ rnpr access type: read/write rxnptr: receive next pointer address rxnptr is the address of the next buffer to fill with received data when the current buffer is full. pdc receive next counter register register name: periph _ rncr access type: read/write rxncr: receive next counter value rxncr is the size of the next buffer to receive. pdc transmit next pointer register register name: periph _ tnpr access type: read/write txnptr: transmit next pointer address txnptr is the address of the next buffer to transmit when the current buffer is empty. 31 30 29 28 27 26 25 24 rxnptr 23 22 21 20 19 18 17 16 rxnptr 15 14 13 12 11 10 9 8 rxnptr 76543210 rxnptr 31 30 29 28 27 26 25 24 -- 23 22 21 20 19 18 17 16 -- 15 14 13 12 11 10 9 8 rxncr 76543210 rxncr 31 30 29 28 27 26 25 24 txnptr 23 22 21 20 19 18 17 16 txnptr 15 14 13 12 11 10 9 8 txnptr 76543210 txnptr
229 AT91RM9200 1768b?atarm?08/03 pdc transmit next counter register register name: periph _ tncr access type: read/write txncr: transmit next counter value txncr is the size of the next buffer to transmit. pdc transfer control register register name: periph_ptcr access type: write - only rxten: receiver transfer enable 0 = no effect. 1 = enables the receiver pdc transfer requests if rxtdis is not set. rxtdis: receiver transfer disable 0 = no effect. 1 = disables the receiver pdc transfer requests. txten: transmitter transfer enable 0 = no effect. 1 = enables the transmitter pdc transfer requests. txtdis: transmitter transfer disable 0 = no effect. 1 = disables the transmitter pdc transfer requests 31 30 29 28 27 26 25 24 -- 23 22 21 20 19 18 17 16 -- 15 14 13 12 11 10 9 8 txncr 76543210 txncr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? txtdis txten 76543210 ? ? ? ? ? ? rxtdis rxten
230 AT91RM9200 1768b?atarm?08/03 pdc transfer status register register name: periph _ ptsr access type: read-onl y rxten: receiver transfer enable 0 = receiver pdc transfer requests are disabled. 1 = receiver pdc transfer requests are enabled. txten: transmitter transfer enable 0 = transmitter pdc transfer requests are disabled. 1 = transmitter pdc transfer requests are enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????txten 76543210 ???????rxten
231 AT91RM9200 1768b?atarm?08/03 advanced interrupt controller (aic) overview the advanced interrupt controller (aic) is an 8-level priority, individually maskable, vectored interrupt controller, providing handling of up to thirty-two interrupt sources. it is designed to substantially reduce the software and real-time overhead in handling internal and external interrupts. the aic drives the nfiq (fast interrupt request) and the nirq (standard interrupt request) inputs of an arm processor. inputs of the aic are either internal peripheral interrupts or exter- nal interrupts coming from the product's pins. the 8-level priority controller allows the user to define the priority for each interrupt source, thus permitting higher priority interrupts to be serviced even if a lower priority interrupt is being treated. internal interrupt sources can be programmed to be level sensitive or edge triggered. external interrupt sources can be programmed to be positive-edge or negative-edge triggered or high- level or low-level sensitive. the fast forcing feature redirects any internal or external interrupt source to provide a fast interrupt rather than a normal interrupt. important features of the aic are: controls the interrupt lines (nirq and nfiq) of an arm ? processor thirty-two individually maskable and vectored interrupt sources ? source 0 is reserved for the fast interrupt input (fiq) ? source 1 is reserved for system peripherals (st, rtc, pmc, dbgu?) ? source 2 to source 31 control up to thirty embedded peripheral interrupts or external interrupts ? programmable edge-triggered or level-sensitive internal sources ? programmable positive/negative edge-triggered or high/low level-sensitive external sources 8-level priority controller ? drives the normal interrupt of the processor ? handles priority of the interrupt sources 1 to 31 ? higher priority interrupts can be served during service of lower priority interrupt vectoring ? optimizes interrupt service routine branch and execution ? one 32-bit vector register per interrupt source ? interrupt vector register reads the corresponding current interrupt vector protect mode ? easy debugging by preventing automatic operations when protect modeis are enabled fast forcing ? permits redirecting any normal interrupt source on the fast interrupt of the processor general interrupt mask ? provides processor synchronization on events without triggering an interrupt
232 AT91RM9200 1768b?atarm?08/03 block diagram figure 107. block diagram application block diagram figure 108. description of the application block aic detailed block diagram figure 109. aic detailed block diagram aic apb arm processor fiq irq0-irqn embedded peripheralee peripheral embedded peripheral embedded up to thirty-two sources nfiq nirq advanced interrupt controller embedded peripherals external peripherals (external interrupts) standalone applications rtos drivers hard real time tasks os-based applications os drivers general os interrupt handler fiq pio controller advanced interrupt controller irq0-irqn pioirq embedded peripherals external source input stage internal source input stage fast forcing interrupt priority controller fast interrupt controller arm processor nfiq nirq power management controller wake up user interface apb processor clock
233 AT91RM9200 1768b?atarm?08/03 i/o line description product dependencies i/o lines the interrupt signals fiq and irq0 to irqn are normally multiplexed through the pio control- lers. depending on the features of the pio controller used in the product, the pins must be programmed in accordance with their assigned interrupt function. this is not applicable when the pio controller used in the product is transparent on the input path. power management the advanced interrupt controller is continuously clocked. the power management controller has no effect on the advanced interrupt controller behavior. the assertion of the advanced interrupt controller outputs, either nirq or nfiq, wakes up the arm processor while it is in idle mode. the general interrupt mask feature enables the aic to wake up the processor without asserting the interrupt line of the processor, thus providing syn- chronization of the processor on an event. interrupt sources the interrupt source 0 is always located at fiq. if the product does not feature an fiq pin, the interrupt source 0 cannot be used. the interrupt source 1 is always located at system interrupt. this is the result of the or-wir- ing of the system peripheral interrupt lines, such as the system timer, the real time clock, the power management controller and the memory controller. when a system interrupt occurs, the service routine must first distinguish the cause of the interrupt. this is performed by reading successively the status registers of the above mentioned system peripherals. the interrupt sources 2 to 31 can either be connected to the interrupt outputs of an embedded user peripheral or to external interrupt lines. the external interrupt lines can be connected directly, or through the pio controller. the pio controllers are considered as user peripherals in the scope of interrupt handling. accordingly, the pio controller interrupt lines are connected to the interrupt sources 2 to 31. the peripheral identification defined at the pr oduct level corresponds to the interrupt source number (as well as the bit number controlling the clock of the peripheral). consequently, to simplify the description of the functional operat ions and the user interface, the interrupt sources are named fiq, sys, and pid2 to pid31. table 58. i/o line description pin name pin description type fiq fast interrupt input irq0 - irqn interrupt 0 - interrupt n input
234 AT91RM9200 1768b?atarm?08/03 functional description interrupt source control interrupt source mode the advanced interrupt controller independen tly programs each interrupt source. the src- type field of the corresponding aic_smr (s ource mode register) selects the interrupt condition of each source. the internal interrupt sources wired on the interrupt outputs of the embedded peripherals can be programmed either in level-sensitive mode or in edge-triggered mode. the active level of the internal interrupts is not important for the user. the external interrupt sources can be programmed either in high level-sensitive or low level- sensitive modes, or in positive edge-triggered or negative edge-triggered modes. interrupt source enabling each interrupt source, including the fiq in source 0, can be enabled or disabled by using the command registers; aic_iecr (interrupt enable command register) and aic_idcr (inter- rupt disable command register). this set of registers conducts enabling or disabling in one instruction. the interrupt mask can be read in the aic_imr register. a disabled interrupt does not affect servicing of other interrupts. interrupt clearing and setting all interrupt sources programmed to be edge-triggered (including the fiq in source 0) can be individually set or cleared by writing respectively the aic_iscr and aic_iccr registers. clearing or setting interrupt sources programmed in level-sensitive mode has no effect. the clear operation is perfunctory, as the software must perform an action to reinitialize the ?memorization? circuitry activated when the source is programmed in edge-triggered mode. however, the set operation is available for auto-test or software debug purposes. it can also be used to execute an aic-implementation of a software interrupt. the aic features an automatic clear of the current interrupt when the aic_ivr (interrupt vec- tor register) is read. only the interrupt source being detected by the aic as the current interrupt is affected by this operation. (see ?priority controller? on page 237.) the automatic clear reduces the operations required by the interrupt service routine entry code to reading the aic_ivr. note that the automatic interrupt clear is disabled if the interrupt source has the fast forcing feature enabled as it is considered uniquely as a fiq source. (for further details, see ?fast forcing? on page 241.) the automatic clear of the interrupt source 0 is performed when aic_fvr is read. interrupt status for each interrupt, the aic operation originates in aic_ipr (interrupt pending register) and its mask in aic_imr (interrupt mask register). aic_ipr enables the actual activity of the sources, whether masked or not. the aic_isr register reads the number of the current interrupt (see ?priority controller? on page 237) and the register aic_cisr gives an image of the signals nirq and nfiq driven on the processor. each status referred to above can be used to optimize the interrupt handling of the systems.
235 AT91RM9200 1768b?atarm?08/03 internal interrupt source input stage figure 110. internal interrupt source input stage external interrupt source input stage figure 111. external interrupt source input stage mck nirq maximum irq latency = 3.5 cycles peripheral interrupt becomes active edge detector clear set pos./neg. aic_iscr aic_iccr source i ff level/ edge high/lo w aic_smri srctype aic_ipr aic_imr aic_iecr aic_idcr fast interrupt controller or priority controller
236 AT91RM9200 1768b?atarm?08/03 interrupt latencies global interrupt latencies depend on several parameters, including: the time the software masks the interrupts. occurrence, either at the processor level or at the aic level. the execution time of the instruction in progress when the interrupt occurs. the treatment of higher priority interrupts and the resynchronization of the hardware signals. this section addresses only the hardware resynchronizations. it gives details of the latency times between the event on an external interrupt leading in a valid interrupt (edge or level) or the assertion of an internal interrupt source and the assertion of the nirq or nfiq line on the processor. the resynchronization time depends on the programming of the interrupt source and on its type (internal or external). for the standard interrupt, resynchronization times are given assuming there is no higher priority in progress. the pio controller multiplexing has no effect on the interrupt latencies of the external interrupt sources. external interrupt edge triggered source figure 112. external interrupt edge triggered source external interrupt level sensitive source figure 113. external interrupt level sensitive source maximum fiq latency = 4 cycles maximum irq latency = 4 cycles nfiq nirq mck irq or fiq (positive edge) irq or fiq (negative edge) maximum irq latency = 3 cycles maximum fiq latency = 3 cycles mck irq or fiq (high level) irq or fiq (low level) nirq nfiq
237 AT91RM9200 1768b?atarm?08/03 internal interrupt edge triggered source figure 114. internal interrupt edge triggered source internal interrupt level sensitive source figure 115. internal interrupt level sensitive source normal interrupt priority controller an 8-level priority controller drives the nirq line of the processor, depending on the interrupt conditions occurring on the interrupt sources 1 to 31 (except for those programmed in fast forcing). each interrupt source has a programmable priority level of 7 to 0, which is user-definable by writing the prior field of the corresponding aic_smr (source mode register). level 7 is the highest priority and level 0 the lowest. as soon as an interrupt conditi on occurs, as defined by the srctype field of the aic_svr (source vector register), the nirq line is asserted. as a new interrupt condition might have happened on other interrupt sources since the nirq has been asserted, the priority controller determines the current interrupt at the time the aic_ivr (interrupt vector register) is read. the read of aic_ivr is the entry point of the interrupt handling which allows the aic to consider that the interrupt has been taken into account by the software. the current priority level is defined as the priority level of the current interrupt. if several interrupt sources of equal priority are pending and enabled when the aic_ivr is read, the interrupt with the lowest interrupt source number is serviced first. the nirq line can be asserted only if an interrupt condition occurs on an interrupt source with a higher priority. if an interrupt condition happens (or is pending) during the interrupt treatment in progress, it is delayed until the software indicates to the aic the end of the current service by writing the aic_eoicr (end of interrupt command register). the write of aic_eoicr is the exit point of the interrupt handling . mck nirq peripheral interrupt becomes active maximum irq latency = 4.5 cycles mck nirq maximum irq latency = 3.5 cycles peripheral interrupt becomes active
238 AT91RM9200 1768b?atarm?08/03 interrupt nesting the priority controller utilizes interrupt nesting in order for the highest priority interrupt to be handled during the service of lower priority interrupts. this requires the interrupt service rou- tines of the lower interrupts to re-enable the interrupt at the processor level. when an interrupt of a higher priority happens during an already occurring interrupt service routine, the nirq line is re-asserted. if the interrupt is enabled at the core level, the current execution is interrupted and the new interrupt service routine should read the aic_ivr. at this time, the current interrupt number and its priority level are pushed into an embedded hardware stack, so that they are saved and restored when the higher priority interrupt servicing is fin- ished and the aic_eoicr is written. the aic is equipped with an 8-level wide hardware stack in order to support up to eight inter- rupt nestings pursuant to having eight priority levels. interrupt vectoring the interrupt handler addresses corresponding to each interrupt source can be stored in the registers aic_svr1 to aic_svr31 (source vector register 1 to 31). when the processor reads aic_ivr (interrupt vector register), the value written into aic_svr corresponding to the current interrupt is returned. this feature offers a way to branch in one single instruction to the handler corresponding to the current interrupt, as aic_ivr is mapped at the absolute address 0xffff f100 and thus accessible from the arm interrupt vector at address 0x0000 0018 through the following instruction: ldr pc,[pc,# -&f20] when the processor executes this instruction, it loads the read value in aic_ivr in its program counter, thus branching the execution on the correct interrupt handler. this feature is often not used when the application is based on an operating system (either real time or not). operating systems often have a single entry point for all the interrupts and the first task performed is to discern the source of the interrupt. however, it is strongly recommended to port the operating system on at91 products by sup- porting the interrupt vectoring. this can be performed by defining all the aic_svr of the interrupt source to be handled by the operating system at the address of its interrupt handler. when doing so, the interrupt vectoring permits a critical interrupt to transfer the execution on a specific very fast handler and not onto the operating system?s general interrupt handler. this facilitates the support of hard real-time tasks (input/outputs of voice/audio buffers and software peripheral handling) to be handled efficiently and independently of the application running under an operating system. interrupt handlers this section gives an overview of the fast interrupt handling sequence when using the aic. it is assumed that the programmer understands the architecture of the arm processor, and especially the processor interrupt modes and the associated status bits. it is assumed that: 1. the advanced interrupt controller has been programmed, aic_svr registers are loaded with corresponding interrupt service routine addresses and interrupts are enabled. 2. the instruction at the arm interrupt exception vector address is required to work with the vectoring ldr pc, [pc, # -&f20] when nirq is asserted, if the bit ?i? of cpsr is 0, the sequence is as follows: 1. the cpsr is stored in spsr_irq, the current value of the program counter is loaded in the interrupt link register (r14_irq) and the program counter (r15) is loaded with
239 AT91RM9200 1768b?atarm?08/03 0x18. in the following cycle during fetch at address 0x1c, the arm core adjusts r14_irq, decrementing it by four. 2. the arm core enters interrupt mode, if it has not already done so. 3. when the instruction loaded at address 0x18 is executed, the program counter is loaded with the value read in aic_ivr. reading the aic_ivr has the following effects: ? sets the current interrupt to be the pending and enabled interrupt with the highest priority. the current level is the priority level of the current interrupt. ? de-asserts the nirq line on the processor. even if vectoring is not used, aic_ivr must be read in order to de-assert nirq. ? automatically clears the interrupt, if it has been programmed to be edge-triggered. ? pushes the current level and the current interrupt number on to the stack. ? returns the value written in the aic_svr corresponding to the current interrupt. 4. the previous step has the effect of branching to the corresponding interrupt service routine. this should start by saving the link register (r14_irq) and spsr_irq. the link register must be decremented by four when it is saved if it is to be restored directly into the program counter at the end of the interrupt. for example, the instruction sub pc, lr, #4 may be used. 5. further interrupts can then be unmasked by clearing the ?i? bit in cpsr, allowing re- assertion of the nirq to be taken into account by the core. this can happen if an inter- rupt with a higher priority than the current interrupt occurs. 6. the interrupt handler can then proceed as required, saving the registers that will be used and restoring them at the end. during this phase, an interrupt of higher priority than the current level will restart the sequence from step 1. note: if the interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase. 7. the ?i? bit in cpsr must be set in order to mask interrupts before exiting to ensure that the interrupt is completed in an orderly manner. 8. the end of interrupt command register (aic_eoicr) must be written in order to indi- cate to the aic that the current interrupt is finished. this causes the current level to be popped from the stack, restoring the previous current level if one exists on the stack. if another interrupt is pending, with lower or equal priority than the old current level but with higher priority than the new current level, the nirq line is re-asserted, but the interrupt sequence does not immediately start because the ?i? bit is set in the core. spsr_irq is restored. finally, the saved value of the link register is restored directly into the pc. this has effect of returning from the interrupt to whatever was being exe- cuted before, and of loading the cpsr with the stored spsr, masking or unmasking the interrupts depending on the state saved in spsr_irq. note: the ?i? bit in spsr is significant. if it is set, it indicates that the arm core was on the verge of masking an interrupt when the mask instruction was interrupted. hence, when spsr is restored, the mask instruction is completed (interrupt is masked). fast interrupt fast interrupt source the interrupt source 0 is the only source which can raise a fast interrupt request to the proces- sor except if fast forcing is used. the interrupt source 0 is generally connected to a fiq pin of the product, either directly or through a pio controller. fast interrupt control the fast interrupt logic of the aic has no priority controller. the mode of interrupt source 0 is programmed with the aic_smr0 and the field prior of this register is not used even if it
240 AT91RM9200 1768b?atarm?08/03 reads what has been written. the field srctype of aic_smr0 enables programming the fast interrupt source to be positive-edge triggered or negative-edge triggered or high-level sen- sitive or low-level sensitive writing 0x1 in the aic_iecr (interrupt enable command register) and aic_idcr (interrupt disable command register) respectively enables and disables the fast interrupt. the bit 0 of aic_imr (interrupt mask register) indicates whether the fast interrupt is enabled or disabled. fast interrupt vectoring the fast interrupt handler address can be stored in aic_svr0 (source vector register 0). the value written into this register is returned when the processor reads aic_fvr (fast vec- tor register). this offers a way to branch in one single instruction to the interrupt handler, as aic_fvr is mapped at the absolute address 0xffff f104 and thus accessible from the arm fast interrupt vector at address 0x0000 001c through the following instruction: ldr pc,[pc,# -&f20] when the processor executes this instruction it loads the value read in aic_fvr in its pro- gram counter, thus branching the execution on the fast interrupt handler. it also automatically performs the clear of the fast interrupt source if it is programmed in edge-triggered mode. fast interrupt handlers this section gives an overview of the fast interrupt handling sequence when using the aic. it is assumed that the programmer understands the architecture of the arm processor, and especially the processor interrupt modes and associated status bits. assuming that: 1. the advanced interrupt controller has been programmed, aic_svr0 is loaded with the fast interrupt service routine address, and the interrupt source 0 is enabled. 2. the instruction at address 0x1c (fiq exception vector address) is required to vector the fast interrupt: ldr pc, [pc, # -&f20] 3. the user does not need nested fast interrupts. when nfiq is asserted if the bit "f" of cpsr is 0, the sequence is: 1. the cpsr is stored in spsr_fiq, the current value of the program counter is loaded in the fiq link register (r14_fiq) and the program counter (r15) is loaded with 0x1c. in the following cycle, during fetch at address 0x20, the arm core adjusts r14_fiq, decre- menting it by four. 2. the arm core enters fiq mode. 3. when the instruction loaded at address 0x1c is executed, the program counter is loaded with the value read in aic_fvr. reading the aic_fvr has effect of automati- cally clearing the fast interrupt, if it has been programmed to be edge triggered. in this case only, it de-asserts the nfiq line on the processor. 4. the previous step enables branching to the corresponding interrupt service routine. it is not necessary to save the link register r14_fiq and spsr_fiq if nested fast interrupts are not needed. 5. the interrupt handler can then proceed as required. it is not necessary to save regis- ters r8 to r13 because fiq mode has its own dedicated registers and the user r8 to r13 are banked. the other registers, r0 to r7, must be saved before being used, and restored at the end (before the next step). note that if the fast interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase in order to de-assert the interrupt source 0. 6. finally, the link register r14_fiq is restored into the pc after decrementing it by four (with instruction sub pc, lr, #4 for example). this has the effect of returning from the interrupt to whatever was being executed before, loading the cpsr with the spsr
241 AT91RM9200 1768b?atarm?08/03 and masking or unmasking the fast interrupt depending on the state saved in the spsr. note: the "f" bit in spsr is significant. if it is set, it indicates that the arm core was just about to mask fiq interrupts when the mask instruction was interrupted. hence when the spsr is restored, the interrupted instruction is completed (fiq is masked). another way to handle the fast interrupt is to map the interrupt service routine at the address of the arm vector 0x1c. this method does not use the vectoring, so that reading aic_fvr must be performed at the very beginning of the handler operation. however, this method saves the execution of a branch instruction. fast forcing the fast forcing feature of the advanced interrupt controller provides redirection of any nor- mal interrupt source on the fast interrupt controller. fast forcing is enabled or disabled by writing to the fast forcing enable register (aic_ffer) and the fast forcing disable register (aic_ffdr). writing to these registers results in an update of the fast forcing status register (aic_ffsr) that controls the feature for each internal or external interrupt source. when fast forcing is disabled, the interrupt sources are handled as described in the previous pages. when fast forcing is enabled, the edge/level programming and, in certain cases, edge detec- tion of the interrupt source is still active but the source cannot trigger a normal interrupt to the processor and is not seen by the priority handler. if the interrupt source is programmed in level-sensitive mode and an active level is sampled, fast forcing results in the assertion of the nfiq line to the core. if the interrupt source is programmed in edge-triggered mode and an active edge is detected, fast forcing results in the assertion of the nfiq line to the core. the fast forcing feature does not affect the source 0 pending bit in the interrupt pending register (aic_ipr). the fast interrupt vector register (aic_fvr) reads the contents of the source vector regis- ter 0 (aic_svr0), whatever the source of the fast interrupt may be. the read of the fvr does not clear the source 0 when the fast forcing feature is used and the interrupt source should be cleared by writing to the interrupt clear command register (aic_iccr). all enabled and pending interrupt sources that have the fast forcing feature enabled and that are programmed in edge-triggered mode must be cleared by writing to the interrupt clear command register. in doing so, they are cleared independently and thus lost interrupts are prevented. the read of aic_ivr does not clear the source that has the fast forcing feature enabled. the source 0, reserved to the fast interrupt, continues operating normally and becomes one of the fast interrupt sources.
242 AT91RM9200 1768b?atarm?08/03 figure 116. fast forcing protect mode the protect mode permits reading the interrupt vector register without performing the associ- ated automatic operations. this is necessary when working with a debug system. when a debugger, working either with a debug monitor or the arm processor's ice, stops the applica- tions and updates the opened windows, it might read the aic user interface and thus the ivr. this has undesirable consequences: if an enabled interrupt with a higher priority than the current one is pending, it is stacked. if there is no enabled pending interrupt, the spurious vector is returned. in either case, an end of interrupt command is necessary to acknowledge and to restore the context of the aic. this operation is generally not performed by the debug system as the debug system would become strongly intrusive and cause the application to enter an undes- ired state. this is avoided by using the protect mode. writing dbgm in aic_dcr (debug control regis- ter) at 0x1 enables the protect mode. when the protect mode is enabled, the aic performs interrupt stacking only when a write access is performed on the aic_ivr. therefore, the interrupt service routines must write (arbitrary data) to the aic_ivr just after reading it. the new context of the aic, including the value of the interrupt status register (aic_isr), is updated with the current interrupt only when aic_ivr is written. an aic_ivr read on its own (e.g., by a debugger), modifies neither the aic context nor the aic_isr. extra aic_ivr reads perform the same operations. however, it is recommended to not stop the processor between the read and the write of aic_ivr of the interrupt service rou- tine to make sure the debugger does not modify the aic context. to summarize, in normal operating mode, the read of aic_ivr performs the following opera- tions within the aic: 1. calculates active interrupt (higher than current or spurious). 2. determines and returns the vector of the active interrupt. 3. memorizes the interrupt. 4. pushes the current priority level onto the internal stack. 5. acknowledges the interrupt. source 0 _ fiq input stage automatic clear input stage automatic clear source n aic_ipr aic_imr aic_ffsr aic_ipr aic_imr priority manager nfiq nirq read ivr if source n is the current interrupt and if fast forcing is disabled on source n. read fvr if fast forcing is disabled on sources 1 to 31.
243 AT91RM9200 1768b?atarm?08/03 however, while the protect mode is activated, only operations 1 to 3 are performed when aic_ivr is read. operations 4 and 5 are only performed by the aic when aic_ivr is written. software that has been written and debugged using the protect mode runs correctly in normal mode without modification. however, in normal mode the aic_ivr write has no effect and can be removed to optimize the code. spurious interrupt the advanced interrupt controller features protection against spurious interrupts. a spurious interrupt is defined as being the assertion of an interrupt source long enough for the aic to assert the nirq, but no longer present when aic_ivr is read. this is most prone to occur when: an external interrupt source is programmed in level-sensitive mode and an active level occurs for only a short time. an internal interrupt source is programmed in level sensitive and the output signal of the corresponding embedded peripheral is activated for a short time. (as in the case for the watchdog.) an interrupt occurs just a few cycles before the software begins to mask it, thus resulting in a pulse on the interrupt source. the aic detects a spurious interrupt at the time the aic_ivr is read while no enabled interrupt source is pending. when this happens, the aic returns the value stored by the programmer in aic_spu (spurious vector register). the programmer must store the address of a spurious interrupt handler in aic_spu as part of the application, to enable an as fast as possible return to the normal execution flow. this handler writes in aic_eoicr and performs a return from interrupt. general interrupt mask the aic features a general interrupt mask bit to prevent interrupts from reaching the proces- sor. both the nirq and the nfiq lines are driven to their inactive state if the bit gmsk in aic_dcr (debug control register) is set. however, this mask does not prevent waking up the processor if it has entered idle mode. this function facilitates synchronizing the processor on a next event and, as soon as the event occurs, performs subsequent operations without having to handle an interrupt. it is strongly recommended to use this mask with caution.
244 AT91RM9200 1768b?atarm?08/03 advanced interrupt controller (aic) user interface base address the aic is mapped at the address 0xffff f000 . it has a total 4-kbyte addressing space. this permits the vectoring feature, as the pc-relative load/store instructions of the arm processor supports only an 4-kbyte offset. note: 1. the reset value of the interrupt pending register depends on the level of the external interrupt source. all other sourc es are cleared at reset, thus not pending. table 59. register mapping offset register name access reset value 0000 source mode register 0 aic_smr0 read/write 0x0 0x04 source mode register 1 aic_smr1 read/write 0x0 ?? ??? 0x7c source mode register 31 aic_smr31 read/write 0x0 0x80 source vector register 0 aic_svr0 read/write 0x0 0x84 source vector register 1 aic_svr1 read/write 0x0 ?? ??? 0xfc source vector register 31 aic_svr31 read/write 0x0 0x100 interrupt vector register aic_ivr read-only 0x0 0x104 fast interrupt vector register aic_fvr read-only 0x0 0x108 interrupt status register aic_isr read-only 0x0 0x10c interrupt pending register aic_ipr read-only 0x0 (1) 0x110 interrupt mask register aic_imr read-only 0x0 0x114 core interrupt status register aic_cisr read-only 0x0 0x118 reserved ? ? ? 0x11c reserved ? ? ? 0x120 interrupt enable command register aic_iecr write-only ? 0x124 interrupt disable command register aic_idcr write-only ? 0x128 interrupt clear command register aic_iccr write-only ? 0x12c interrupt set command register aic_iscr write-only ? 0x130 end of interrupt command register aic_eoicr write-only ? 0x134 spurious interrupt vector register aic_spu read/write 0x0 0x138 debug control register aic_dcr read/write 0x0 0x13c reserved ? ? ? 0x140 fast forcing enable register aic_ffer write-only ? 0x144 fast forcing disable register aic_ffdr write-only ? 0x148 fast forcing status register aic_ffsr read-only 0x0
245 AT91RM9200 1768b?atarm?08/03 aic source mode register register name: aic_smr0..aic_smr31 access type: read/write reset value: 0x0 prior: priority level programs the priority level for all sources except fiq source (source 0). the priority level can be between 0 (lowest) and 7 (highest). the priority level is not used for the fiq in the related smr register aic_smrx. srctype: interrupt source type the active level or edge is not programmable for the internal interrupt sources. aic source vector register register name: aic_svr0..aic_svr31 access type: read/write reset value: 0x0 vector: source vector the user may store in these registers the addresses of the corresponding handler for each interrupt source. aic interrupt vector register register name: aic_ivr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? srctype ? ? prior srctype internal interrupt sources 0 0 level sensitive 0 1 edge triggered 1 0 level sensitive 1 1 edge triggered 31 30 29 28 27 26 25 24 vector 23 22 21 20 19 18 17 16 vector 15 14 13 12 11 10 9 8 vector 76543210 vector
246 AT91RM9200 1768b?atarm?08/03 access type: read-only reset value: 0 irqv: interrupt vector register the interrupt vector register contains the vector programmed by the user in the source vector register corresponding to the current interrupt. the source vector register is indexed using the current interrupt number when the interrupt vector register is read. when there is no current interrupt, the interrupt vector register reads the value stored in aic_spu. aic fiq vector register register name: aic_fvr access type: read-only reset value: 0 fiqv: fiq vector register the fiq vector register contains the vector programmed by the user in the source vector register 0. when there is no fast interrupt, the fast interrupt vector register reads the value stored in aic_spu. 31 30 29 28 27 26 25 24 irqv 23 22 21 20 19 18 17 16 irqv 15 14 13 12 11 10 9 8 irqv 76543210 irqv 31 30 29 28 27 26 25 24 fiqv 23 22 21 20 19 18 17 16 fiqv 15 14 13 12 11 10 9 8 fiqv 76543210 fiqv
247 AT91RM9200 1768b?atarm?08/03 aic interrupt st atus register register name: aic_isr access type: read-only reset value: 0 irqid: current interrupt identifier the interrupt status register returns the current interrupt source number. aic interrupt pending register register name: aic_ipr access type: read-only reset value: 0 fiq, sys, pid2-pid31: interrupt pending 0 = corresponding interrupt is no pending. 1 = corresponding interrupt is pending. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??? irqid 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq
248 AT91RM9200 1768b?atarm?08/03 aic interrupt mask register register name: aic_imr access type: read-only reset value: 0 fiq, sys, pid2-pid31: interrupt mask 0 = corresponding interrupt is disabled. 1 = corresponding interrupt is enabled. aic core interrupt status register register name: aic_cisr access type: read-only reset value: 0 nfiq: nfiq status 0 = nfiq line is deactivated. 1 = nfiq line is active. nirq: nirq status 0 = nirq line is deactivated. 1 = nirq line is active. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????nirqnifq
249 AT91RM9200 1768b?atarm?08/03 aic interrupt enable command register register name: aic_iecr access type: write-only fiq, sys, pid2-pid3: interrupt enable 0 = no effect. 1 = enables corresponding interrupt. aic interrupt disable command register register name: aic_idcr access type: write-only fiq, sys, pid2-pid31: interrupt disable 0 = no effect. 1 = disables corresponding interrupt. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq
250 AT91RM9200 1768b?atarm?08/03 aic interrupt clear command register register name: aic_iccr access type: write-only fiq, sys, pid2-pid31: interrupt clear 0 = no effect. 1 = clears corresponding interrupt. aic interrupt set command register register name: aic_iscr access type: write-only fiq, sys, pid2-pid31: interrupt set 0 = no effect. 1 = sets corresponding interrupt. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq
251 AT91RM9200 1768b?atarm?08/03 aic end of interrupt command register register name: aic_eoicr access type: write-only the end of interrupt command register is used by the interrupt routine to indicate that the interrupt treatment is complete. any value can be written because it is only necessary to make a write to this register location to signal the end of interrupt treatment. aic spurious interr upt vector register register name: aic_spu access type: read/write reset value: 0 siqv: spurious interrupt vector register the use may store the address of a spurious interrupt handler in this register. the written value is returned in aic_ivr in case of a spurious interrupt and in aic_fvr in case of a spurious fast interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????? 31 30 29 28 27 26 25 24 siqv 23 22 21 20 19 18 17 16 siqv 15 14 13 12 11 10 9 8 siqv 76543210 siqv
252 AT91RM9200 1768b?atarm?08/03 aic debug control register register name: aic_debug access type: read/write reset value: 0 prot: protection mode 0 = the protection mode is disabled. 1 = the protection mode is enabled. gmsk: general mask 0 = the nirq and nfiq lines are normally controlled by the aic. 1 = the nirq and nfiq lines are tied to their inactive state. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????gmskprot
253 AT91RM9200 1768b?atarm?08/03 aic fast forcing enable register register name: aic_ffer access type: write-only sys, pid2-pid31: fast forcing enable 0 = no effect. 1 = enables the fast forcing feature on the corresponding interrupt. aic fast forcing disable register register name: aic_ffdr access type: write-only sys, pid2-pid31: fast forcing disable 0 = no effect. 1 = disables the fast forcing feature on the corresponding interrupt. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys ? 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys ?
254 AT91RM9200 1768b?atarm?08/03 aic fast forcing status register register name: aic_ffsr access type: read-only sys, pid2 - pid31: fast forcing status 0 = the fast forcing feature is disabled on the corresponding interrupt. 1 = the fast forcing feature is enable on the corresponding interrupt. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys ?
255 AT91RM9200 1768b?atarm?08/03 power management controller (pmc) overview the power management controller (pmc) generates all the clocks of a system thanks to the integration of two oscillators and two plls. the pmc provides clocks to the embedded processor and enables the idle mode by stopping the processor clock until the next interrupt. the pmc independently provides and controls up to thirty peripheral clocks and four programmable clocks that can be used as outputs on pins to feed external devices. the integration of the plls supplies the usb devices and host ports with a 48 mhz clock, as required by the bus speed, and the rest of the system with a clock at another frequency. thus, the fully-featured power management controller optimizes power consumption of the whole system and supports the normal, idle, slow clock and standby operating modes. the main features of the pmc are: optimize the power consumption of the whole system embeds and controls: ? one main oscillator and one slow clock oscillator (32.768 khz) ? two phase locked loops (plls) and dividers ?clock prescalers provides: ? the processor clock pck ? the master clock mck ? the usb clocks, uhpck and udpck, respectively for the usb host port and the usb device port ? programmable automatic pll switch-off in usb device suspend conditions ? up to thirty peripheral clocks ? up to four programmable clock outputs four operating modes: ? normal mode, idle mode, slow clock mode, standby mode
256 AT91RM9200 1768b?atarm?08/03 product dependencies i/o lines the power management controller is capable of handling up to four programmable clocks, pck0 to pck3. a programmable clock is generally multiplexed on a pio controller. the user must first program the pio controllers to assign the pins of the programmable clock to its periph- eral function. interrupt the power management controller has an inte rrupt line connected to the advanced interrupt controller (aic). handling the pmc interrupt requires programming the aic before configuring the pmc. oscillator and pll characteristics the electrical characteristics of the embedded oscillators and plls are product-depen- dent, even if the way to control them is similar. all of the parameters for both oscillators and the plls are given in the dc characteris- tics section of the product datasheet. these figures are used not only for the hardware design, as they affect the external components to be connected to the pins, but also the software configuration, as they determine the waiting time for the startup and lock times to be programmed. peripheral clocks the power management controller provides and controls up to thirty peripheral clocks. the bit number permitting the control of a peripheral clock is the peripheral id of the embedded peripheral. when the peripheral id does not correspond to a peripheral, either because this is an external interrupt or because there are less than thirty peripherals, the control bits of the peripheral id are not implemented in the pmc and programming them has no effect on the behavior of the pmc. usb clocks the power management controller provides and controls two usb clocks, the uhpck for the usb host port, and the udpck for the usb device. if the product does not embed either the usb host port or the usb device port, the associated control bits and registers are not implemented in the pmc and programming them has no effect on the behavior of the pmc.
257 AT91RM9200 1768b?atarm?08/03 block diagram figure 117. power management controller block diagram apb pio pck0-pck3 arm7 processor user interface udp uhp embedded peripherals mck (continuous) processor clock mck (individually switchable) aic st rtc slck pmcirq xin32 xout32 xin xout pllrca pllrcb irq or fiq udpck uhpck programmable clocks memory controller suspend slow clock slck main clock plla clock pllb clock slck main clock plla clock pllb clock prescaler /2,/4,...,/64 arm920t processor processor clock processor clock controller idle mode divider /1,/2,/3,/4 arm9-systems only master clock controller peripherals clock controller on/off usb clock controller on/off slck main clock plla clock pllb clock prescaler /2,/4,...,/64 programmable clock controller slow clock slck pllb clock 30 4 slow clock oscillator main oscillator pll and divider a pll and divider b clock generator power management controller
258 AT91RM9200 1768b?atarm?08/03 functional description operating modes definition the following operating modes are supported by the pmc and offer different power con- sumption levels and event response latency times: normal mode: the arm processor clock is enabled and peripheral clocks are enabled depending on application requirements. idle mode: the arm processor clock is disabled and waiting for the next interrupt (or a main reset). the peripheral clocks are enabled depending on application requirements. pdc transfers are still possible. slow clock mode: slow clock mode is similar to normal mode, but the main oscillator and the pll are switched off to save power and the processor and the peripherals run in slow clock mode. note that slow clock mode is the mode selected after the reset. standby mode: standby mode is a combination of slow clock mode and idle mode. it enables the processor to respond quickly to a wake-up event by keeping power consumption very low. clock definitions the power management controller provides the following clocks: slow clock (slck), typically at 32.768 khz, is the only permanent clock within the system. master clock (mck), programmable from a few hundred hz to the maximum operating frequency of the device. it is available to the modules running permanently, such as the aic and the memory controller. processor clock (pck), typically the master clock for arm7-based systems and a faster clock on arm9-based systems, switched off when entering idle mode. peripheral clocks, typically mck, provided to the embedded peripherals (usart, ssc, spi, twi, tc, mci, etc.) and independently controllable. in order to reduce the number of clock names in a product, the peripheral clocks are named mck in the product datasheet. udp clock (udpck), typically at 48 mhz, required by the usb device port operations. uhp clock (uhpck), typically at 48 mhz, required by the usb host port operations. programmable clock outputs (pck0 to pck3) can be selected from the clocks provided by the clock generator and driven on the pck0 to pck3 pins. clock generator the clock generator embeds: the slow clock oscillator the main oscillator two pll and divider blocks, a and b the clock generator may optionally integrate a divider by 2. the arm7-based systems generally embed plls able to output between 20 mhz and 100 mhz and do not embed the divider by 2. the arm9-based systems generally embed plls able to output between 80 mhz and 240 mhz. as the 48 mhz required by the usb cannot be reached by such a pll, the optional divider by 2 is implemented. the block diagram of the clock generator is shown in figure 118.
259 AT91RM9200 1768b?atarm?08/03 figure 118. clock generator block diagram slow clock oscillator slow clock oscillator connection the clock generator integrates a low-power 32.768 khz oscillator. the xin32 and xout32 pins must be connected to a 32.768 khz crystal. two external capacitors must be wired as shown in figure 119. figure 119. typical slow clock oscillator connection slow clock oscillator startup time the startup time of the slow clock oscillator is given in the dc characteristics section of the product datasheet. as it is often higher than 500 ms and the processor requires an assertion of the reset until it has stabilized, the user must implement an external reset supervisor covering this startup time. however, this startup is only required in case of cold reset, i.e., in case of system power-up. when a warm reset occurs, the length of the reset pulse may be much lower. for further details, see ?AT91RM9200 reset con- troller? on page 119. slow clock oscillator main oscillator clock generator xin32 xout32 xin xout pllrca pllrcb slow clock slck main clock plla clock pllb clock pll a divider a divider b pll b /2 (optional) main clock frequency counter xin32 xout32 gndpll c l2 c l1 32.768 khz crystal
260 AT91RM9200 1768b?atarm?08/03 main oscillator figure 120 shows the main oscillator block diagram. figure 120. main oscillator block diagram main oscillator connections the clock generator integrates a main oscillator that is designed for a 3 to 20 mhz fun- damental crystal. the typical crystal connection is illustrated in figure 121. the 1 k ? resistor is only required for crystals with frequencies lower than 8 mhz. the oscillator contains twenty-five pf capacitors on each xin and xout pin. consequently, cl1 and cl2 can be removed when a crystal with a load capacitance of 12.5 pf is used. for fur- ther details on the electric al characteristics of the main oscillator, see the dc characteristics section of the product datasheet. figure 121. typical crystal connection main oscillator startup time the startup time of the main oscillator is given in the dc characteristics section of the product datasheet. the startup time depends on the crystal frequency and increases when the frequency rises. main oscillator control to minimize the power required to start up the system, the main oscillator is disabled after reset and the slow clock mode is selected. the software enables or disables the main oscillator so as to reduce power consump- tion by clearing the moscen bit in the main oscillator register (ckgr_mor). when disabling the main oscillator by clearing the moscen bit in ckgr_mor, the moscs bit in pmc_sr is automatically cleared indicating the main clock is off. main oscillator xin xout moscen main oscillator counter oscount moscs slow clock main clock main clock frequency counter mainf mainrdy xin xout gndpll c l2 c l1 1k
261 AT91RM9200 1768b?atarm?08/03 when enabling the main oscillator, the user must initiate the main oscillator counter with a value corresponding to the startup time of the oscillator. this startup time depends on the crystal frequency connected to the main oscillator. when the moscen bit and the oscount are written in ckgr _mor to enable the main oscillator, the moscs bit is cleared and the counter starts counting down on the slow clock divided by 8 from the oscount value. since the oscount value is coded with 8 bits, the maximum startup time is about 62 ms. when the counter reaches 0, the moscs bit is set, indicating that the main clock is valid. setting the moscs bit in pmc_imr can trigger an interrupt to the processor on this event. main clock frequency counter the main oscillator features a main clock frequency counter that provides the quartz frequency connected to the main oscillator. g enerally, this value is known by the sys- tem designer; however, it is useful for the boot program to configure the device with the correct clock speed, independently of the application. the main clock frequency counter starts incrementing at the main clock speed after the next rising edge of the slow clock as soon as the main oscillator is stable, i.e., as soon as the moscs bit is set. then, at the 16th falling edge of slow clock, the bit mainrdy in ckgr_mcfr (main clock frequency regist er) is set and the counter stops count- ing. its value can be read in the mainf field of ckgr_mcfr and gives the number of main clock cycles during 16 periods of slow clock, so that the frequency of the crystal connected on the main oscillator can be determined. main oscillator bypass the user can input a clock on the device instead of connecting a crystal. in this case, the user has to provide the external clock signal on the pin xin. the input characteristics of the xin pin under these conditions are given in the product electrical characteristics section. the programmer has to be sure not to modify the moscen bit in the main oscillator register (ckgr_mor). this bit must remain at 0, its reset value, for the external clock to operate properly. while this bit is at 0, the pin xin is tied low to prevent any internal oscillation regardless of pin connected. the external clock signal must meet the requirements relating to the power supply vddpll (i.e., between 1.65v and 1.95v) and cannot exceed 50 mhz.
262 AT91RM9200 1768b?atarm?08/03 divider and pll blocks the clock generator features two divider/pll blocks that generates a wide range of frequencies. additionally, they provide a 48 mhz signal to the embedded usb device and/or host ports, regardless of the frequency of the main clock. figure 122 shows the block diagram of the divider and pll blocks. figure 122. divider and pll blocks block diagram pll filters the two plls require connection to an exte rnal second-order filter through the pins pllrc. figure 123 shows a schematic of these filters. figure 123. pll capacitors and resistors values of r, c1 and c2 to be connected to the pllrc pins must be calculated as a function of the pll input frequency, the pll output frequency and the phase margin. a trade-off has to be found between output signal overshoot and startup time. divider b pllrcb divb pll b mulb divider a pllrca diva pll a pll b counter pllbcount lockb pll a counter pllacount locka mula outb outa pll b output slow clock main clock pll a output gnd c1 c2 pll pllrc r
263 AT91RM9200 1768b?atarm?08/03 pll source clock the source of plls a and b is respectively the output of divider a, i.e. the main clock divided by diva, and the output of divider b, i.e. the main clock divided by divb. as the input frequency of the plls is limited, the user has to make sure that the pro- gramming of diva and divb are compliant with the input frequency range of the plls, which is given in the dc characteristics section of the product datasheet. divider and phase lock loop programming the two dividers increase the accuracy of the plla and the pllb clocks independently of the input frequency. the main clock can be divided by programming the divb field in ckgr_pllbr and the diva field in ckgr_pllar. each divider can be set between 1 and 255 in steps of 1. when the diva and divb fields are set to 0, the output of the divider and the pll out- puts a and b are a continuous signal at level 0. on reset, the diva and divb fields are set to 0, thus both pll input clocks are set to 0. the two plls of the clock generator allow multiplication of the divider?s outputs. the plla and the pllb clock signals have a frequency that depends on the respective source signal frequency and on the parameters div (diva, divb) and mul (mula, mulb). the factor applied to the source signal frequency is (mul + 1)/div. when mula or mulb is written to 0, the corresponding pll is disabled and its power con- sumption is saved. re-enabling the plla or the pllb can be performed by writing a value higher than 0 in the mula or mulb field, respectively. whenever a pll is re-enabled or one of its parameters is changed, the locka or lockb bit in pmc_sr is automatically cleared. the values written in the pllacount or pllbcount fields in ckgr_pplar and ckgr_pllbr, respectively, are loaded in the corresponding pll counter. the pll counter then decrements at the speed of the slow clock until it reaches 0. at this time, the corresponding lock bit is set in pmc_sr and can trigger an interrupt to the processor. the user has to load the number of slow clock cycles required to cover the pll transient time into the pllacount and pllb- count field. the transient time depends on the pll filters. the initial state of the pll and its target frequency can be calculated using a specific tool provided by atmel. pllb divider by 2 in arm9-based systems, the pllb clock may be divided by two. this divider can be enabled by setting the bit usb_96m of ckgr _pllbr. in this case, the divider by 2 is enabled and the pllb must be programmed to output 96 mhz and not 48 mhz, thus ensuring correct operation of the usb bus. clock controllers the power management controller provides the clocks to the different peripherals of the system, either internal or external. it embeds the following elements: the master clock controller, which selects the master clock. the processor clock controller, which implements the idle mode. the peripheral clock controller, which provides power saving by controlling clocks of the embedded peripherals. the usb clock controller, which distributes the 48 mhz clock to the usb controllers. the programmable clock controller, which allows generation of up to four programmable clock signals on external pins. master clock controller the master clock controller provides selection and division of the master clock (mck). mck is the clock provided to all the peripherals and the memory controller. the master clock is selected from one of the clocks provided by the clock generator. selecting the slow clock enables slow clock mode by providing a 32.768 khz signal to the whole device. selecting the main clock saves power consumption of both plls, but
264 AT91RM9200 1768b?atarm?08/03 prevents using the usb ports. selecting the pllb clock saves the power consumption of the plla by running the processor and the peripheral at 48 mhz required by the usb ports. selecting the plla clock runs the processor and the peripherals at their maxi- mum speed while running the usb ports at 48 mhz. the master clock controller is made up of a clock selector and a prescaler, as shown in figure 124. it also contains an optional master clock divider in products integrating an arm9 processor. this allows the processor clock to be faster than the master clock. the master clock selection is made by writing the css field (clock source selection) in pmc_mckr (master clock register). the prescaler supports the division by a power of 2 of the selected clock between 1 and 64. the pres field in pmc_mckr programs the prescaler. when the master clock divider is implemented, it can be programmed between 1 and 4 through the mdiv field in pmc_mckr. each time pmc_mckr is written to define a new master clock, the mckrdy bit is cleared in pmc_sr. it reads 0 until the master clock is established. then, the mck- rdy bit is set and can trigger an interrupt to the processor. this feature is useful when switching from a high-speed clock to a lower one to inform the software when the change is actually done. note: a new value to be written in pmc_mckr must not be the same as the current value in pmc_mckr. figure 124. master clock controller processor clock controller the pmc features a processor clock controller that implements the idle mode. the processor clock can be enabled and disabled by writing the system clock enable (pmc_scer) and system clock disable registers (pmc_scdr). the status of this clock (at least for debug purpose) can be read in the system clock status register (pmc_scsr). processor clock source the clock provided to the processor is determined by the master clock controller. on arm7-based systems, the processor clock source is directly the master clock. on arm9-based systems, the processor clock source might be 2, 3 or 4 times the mas- ter clock. this ratio value is determined by programming the field mdiv of the master clock register (pmc_mckr). idle mode the processor clock is enabled after a reset and is automatically re-enabled by any enabled interrupt. the idle mode is achieved by disabling the processor clock, which is automatically re-enabled by any enabled fast or normal interrupt, or by the reset of the product. slck master clock prescaler mck pres cd master clock divider to the processor clock controller main clock plla clock pllb clock mdiv to the processor clock controller mck arm9 products arm7 products
265 AT91RM9200 1768b?atarm?08/03 when the processor clock is disabled, the current instruction is finished before the clock is stopped, but this does not prevent data transfers from other masters of the system bus. peripheral clock controller the pmc controls the clocks of each embedded peripheral. the user can individually enable and disable the master clock on the peripherals by writing into the peripheral clock enable (pmc_pcer) and peripheral clock disable (pmc_pcdr) registers. the status of the peripheral clock activity can be read in the peripheral clock status register (pmc_pcsr). when a peripheral clock is disabled, the clock is immediately stopped. when the clock is re-enabled, the peripheral resumes action where it left off. the peripheral clocks are automatically disabled after a reset. in order to stop a peripheral, it is recommended that the system software wait until the peripheral has executed its last programmed operation before disabling the clock. this is to avoid data corruption or erroneous behavior of the system. the bit number within the peripheral clock control registers (pmc_pcer, pmc_pcdr, and pmc_pcsr) is the peripheral identifier defined at the product level. generally, the bit number corresponds to the interrupt source number assigned to the peripheral. usb clock controller if using one of the usb ports, the user has to program the divider and pll b block to output a 48 mhz signal with an accuracy of 0.25%. when the clock for the usb is stable, the usb device and host clocks, udpck and uhpck, can be enabled. they can be disabled when the usb transactions are finished, so that the power consumption generated by the 48 mhz signal on these peripherals is saved. the usb ports require both the 48 mhz signal and the master clock. the master clock may be controlled via the peripheral clock controller. usb device clock control the usb device port clock udpck can be enabled by writing 1 at the udp bit in pmc_scer (system clock enable register) and disabled by writing 1 at the bit udp in pmc_scdr (system clock disable register). the activity of udpck is shown in the bit udp of pmc_scsr (system clock status register). usb device port suspend when the usb device port detects a suspend condition, the 48 mhz clock is automati- cally disabled, i.e., the udp bit in pmc_scsr is cleared. it is also possible to automatically disable the master clock provided to the usb device port on a suspend condition. the mckudp bit in pmc_scsr configures this feature and can be set or cleared by writing one in the same bit of pmc_scer and pmc_scdr. usb host clock control the usb host port clock uhpck can be enabled by writing 1 at the uhp bit in pmc_scer (system clock enable register) and disabled by writing 1 at the uhp bit in pmc_scdr (system clock disable register). the activity of udpck is shown in the bit uhp of pmc_scsr (system clock status register). programmable clock output controller the pmc controls up to four signals to be output on external pins pck0 to pck3. each signal can be independently programmed via the registers pmc_pck0 to pmc_pck3. pck0 to pck3 can be independently selected between the four clocks provided by the clock generator by writing the css field in pmc_pck0 to pmc_pck3. each output signal can also be divided by a power of 2 between 1 and 64 by writing the field pres (prescaler) in pmc_pck0 to pmc_pck3.
266 AT91RM9200 1768b?atarm?08/03 each output signal can be enabled and disabled by writing 1 in the corresponding bit pck0 to pck3 of pmc_scer and pmc_scdr, respectively. status of the active pro- grammable output clocks are given in the bits pck0 to pck3 of pmc_scsr (system clock status register). moreover, like the mck, a status bit in pmc_sr indicates that the programmable clock is actually what has been programmed in the programmable clock registers. as the programmable clock controller does not manage with glitch prevention when switching clocks, it is strongly recommended to disable the programmable clock before any configuration change and to re-enable it after the change is actually performed. note also that it is required to assign the pin to the programmable clock operation in the pio controller to enable the signal to be driven on the pin.
267 AT91RM9200 1768b?atarm?08/03 clock switching details master clock switching timings table 60 gives the worst case timing required for the master clock to switch from one selected clock to another one. this is in the event that the prescaler is de-activated. when the prescaler is activated, an additional time of 64 clock cycles of the new selected clock has to be added. table 60. clock switching timings (worst case) from main clock slck plla clock pllb clock to main clock ? 4 x slck + 2.5 x main clock 3 x plla clock + 4 x slck + 1 x main clock 3 x pllb clock + 4 x slck + 1 x main clock slck 0.5 x main clock + 4.5 x slck ? 3 x plla clock + 5 x slck 3 x pllb clock + 5 x slck plla clock 0.5 x main clock + 4 x slck + pllacount x slck + 2.5 x plla clock 2.5 x plla clock + 5 x slck + pllacount x slck 2.5 x plla clock + 4 x slck + pllb count x slck 3 x plla clock + 4 x slck + 1.5 x plla clock pllb clock 0.5 x main clock + 4 x slck + pllbcount x slck + 2.5 x pllb clock 2.5 x pllb clock + 5 x slck + pllbcount x slck 3 x pllb clock + 4 x slck + 1.5 x pllb clock 2.5 x pllb clock + 4 x slck + pllacount x slck
268 AT91RM9200 1768b?atarm?08/03 clock switching waveforms figure 125. switch master clock from slow clock to plla clock figure 126. switch master clock from main clock to slow clock slow clock lock a mckrdy master clock write pmc_mckr plla clock slow clock main clock mckrdy master clock write pmc_mckr
269 AT91RM9200 1768b?atarm?08/03 figure 127. change plla programming figure 128. programmable clock output programming slow clock plla clock locka mckrdy master clock write ckgr_pllar slow clock plla clock pckrdy pckx output write pmc_pckx write pmc_scer write pmc_scdr pckx is disabled pckx is enabled plla clock is selected
270 AT91RM9200 1768b?atarm?08/03 power management controller (pmc) user interface table 61. register mapping offset register name access reset value 0x0000 system clock enable register pmc_scer write-only ? 0x0004 system clock disable register pmc_scdr write-only ? 0x0008 system clock status register pmc _scsr read-only 0x01 0x000c reserved ? ? ? 0x0010 peripheral clock enable register pmc _pcer write-only ? 0x0014 peripheral clock disable register pmc_pcdr write-only ? 0x0018 peripheral clock status register pmc_pcsr read-only 0x0 0x001c reserved ? ? ? 0x0020 main oscillator register ckgr_mor readwrite 0x0 0x0024 main clock frequency register ckgr_mcfr read-only - 0x0028 pll a register ckgr_pllar readwrite 0x3f00 0x002c pll b register ckgr_pllbr readwrite 0x3f00 0x0030 master clock register pmc_mckr read/write 0x00 0x0034 reserved ? ? ? 0x0038 reserved ? ? ? 0x003c reserved ? ? ? 0x0040 programmable clock 0 register pmc_pck0 read/write 0x0 0x0044 programmable clock 1 register pmc_pck1 read/write 0x0 0x0048 programmable clock 2 register pmc_pck2 read/write 0x0 0x004c programmable clock 3 register pmc_pck3 read/write 0x0 0x0050 reserved ? ? ? 0x0054 reserved ? ? ? 0x0058 reserved ? ? ? 0x005c reserved ? ? ? 0x0060 interrupt enable register pmc_ier write-only -- 0x0064 interrupt disable register pmc_idr write-only -- 0x0068 status register pmc_sr read-only -- 0x006c interrupt mask register pmc_imr read-only 0x0
271 AT91RM9200 1768b?atarm?08/03 pmc system clock enable register register name: pmc_scer access type: write-only pck: processor clock enable 0 = no effect. 1 = enables the processor clock. udp: usb device port clock enable 0 = no effect. 1 = enables the 48 mhz clock of the usb device port. mckudp: usb device port master clock automatic disable on suspend enable 0 = no effect. 1 = enables the automatic disable of the master clock of the usb device port when a suspend condition occurs. uhp: usb host port clock enable 0 = no effect. 1 = enables the 48 mhz clock of the usb host port. pck0...pck3: programmable clock output enable 0 = no effect. 1 = enables the corresponding programmable clock output. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? ? ? pck3 pck2 pck1 pck0 76543210 ? ? ? uhp ? mckudp udp pck
272 AT91RM9200 1768b?atarm?08/03 pmc system clock disable register register name: pmc_scdr access type: write-only pck: processor clock disable 0 = no effect. 1 = disables the processor clock. udp: usb device port clock disable 0 = no effect. 1 = disables the 48 mhz clock of the usb device port. mckudp: usb device port master clock automatic disable on suspend disable 0 = no effect. 1 = disables the automatic disable of the master clock of the usb device port when a suspend condition occurs. uhp: usb host port clock disable 0 = no effect. 1 = disables the 48 mhz clock of the usb host port. pck0...pck3: programmable clock output disable 0 = no effect. 1 = disables the corresponding programmable clock output. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? ? ? pck3 pck2 pck1 pck0 76543210 ? ? ? uhp ? mckudp udp pck
273 AT91RM9200 1768b?atarm?08/03 pmc system clock status register register name: pmc_scsr access type: read-only pck: processor clock status 0 = the processor clock is disabled. 1 = the processor clock is enabled. udp: usb device port clock status 0 = the 48 mhz clock of the usb device port is disabled. 1 = the 48 mhz clock of the usb device port is enabled. mckudp: usb device port master clock automatic disable on suspend status 0 = the automatic disable of the master clock of the usb device port when suspend condition occurs is disabled. 1 = the automatic disable of the master clock of the usb device port when suspend condition occurs is enabled. uhp: usb host port clock status 0 = the 48 mhz clock of the usb host port is disabled. 1 = the 48 mhz clock of the usb host port is enabled. pck0...pck3: programmable clock output status 0 = the corresponding programmable clock output is disabled. 1 = the corresponding programmable clock output is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? ? ? pck3 pck2 pck1 pck0 76543210 ? ? ? uhp ? mckudp udp pck
274 AT91RM9200 1768b?atarm?08/03 pmc peripheral clock enable register register name: pmc_pcer access type: write-only pid2...pid31: peripheral clock enable 0 = no effect. 1 = enables the corresponding peripheral clock. pmc peripheral clock disable register register name: pmc_pcdr access type: write-only pid2...pid31: peripheral clock disable 0 = no effect. 1 = disables the corresponding peripheral clock. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 ? ? 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 ? ?
275 AT91RM9200 1768b?atarm?08/03 pmc peripheral cloc k status register register name: pmc_pcsr access type: read-only pid2...pid31: peripheral clock status 0 = the corresponding peripheral clock is disabled. 1 = the corresponding peripheral clock is enabled. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 ? ?
276 AT91RM9200 1768b?atarm?08/03 pmc clock generator main oscillator register register name: ckgr_mor access type: read/write moscen: main oscillator enable 0 = the main oscillator is disabled. main clock is the signal connected on xin. 1 = the main oscillator is enabled. a crystal must be connected between xin and xout. oscount: main oscillator start-up time specifies the number of slow clock cycles for the main oscillator start-up time. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 oscount 76543210 ?????? -moscen
277 AT91RM9200 1768b?atarm?08/03 pmc clock generator main clock frequency register register name: ckgr_mcfr access type: read-only mainf: main clock frequency gives the number of main clock cycles within 16 slow clock periods. mainrdy: main clock ready 0 = mainf value is not valid or the main oscillator is disabled. 1 = the main oscillator has been enabled previously and mainf value is available. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????mainrdy 15 14 13 12 11 10 9 8 mainf 76543210 mainf
278 AT91RM9200 1768b?atarm?08/03 pmc clock generator pll a register register name: ckgr_pllar access type: read/write possible limitations on pll a input frequencies and multiplier factors should be checked before using the clock generator. diva: divider a pllacount: pll a counter specifies the number of slow clock cycles before the locka bit is set in pmc_sr after ckgr_pllar is written. outa: pll a clock frequency range mula: pll a multiplier 0 = the pll a is deactivated. 1 up to 2047 = the pll a clock frequency is the pll a input frequency multiplied by mula + 1. 31 30 29 28 27 26 25 24 ??1?? mula 23 22 21 20 19 18 17 16 mula 15 14 13 12 11 10 9 8 outa pllacount 76543210 diva diva divider selected 0 divider output is 0 1 divider is bypassed 2 - 255 divider output is the main clock divided by diva. outa pll a frequency output range 0 0 80 mhz to 160 mhz 01reserved 1 0 150 mhz to 240 mhz 11reserved
279 AT91RM9200 1768b?atarm?08/03 pmc clock generator pll b register register name: ckgr_pllbr access type: read/write divb: divider b pllbcount: pll b counter specifies the number of slow clock cycles before the lockb bit is set in pmc_sr after ckgr_pllbr is written. outb: pll b clock frequency range mulb: pll b multiplier 0 = the pll b is deactivated. 1 up to 2047 = the pll b clock frequency is the pll b input frequency multiplied by mulb + 1. usb_96m: divider by 2 enable (only on arm9-based systems) 0 = usb ports clocks are pll b clock, therefore the pmc clock generator must be programmed for the pll b clock to be 48 mhz. 1 = usb ports clocks are pll b clock divided by 2, therefore the pmc clock generator must be programmed for the pll b clock to be 96 mhz. 31 30 29 28 27 26 25 24 ? ? ? usb_96m ? mulb 23 22 21 20 19 18 17 16 mulb 15 14 13 12 11 10 9 8 outb pllbcount 76543210 divb divb divider selected 0 divider output is 0 1 divider is bypassed 2 - 255 divider output is the selected clock divided by divb. outb pll b clock frequency range 0 0 80 mhz to 160 mhz 01reserved 1 0 150 mhz to 240 mhz 11reserved
280 AT91RM9200 1768b?atarm?08/03 pmc master clock register register name: pmc_mckr access type: read/write note: value to be written in pmc_mckr must not be the same as current value in pmc_mckr. css: master clock selection pres: master clock prescaler mdiv: master clock division (on arm9-based systems only) 0 = the master clock and the processor clock are the same. 1 = the processor clock is twice as fast as the master clock. 2 = the processor clock is three times faster than the master clock. 3 = the processor clock is four times faster than the master clock. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? mdiv 76543210 ? ? pres css css clock source selection 0 0 slow clock is selected 0 1 main clock is selected 1 0 pll a clock is selected 1 1 pll b clock is selected pres master clock 0 0 0 selected clock 0 0 1 selected clock divided by 2 0 1 0 selected clock divided by 4 0 1 1 selected clock divided by 8 1 0 0 selected clock divided by 16 1 0 1 selected clock divided by 32 1 1 0 selected clock divided by 64 111reserved
281 AT91RM9200 1768b?atarm?08/03 pmc programmable clock register 0 to 3 register name: pmc_pck0..pmc_pck3 access type: read/write css: master clock selection pres: programmable clock prescaler 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??? pres css css clock source selection 0 0 slow clock is selected 0 1 main clock is selected 1 0 pll a clock is selected 1 1 pll b clock is selected pres master clock 0 0 0 selected clock 0 0 1 selected clock divided by 2 0 1 0 selected clock divided by 4 0 1 1 selected clock divided by 8 1 0 0 selected clock divided by 16 1 0 1 selected clock divided by 32 1 1 0 selected clock divided by 64 111reserved
282 AT91RM9200 1768b?atarm?08/03 pmc interrupt enable register register name: pmc_ier access type: write-only moscs: main oscillator status locka: pll a lock lockb: pll b lock mckrdy: master clock ready pck0rdy - pck3rdy: programmable clock ready 0 = no effect. 1 = enables the corresponding interrupt. pmc interrupt disable register register name: pmc_idr access type: write-only moscs: main oscillator status locka: pll a lock lockb: pll b lock mckrdy: master clock ready pck0rdy - pck3rdy: programmable clock ready 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? ? ? pck3rdy pck2rdy pck1rdy pck0rdy 76543210 ? ? ? ? mckrdy lockb locka moscs 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? ? ? pck3rdy pck2rdy pck1rdy pck0rdy 76543210 ? ? ? ? mckrdy lockb locka moscs
283 AT91RM9200 1768b?atarm?08/03 pmc status register register name: pmc_sr access type: read-only moscs: moscs flag status 0 = main oscillator is not stabilized. 1 = main oscillator is stabilized. locka: plla lock status 0 = plll a is not locked 1 = pll a is locked. lockb: pllb lock status 0 = pll b is not locked. 1 = pll b is locked. mckrdy: master clock status 0 = mck is not ready. 1 = mck is ready. pck0rdy - pck3rdy: programmable clock ready status 0 = programmable clock 0 to 3 is not ready. 1 = programmable clock 0 to 3 is ready. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? ? ? pck3rdy pck2rdy pck1rdy pck0rdy 76543210 ? ? ? ? mckrdy lockb locka moscs
284 AT91RM9200 1768b?atarm?08/03 pmc interrupt mask register register name: pmc_imr access type: read-only moscs: main oscillator status locka: pll a lock lockb: pll b lock mckrdy: master clock ready pck0rdy - pck3rdy: programmable clock ready moscs: moscs interrupt mask 0 = the corresponding interrupt is enabled. 1 = the corresponding interrupt is disabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? ? ? pck3rdy pck2rdy pck1rdy pck0rdy 76543210 ? ? ? ? mckrdy lockb locka moscs
285 AT91RM9200 1768b?atarm?08/03 system timer (st) overview the system timer (st) module integrates three different free-running timers: a period interval timer (pit) that sets the time base for an operating system. a watchdog timer (wdt) with system reset capabilities in case of software deadlock. a real-time timer (rtt) counting elapsed seconds. these timers count using the slow clock provided by the power management controller. typ- ically, this clock has a frequency of 32.768 khz, but the system timer might be configured to support another frequency. the system timer provides an interrupt line connected to one of the sources of the advanced interrupt controller (aic). interrupt handling requires programming the aic before configuring the system timer. usually, the system timer in terrupt line is connected to the first interrupt source line and shares this entry with the debug unit (dbgu) and the real time clock (rtc). this sharing requires the programmer to determine the source of the interrupt when the source 1 is triggered. important features of the system timer include: one period interval timer, 16-bit programmable counter one watchdog timer, 16-bit programmable counter one real-time timer, 20-bit free-running counter interrupt generation on event block diagram figure 129. system timer block diagram application block diagram figure 130. application block diagram system timer watchdog timer apb nwdovf power management controller stirq slck advanced interrupt controller real-time timer periodic interval timer os or rtos scheduler rtt pit wdt date, time and alarm manager system survey manager
286 AT91RM9200 1768b?atarm?08/03 product dependencies power management the system timer is continuously clocked at 32768 hz. the power management controller has no effect on the system timer behavior. interrupt sources the system timer interrupt is generally connected to the source 1 of the advanced interrupt controller. this interrupt line is the result of the or-wiring of the system peripheral interrupt lines (system timer, real time clock, power management controller, memory controller). when a system interrupt happens, the service routine must first determine the cause of the interrupt. this is accomplished by reading successively the status registers of the above men- tioned system peripherals. watchdog overflow the system timer is capable of driving the nwdovf pin. this pin might be implemented or not in a product. when it is implemented, this pin might or not be multiplexed on the pio con- trollers even though it is recommended to dedicate a pin to the watchdog function. if the nwdovf is multiplexed on a pio controller, this last should be first programmed to assign the pin to the watchdog function before using the pin as nwdovf. when it is not implemented, programming the associated bits and registers has no effect on the behavior of the system timer. functional description system timer clock the system timer uses only the slck clock so that it is capable to provide periodic, watch- dog, second change or alarm interrupt even if the power management controller is programmed to put the product in slow clock mode. if the product has the capability to back up the slow clock oscillator and the system timer, the system timer can continue to operate. period interval timer (pit) the period interval timer can be used to provide periodic interrupts for use by operating sys- tems. the reset value of the pit is 0 corresponding to the maximum value. it is built around a 16-bit down counter, which is preloaded by a value programmed in st_pimr (period interval mode register). when the pit counter reaches 0, the bit pits is set in st_sr (status regis- ter), and an interrupt is generated if it is enabled. the counter is then automatically reloaded and restarted. writing to the st_pimr at any time immediately reloads and restarts the down counter with the new programmed value. warning: if st_pimr is programmed with a period less or equal to the current mck period, the update of the pits status bit and its associated interrupt generation are unpredictable. figure 131. period interval timer 16-bit down counter slck slow clock pits piv
287 AT91RM9200 1768b?atarm?08/03 watchdog timer (wdt) the watchdog timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. it is built around a 16-bit down counter loaded with the value defined in st_wdmr (watchdog mode register). at reset, the value of the st_wdmr is 0x00020000, corresponding to the maximum value of the counter. the watchdog overflow signal is tied low during 8 slow clock cycles when a watchdog overflow occurs (exten bit set in st_wdmr). it uses the slow clock divided by 128 to es tablish the maximum watchdog period to be 256 seconds (with a typical slow clock of 32.768 khz). in normal operation, the user reloads the watchdog at regular intervals before the timer over- flow occurs, by setting the bit wdrst in the st_cr (control register). if an overflow does occur, the watchdog timer: sets the wdovf bit in st_sr (status register), from which an interrupt can be generated. generates a pulse for 8 slow clock cycles on the external signal watchdog overflow if the bit exten in st_wdmr is set. generates an internal reset if the parameter rsten in st_wdmr is set. reloads and restarts the down counter. writing the st_wdmr does not reload or restart the down counter. when the st_cr is writ- ten the watchdog counter is immediately reloaded from st_wdmr and restarted and the slow clock 128 divider is also immediately reset and restarted. figure 132. watchdog timer real-time timer (rtt) the real-time timer is used to count elapsed seconds. it is built around a 20-bit counter fed by slow clock divided by a programmable value. at reset, this value is set to 0x8000, corre- sponding to feeding the real-time counter with a 1 hz signal when the slow clock is 32.768 hz. the 20-bit counter can count up to 1048576 seconds, corresponding to more than 12 days, then roll over to 0. the real-time timer value can be read at any time in the register st_crtr (current real- time register). as this value can be updated asyn chronously to the master clock, it is advis- able to read this register twice at the same value to improve accuracy of the returned value. this current value of the counter is compared with the value written in the alarm register st_rtar (real-time alarm register). if the counter value matches the alarm, the bit alms in tc_sr is set. the alarm register is set to its maximum value, corresponding to 0, after a reset. the bit rttinc in st_sr is set each time the 20-bit counter is incremented. this bit can be used to start an interrupt, or generate a one-second signal. slck 1/128 wv wdrst 16-bit down counter rsten internal reset exten nwdovf wdovf status
288 AT91RM9200 1768b?atarm?08/03 writing the st_rtmr immediately reloads and restarts the clock divider with the new pro- grammed value. this also resets the 20-bit counter. warning: if rtpres is programmed with a period less or equal to the current mck period, the update of the rttinc and alms status bits and their associated interrupt generation are unpredictable. figure 133. real time timer slck rtpres rttinc alms 16-bit divider 20-bit counter = almv
289 AT91RM9200 1768b?atarm?08/03 system timer (st) user interface st control register register name: st_cr access type: write-only wdrst: watchdog timer restart 0 = no effect. 1 = reload the start-up value in the watchdog timer. table 62. system timer registers offset register name access reset value 0x0000 control register st_cr write-only ? 0x0004 period interval mode register st_pimr read/write 0x00000000 0x0008 watchdog mode register st_wdmr read/write 0x00020000 0x000c real-time mode register st_rtmr read/write 0x00008000 0x0010 status register st_sr read-only ? 0x0014 interrupt enable register st_ier write-only ? 0x0018 interrupt disable register st_idr write-only ? 0x001c interrupt mask register st_imr write-only 0x0 0x0020 real-time alarm register st_rtar read/write 0x0 0x0024 current real-time register st_crtr read-only 0x0 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????wdrst
290 AT91RM9200 1768b?atarm?08/03 st period interval mode register register name: st_pimr access type: read/write piv: period interval value defines the value loaded in the 16-bit counter of the period interval timer. the maximum period is obtained by programming piv at 0x0 corresponding to 65536 slow clock cycles. st watchdog mode register register name: st_wdmr access type: read/write wdv: watchdog counter value defines the value loaded in the 16-bit counter. the maximum period is obtained by programming wdv to 0x0 correspond- ing to 65536 x 128 slow clock cycles. rsten: reset enable 0 = no reset is generated when a watchdog overflow occurs. 1 = an internal reset is generated when a watchdog overflow occurs. exten: external signal assertion enable 0 = the watchdog_overflow is not tied low when a watchdog overflow occurs. 1 = the watchdog_overflow is tied low during 8 slow clock cycles when a watchdog overflow occurs. ???????? ???????? piv piv 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ??????extenrsten 15 14 13 12 11 10 9 8 wdv 76543210 wdv
291 AT91RM9200 1768b?atarm?08/03 st real-time mode register register name: st_rtmr access type: read/write rtpres: real-time timer prescaler value defines the number of slck periods required to increment the real-time timer. the maximum period is obtained by pro- gramming rtpres to 0x0 corresponding to 65536 slow clock cycles. st status register register name: st_sr access type: read-only pits: period interval timer status 0 = the period interval timer has not reached 0 since the last read of the status register. 1 = the period interval timer has reached 0 since the last read of the status register. wdovf: watchdog overflow 0 = the watchdog timer has not reached 0 since the last read of the status register. 1 = the watchdog timer has reached 0 since the last read of the status register. rttinc: real-time timer increment 0 = the real-time timer has not been incremented since the last read of the status register. 1 = the real-time timer has been incremented since the last read of the status register. alms: alarm status 0 = no alarm compare has been detected since the last read of the status register. 1 = alarm compare has been detected since the last read of the status register. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rtpres 76543210 rtpres 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????almsrttincwdovfpits
292 AT91RM9200 1768b?atarm?08/03 st interrupt enable register register name: st_ier access type: write-only pits: period interval timer status interrupt enable wdovf: watchdog overflow interrupt enable rttinc: real-time timer increment interrupt enable alms: alarm status interrupt enable 0 = no effect. 1 = enables the corresponding interrupt. st interrupt disable register register name: st_idr access type: write-only pits: period interval timer status interrupt disable wdovf: watchdog overflow interrupt disable rttinc: real-time timer increment interrupt disable alms: alarm status interrupt disable 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????almsrttincwdovfpits 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????almsrttincwdovfpits
293 AT91RM9200 1768b?atarm?08/03 st interrupt mask register register name: st_imr access type: read-only pits: period interval timer status interrupt mask wdovf: watchdog overflow interrupt mask rttinc: real-time timer increment interrupt mask alms: alarm status interrupt mask 0 = the corresponding interrupt is disabled. 1 = the corresponding interrupt is enabled. st real-time alarm register register name: st_rtar access type: read/write almv: alarm value defines the alarm value compared with the real-time timer. the maximum delay before alms status bit activation is obtained by programming almv to 0x0 corresponding to 1048576 seconds. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????almsrttincwdovfpits 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???? almv 15 14 13 12 11 10 9 8 almv 76543210 almv
294 AT91RM9200 1768b?atarm?08/03 st current real-time register register name: st_crtr access type: read-only crtv: current real-time value returns the current value of the real-time timer. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???? crtv 15 14 13 12 11 10 9 8 crtv 76543210 crtv
295 AT91RM9200 1768b?atarm?08/03 real time controller (rtc) overview the real-time clock (rtc) peripheral is designed for very low power consumption. it combines a complete time-of-day clock with alarm and a two-hundred-year gregorian calen- dar, complemented by a programmable periodic interrupt. the alarm and calendar registers are accessed by a 32-bit data bus. the time and calendar values are coded in binary-coded decimal (bcd) format. the time for- mat can be 24-hour mode or 12-hour mode with an am/pm indicator. updating time and calendar fields and configuring the alarm fields are performed by a parallel capture on the 32-bit data bus. an entry control is performed to avoid loading registers with incompatible bcd format data or with an incompatible date according to the current month/year/century. important features of the rtc include: low power consumption full asynchronous design two hundred year calendar programmable periodic interrupt alarm and update parallel load control of alarm and update time/calendar data in block diagram figure 134. rtc block diagram product dependencies power management the real-time clock is continuously clocked at 32768 hz. the power management controller has no effect on rtc behavior. interrupt the rtc interrupt is connected to interrupt source 1 (irq1) of the advanced interrupt control- ler. this interrupt line is due to the or-wiring of the system peripheral interrupt lines (system timer, real time clock, power management controller, memory controller, etc.). when a bus interface 32768 divider time crystal oscillator: slck bus interface date rtc interrupt entry control interrupt control
296 AT91RM9200 1768b?atarm?08/03 system interrupt occurs, the service routine must first determine the cause of the interrupt. this is done by reading the status registers of the above system peripherals successively. functional description the rtc provides a full binary-coded decimal (bcd) clock that includes century (19/20), year (with leap years), month, date, day, hours, minutes and seconds. the valid year range is 1900 to 2099, a two- hundred-year gregorian ca lendar achieving full y2k compliance. the rtc can operate in 24-hour mode or in 12-hour mode with an am/pm indicator. corrections for leap years are included (all years divisible by 4 being leap years, including year 2000). this is correct up to the year 2099. after hardware reset, the calendar is initialized to thursday, january 1, 1998. reference clock the reference clock is slow clock (slck). it can be driven by the atmel cell osc55 or osc56 (or an equivalent cell) and an external 32.768 khz crystal. during low power modes of the processor (idle mode), the oscillator runs and power consump- tion is critical. the crystal selection has to take into account the current consumption for power saving and the frequency drift due to temperature effect on the circuit for time accuracy. timing the rtc is updated in real time at one-second intervals in normal mode for the counters of seconds, at one-minute intervals for the counter of minutes and so on. due to the asynchronous operation of the rtc with respect to the rest of the chip, to be cer- tain that the value read in the rtc registers (century, year, month, date, day, hours, minutes, seconds) are valid and stable, it is necessary to read these registers twice. if the data is the same both times, then it is valid. therefore, a minimum of two and a maximum of three accesses are required. alarm the rtc has five programmable fields: month, date, hours, minutes and seconds. each of these fields can be enabled or disabled to match the alarm condition: if all the fields are enabled, an alarm flag is generated (the corresponding flag is asserted and an interrupt generated if enabled) at a given month, date, hour/minute/second. if only the ?seconds? field is enabled, then an alarm is generated every minute. depending on the combination of fields enabled, a large number of possibilities are available to the user ranging from minutes to 365/366 days. error checking verification on user interface data is perfo rmed when accessing the century, year, month, date, day, hours, minutes, seconds and alarms. a check is performed on illegal bcd entries such as illegal date of the month with regard to the year and century configured. if one of the time fields is not correct, the data is not loaded into the register/counter and a flag is set in the validity register. the user can not reset this flag. it is reset as soon as an accept- able value is programmed. this avoids any further side effects in the hardware. the same procedure is done for the alarm. the following checks are performed: 1. century (check if it is in range 19 - 20) 2. year (bcd entry check) 3. date (check range 01 - 31)
297 AT91RM9200 1768b?atarm?08/03 4. month (check if it is in bcd range 01 - 12, check validity regarding ?date?) 5. day (check range 1 - 7) 6. hour (bcd checks: in 24-hour mode, check range 00 - 23 and check that am/pm flag is not set if rtc is set in 24-hour mode; in 12-hour mode check range 01 - 12) 7. minute (check bcd and range 00 - 59) 8. second (check bcd and range 00 - 59) note: if the 12-hour mode is selected by means of the rtc_mode register, a 12-hour value can be programmed and the returned value on rtc_time will be the corresponding 24-hour value. the entry control checks the value of the am/pm indicator (bit 22 of rtc_time register) to determine the range to be checked. updating time/calendar to update any of the time/calendar fields, the user must first stop the rtc by setting the corre- sponding field in the control register. bit updtim must be set to update time fields (hour, minute, second) and bit updcal must be set to update calendar fields (century, year, month, date, day). then the user must poll or wait for the interrupt (if enabled) of bit ackupd in the status reg- ister. once the bit reads 1, the user can write to the appropriate register. once the update is finished, the user must reset (0) updtim and/or updcal in the control register. when programming the calendar fields, the time fields remain enabled. this avoids a time slip in case the user stays in the calendar update phase for several tens of seconds or more. in successive update operations, the user must wait at least one second after resetting the updtim/updcal bit in the rtc_cr (control register) before setting these bits again. this is done by waiting for the sec flag in the status register before setting updtim/updcal bit. after resetting updtim/updcal, the sec flag must also be cleared.
298 AT91RM9200 1768b?atarm?08/03 real time controller (rtc) user interface table 63. rtc register mapping offset register register name read/write reset 0x00 rtc control register rtc_cr read/write 0x0 0x04 rtc mode register rtc_mr read/write 0x0 0x08 rtc time register rtc_timr read/write 0x0 0x0c rtc calendar register rtc_calr read/write 0x01819819 0x10 rtc time alarm register rtc_timalr read/write 0x0 0x14 rtc calendar alarm register rtc_calalr read/write 0x01010000 0x18 rtc status register rtc_sr read only 0x0 0x1c rtc status clear command register rtc_sccr write only --- 0x20 rtc interrupt enable register rtc_ier write only --- 0x24 rtc interrupt disable register rtc_idr write only --- 0x28 rtc interrupt mask register rtc_imr read only 0x0 0x2c rtc valid entry register rtc_ver read only 0x0
299 AT91RM9200 1768b?atarm?08/03 rtc control register name: rtc_cr access type: read/write updtim: update request time register 0 = no effect. 1 = stops the rtc time counting. time counting consists of second, minute and hour counters . time counters can be programmed once this bit is set and acknowledged by the bit ackupd of the status register. updcal: update request calendar register 0 = no effect. 1 = stops the rtc calendar counting. calendar counting consists of day, date, month, year and century counters. calendar counters can be programmed once this bit is set. timevsel: time event selection the event that generates the flag timev in rtc_sr (status register) depends on the value of timevsel. 0 = minute change. 1 = hour change. 2 = every day at midnight. 3 = every day at noon. calevsel: calendar event selection the event that generates the flag calev in rtc_sr depends on the value of calevsel. 0 = week change (every monday at time 00:00:00). 1 = month change (every 01 of each month at time 00:00:00). 2, 3 = year change (every january 1 at time 00:00:00). 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? calevsel 15 14 13 12 11 10 9 8 ? ? ? ? ? ? timevsel 76543210 ??????updcalupdtim
300 AT91RM9200 1768b?atarm?08/03 rtc mode register name: rtc_mr access type: read/write hrmod: 12-/24-hour mode 0 = 24-hour mode is selected. 1 = 12-hour mode is selected. all non-significant bits read zero. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????hrmod
301 AT91RM9200 1768b?atarm?08/03 rtc time register name: rtc_timr access type: read/write sec: current second the range that can be set is 0 - 59 (bcd). the lowest four bits encode the units. the higher bits encode the tens. min: current minute the range that can be set is 0 - 59 (bcd). the lowest four bits encode the units. the higher bits encode the tens. hour: current hour the range that can be set is 1 - 12 (bcd) in 12-hour mode or 0 - 23 (bcd) in 24-hour mode. ampm: ante meridiem post meridiem indicator this bit is the am/pm indicator in 12-hour mode. 0 = am. 1 = pm. all non-significant bits read zero. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?ampm hour 15 14 13 12 11 10 9 8 ?min 76543210 ? sec
302 AT91RM9200 1768b?atarm?08/03 rtc calendar register name: rtc_calr access type: read/write cent: current century the range that can be set is 19 - 20 (bcd). the lowest four bits encode the units. the higher bits encode the tens. year: current year the range that can be set is 00 - 99 (bcd). the lowest four bits encode the units. the higher bits encode the tens. month: current month the range that can be set is 01 - 12 (bcd). the lowest four bits encode the units. the higher bits encode the tens. day: current day the range that can be set is 1 - 7 (bcd). the coding of the number (which number represents which day) is user-defined as it has no effect on the date counter. date: current date the range that can be set is 01 - 31 (bcd). the lowest four bits encode the units. the higher bits encode the tens. all non-significant bits read zero. 31 30 29 28 27 26 25 24 ?? date 23 22 21 20 19 18 17 16 day month 15 14 13 12 11 10 9 8 year 76543210 ?cent
303 AT91RM9200 1768b?atarm?08/03 rtc time alarm register name: rtc_timalr access type: read/write sec: second alarm this field is the alarm field corresponding to the bcd-coded second counter. secen: second alarm enable 0 = the second-matching alarm is disabled. 1 = the second-matching alarm is enabled. min: minute alarm this field is the alarm field corresponding to the bcd-coded minute counter. minen: minute alarm enable 0 = the minute-matching alarm is disabled. 1 = the minute-matching alarm is enabled. hour: hour alarm this field is the alarm field corresponding to the bcd-coded hour counter. ampm: am/pm indicator this field is the alarm field corresponding to the bcd-coded hour counter. houren: hour alarm enable 0 = the hour-matching alarm is disabled. 1 = the hour-matching alarm is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 houren ampm hour 15 14 13 12 11 10 9 8 minen min 76543210 secen sec
304 AT91RM9200 1768b?atarm?08/03 rtc calendar alarm register name: rtc_calalr access type: read/write month: month alarm this field is the alarm field corresponding to the bcd-coded month counter. mthen: month alarm enable 0 = the month-matching alarm is disabled. 1 = the month-matching alarm is enabled. date: date alarm this field is the alarm field corresponding to the bcd-coded date counter. dateen: date alarm enable 0 = the date-matching alarm is disabled. 1 = the date-matching alarm is enabled. 31 30 29 28 27 26 25 24 dateen ? date 23 22 21 20 19 18 17 16 mthen ? ? month 15 14 13 12 11 10 9 8 ???????? 76543210 ????????
305 AT91RM9200 1768b?atarm?08/03 rtc status register name: rtc_sr access type: read-only ackupd: acknowledge for update 0 = time and calendar registers cannot be updated. 1 = time and calendar registers can be updated. alarm: alarm flag 0 = no alarm matching condition occurred. 1 = an alarm matching condition has occurred. sec: second event 0 = no second event has occurred since the last clear. 1 = at least one second event has occurred since the last clear. timev: time event 0 = no time event has occurred since the last clear. 1 = at least one time event has occurred since the last clear. the time event is selected in the timevsel field in rtc_ctrl (control register) and can be any one of the following events: minute change, hour change, noon, midnight (day change). calev: calendar event 0 = no calendar event has occurred since the last clear. 1 = at least one calendar event has occurred since the last clear. the calendar event is selected in the calevsel field in rtc_cr and can be any one of the following events: week change, month change and year change. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ? calev timev sec alarm ackupd
306 AT91RM9200 1768b?atarm?08/03 rtc status clear command register name: rtc_sccr access type: write-only status flag clear 0 = no effect. 1 = clears corresponding status flag in the status register (rtc_sr). 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ? calclr timclr secclr alrclr ackclr
307 AT91RM9200 1768b?atarm?08/03 rtc interrupt enable register name: rtc_ier access type: write-only acken: acknowledge update interrupt enable 0 = no effect. 1 = the acknowledge for update interrupt is enabled. alren: alarm interrupt enable 0 = no effect. 1 = the alarm interrupt is enabled. secen: second event interrupt enable 0 = no effect. 1 = the second periodic interrupt is enabled. timen: time event interrupt enable 0 = no effect. 1 = the selected time event interrupt is enabled. calen: calendar event interrupt enable 0 = no effect. 1 = the selected calendar event interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ? calen timen secen alren acken
308 AT91RM9200 1768b?atarm?08/03 rtc interrupt disable register name: rtc_idr access type: write-only ackdis: acknowledge update interrupt disable 0 = no effect. 1 = the acknowledge for update interrupt is disabled. alrdis: alarm interrupt disable 0 = no effect. 1 = the alarm interrupt is disabled. secdis: second event interrupt disable 0 = no effect. 1 = the second periodic interrupt is disabled. timdis: time event interrupt disable 0 = no effect. 1 = the selected time event interrupt is disabled. caldis: calendar event interrupt disable 0 = no effect. 1 = the selected calendar event interrupt is disabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ? caldis timdis secdis alrdis ackdis
309 AT91RM9200 1768b?atarm?08/03 rtc interrupt mask register name: rtc_imr access type: read-only ack: acknowledge update interrupt mask 0 = the acknowledge for update interrupt is disabled. 1 = the acknowledge for update interrupt is enabled. alr: alarm interrupt mask 0 = the alarm interrupt is disabled. 1 = the alarm interrupt is enabled. sec: second event interrupt mask 0 = the second periodic interrupt is disabled. 1 = the second periodic interrupt is enabled. tim: time event interrupt mask 0 = the selected time event interrupt is disabled. 1 = the selected time event interrupt is enabled. cal: calendar event interrupt mask 0 = the selected calendar event interrupt is disabled. 1 = the selected calendar event interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ? cal tim sec alr ack
310 AT91RM9200 1768b?atarm?08/03 rtc valid entry register name: rtc_ver access type: read-only nvtim: non valid time 0 = no invalid data has been detected in rtc_timr (time register). 1 = rtc_timr has contained invalid data since it was last programmed. nvcal: non valid calendar 0 = no invalid data has been detected in rtc_calr (calendar register). 1 = rtc_calr has contained invalid data since it was last programmed. nvtimalr: non valid time alarm 0 = no invalid data has been detected in rtc_timalr (time alarm register). 1 = rtc_timalr has contained invalid data since it was last programmed. nvcalalr: non valid calendar alarm 0 = no invalid data has been detected in rtc_calalr (calendar alarm register). 1 = rtc_calalr has contained invalid data since it was last programmed. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ? ? nvcalar nvtimalr nvcal nvtim
311 AT91RM9200 1768b?atarm?08/03 debug unit (dbgu) overview the debug unit provides a single entry point from the processor for access to all the debug capabilities of atmel?s arm-based systems. the debug unit features a two-pin uart t hat can be used for several debug and trace pur- poses and offers an ideal medium for in-situ programming solutions and debug monitor communications. moreover, the association with two peripheral data controller channels per- mits packet handling for these tasks with processor time reduced to a minimum. the debug unit also makes the debug communication channel (dcc) signals provided by the in-circuit emulator of the arm processor visible to the software. these signals indicate the status of the dcc read and write registers and generate an interrupt to the arm processor, making possible the handling of the dcc under interrupt control. chip identifier registers permit recognition of the device and its revision. these registers inform as to the sizes and types of the on-chip memories, as well as the set of embedded peripherals. finally, the debug unit features a force ntrst capability that enables the software to decide whether to prevent access to the system via the in-circuit emulator. this permits protection of the code, stored in rom. important features of the debug unit are: system peripheral to facilitate debug of atmel?s arm-based systems composed of four functions ?two-pin uart ? debug communication channel (dcc) support ? chip id registers ? ice access prevention two-pin uart ? implemented features are 100% compatible with the standard atmel usart ? independent receiver and transmitter with a common programmable baud rate generator ? even, odd, mark or space parity generation ? parity, framing and overrun error detection ? automatic echo, local loopback and remote loopback channel modes ? interrupt generation ? support for two pdc channels with connection to receiver and transmitter debug communication channel support ? offers visibility of commrx and co mmtx signals from the arm processor ? interrupt generation chip id registers ? identification of the device revision, sizes of the embedded memories, set of peripherals ice access prevention ? enables software to prevent system access through the arm processor?s ice ? prevention is made by asserting the ntrst line of the arm processor?s ice
312 AT91RM9200 1768b?atarm?08/03 block diagram figure 135. debug unit functional block diagram note: 1. if ntrst pad is not bonded out, it is connected to nrst. figure 136. debug unit application example table 64. debug unit pin description pin name description type drxd debug receive data input dtxd debug transmit data output debug unit apb peripheral data controller baud rate generator dcc handler ice access handler transmit receive chip id interrupt control peripheral bridge parallel input/ output dtxd drxd power management controller arm processor advanced interrupt controller force ntrst ntrst (1) other system interrupt sources source 1 dbgu interupt commrx commtx mck ntrst debug unit rs232 drivers programming tool trace console debug console boot program debug monitor trace manager
313 AT91RM9200 1768b?atarm?08/03 product dependencies i/o lines depending on product integration, the debug unit pins may be multiplexed with pio lines. in this case, the programmer must first configure the corresponding pio controller to enable i/o lines operations of the debug unit. power management depending on product integration, the debug unit clock may be controllable through the power management controller. in this case, the programmer must first configure the pmc to enable the debug unit clock. usually, the peripheral identifier used for this purpose is 1. interrupt source depending on product integration, the debug unit interrupt line is connected to one of the interrupt sources of the advanced interrupt controller. interrupt handling requires program- ming of the aic before configuring the debug unit. usually, the debug unit interrupt line connects to the interrupt source 1 of the aic, which may be shared with the real-time clock, the system timer interrupt lines and other system peripheral interrupts, as shown in figure 135. this sharing requires the programmer to determine the source of the interrupt when the source 1 is triggered. uart operations the debug unit operates as a uart, (asynchronous mode only) and supports only 8-bit char- acter handling (with parity). it has no clock pin. the debug unit's uart is made up of a receiver and a transmitter that operate independently, and a common baud rate generator. receiver timeout and transmitter time guard are not implemented. however, all the implemented features are compatible with those of a standard usart. baud rate generator the baud rate generator provides the bit period clock named baud rate clock to both the receiver and the transmitter. the baud rate clock is the master clock divi ded by 16 times the value (cd) written in dbgu_brgr (baud rate generator register). if dbgu_brgr is set to 0, the baud rate clock is disabled and the debug unit's uart remains inactive. the maximum allowable baud rate is master clock divided by 16. the minimum allowable baud rate is master clock divided by (16 x 65536). baud rate mck 16 cd --------------------- =
314 AT91RM9200 1768b?atarm?08/03 figure 137. baud rate generator receiver receiver reset, enable and disable after device reset, the debug unit receiv er is disabled and must be enabled before being used. the receiver can be enabled by writing the control register dbgu_cr with the bit rxen at 1. at this command, the receiver starts looking for a start bit. the programmer can disable the receiver by writing dbgu_cr with the bit rxdis at 1. if the receiver is waiting for a start bit, it is immediately stopped. however, if the receiver has already detected a start bit and is receiving the data, it waits for the stop bit before actually stopping its operation. the programmer can also put the receiver in its reset state by writing dbgu_cr with the bit rstrx at 1. in doing so, the receiver immediately stops its current operations and is disabled, whatever its current state. if rstrx is applied when data is being processed, this data is lost. start detection and data sampling the debug unit only supports asynchronous operations, and this affects only its receiver. the debug unit receiver detects the start of a received character by sampling the drxd signal until it detects a valid start bit. a low level (space) on drxd is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud rate. hence, a space that is longer than 7/16 of the bit period is detected as a valid start bit. a space which is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit. when a valid start bit has been detected, the receiver samples the drxd at the theoretical midpoint of each bit. it is assumed that each bit lasts 16 cycles of the sampling clock (1-bit period) so the bit sampling point is eight cycles (0.5-bit period) after the start of the bit. the first sampling point is therefore 24 cycles (1.5-bit periods) after the falling edge of the start bit was detected. each subsequent bit is sampled 16 cycles (1-bit period) after the previous one. figure 138. start bit detection mck 16-bit counter 0 baud rate clock cd cd out divide by 16 0 1 >1 receiver sampling clock sampling clock drxd true start detection d0 baud rate clock
315 AT91RM9200 1768b?atarm?08/03 figure 139. character reception receiver ready when a complete character is received, it is transferred to the dbgu_rhr and the rxrdy status bit in dbgu_sr (status register) is set. the bit rxrdy is automatically cleared when the receive holding register dbgu_rhr is read. figure 140. receiver ready receiver overrun if dbgu_rhr has not been read by the software (or the peripheral data controller) since the last transfer, the rxrdy bit is still set and a new character is received, the ovre status bit in dbgu_sr is set. ovre is cleared when the softw are writes the control register dbgu_cr with the bit rststa (reset status) at 1. figure 141. receiver overrun parity error each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the field par in dbgu_mr. it then compares the result with the received parity bit. if different, the parity error bit pare in dbgu_sr is set at the same time the rxrdy is set. the parity bit is cleared when the control register dbgu_cr is written with the bit rststa (reset status) at 1. if a new char acter is received before the reset status com- mand is written, the pare bit remains at 1. figure 142. parity error d0 d1 d2 d3 d4 d5 d6 d7 drxd true start detection sampling parity bit stop bit example: 8-bit, parity enabled 1 stop 1 bit period 0.5 bit period d0 d1 d2 d3 d4 d5 d6 d7 p s s d0 d1 d2 d3 d4 d5 d6 d7 p drxd read dbgu_rhr rxrdy d0 d1 d2 d3 d4 d5 d6 d7 p s s d0 d1 d2 d3 d4 d5 d6 d7 p drxd rststa rxrdy ovre stop stop stop d0 d1 d2 d3 d4 d5 d6 d7 p s drxd rststa rxrdy pare wrong parity bit
316 AT91RM9200 1768b?atarm?08/03 receiver framing error when a start bit is detected, it generates a character reception when all the data bits have been sampled. the stop bit is also sampled and when it is detected at 0, the frame (framing error) bit in dbgu_sr is set at the same time the rxrdy bit is set. the bit frame remains high until the control register dbgu_cr is written with the bit rststa at 1. figure 143. receiver framing error transmitter transmitter reset, enable and disable after device reset, the debug unit transmitter is disabled and it must be enabled before being used. the transmitter is enabled by writing the control register dbgu_cr with the bit txen at 1. from this command, the transmitter waits for a character to be written in the transmit hold- ing register dbgu_thr before actually starting the transmission. the programmer can disable the transmitter by writing dbgu_cr with the bit txdis at 1. if the transmitter is not operating, it is immediately stopped. however, if a character is being pro- cessed into the shift register and/or a character has been written in the transmit holding register, the characters are completed before the transmitter is actually stopped. the programmer can also put the transmitter in its reset state by writing the dbgu_cr with the bit rsttx at 1. this immediately stops the transmitter, whether or not it is processing characters. transmit format the debug unit transmitter drives the pin dtxd at the baud rate clock speed. the line is driven depending on the format defined in the mode register and the data stored in the shift register. one start bit at level 0, then the 8 data bits, from the lowest to the highest bit, one optional parity bit and one stop bit at 1 are consecutively shifted out as shown on the following figure. the field pare in the mode register dbgu_mr defines whether or not a parity bit is shifted out. when a parity bit is enabled, it can be selected between an odd parity, an even parity, or a fixed space or mark bit. figure 144. character transmission transmitter control when the transmitter is enabled, the bit txrdy (transmitter ready) is set in the status regis- ter dbgu_sr. the transmission starts when the programmer writes in the transmit holding register dbgu_thr, and after the written char acter is transferred from dbgu_thr to the shift register. the bit txrdy remains high until a second character is written in dbgu_thr. d0 d1 d2 d3 d4 d5 d6 d7 p s drxd rststa rxrdy frame stop bit detected at 0 stop d0 d1 d2 d3 d4 d5 d6 d7 dtxd start bit parity bit stop bit example: parity enabled baud rate clock
317 AT91RM9200 1768b?atarm?08/03 as soon as the first character is completed, the last character written in dbgu_thr is trans- ferred into the shift register and txrdy rises again, showing that the holding register is empty. when both the shift register and the dbgu_thr are empty, i.e., all the characters written in dbgu_thr have been processed, the bit txempty rises after the last stop bit has been completed. figure 145. transmitter control peripheral data controller both the receiver and the transmitter of the debug unit's uart are generally connected to a peripheral data controller (pdc) channel. the peripheral data controller channels are programmed via registers that are mapped within the debug unit user interface from the offset 0x100. the status bits are reported in the debug unit status register dbgu_sr and can generate an interrupt. the rxrdy bit triggers the pdc channel data transfer of the receiver. this results in a read of the data in dbgu_rhr. the txrdy bit triggers the pdc channel data transfer of the trans- mitter. this results in a write of a data in dbgu_thr. test modes the debug unit supports three tests modes. these modes of operation are programmed by using the field chmode (channel mode) in the mode register dbgu_mr. the automatic echo mode allows bit-by-bit retransmission. when a bit is received on the drxd line, it is sent to the dtxd line. the transmitter operates normally, but has no effect on the dtxd line. the local loopback mode allows the transmitted characters to be received. dtxd and drxd pins are not used and the output of the transmitte r is internally connected to the input of the receiver. the drxd pin level has no effect and the dtxd line is held high, as in idle state. the remote loopback mode directly connects the drxd pin to the dtxd line. the transmit- ter and the receiver are disabled and have no effect. this mode allows a bit-by-bit retransmission. dbgu_thr shift register dtxd txrdy txempty data 0 data 1 data 0 data 0 data 1 data 1 s s p p write data 0 in dbgu_thr write data 1 in dbgu_thr stop stop
318 AT91RM9200 1768b?atarm?08/03 figure 146. test modes receiver transmitter disabled rxd txd receiver transmitter disabled rxd txd v dd disabled receiver transmitter disabled rxd txd disabled automatic echo local loopback remote loopback v dd
319 AT91RM9200 1768b?atarm?08/03 debug communication channel support the debug unit handles the signals commrx and commtx that come from the debug communication channel of the arm processor and are driven by the in-circuit emulator. the debug communication channel contains two registers that are accessible through the ice breaker on the jtag side and through the coprocessor 0 on the arm processor side. as a reminder, the following instructions are used to read and write the debug communication channel: mrc p14, 0, rd, c1, c0, 0 returns the debug communication data read register into rd mcr p14, 0, rd, c1, c0, 0 writes the value in rd to the debug communication data write register. the bits commrx and commtx, which indicate , respectively, that the read register has been written by the debugger but not yet read by the processor, and that the write register has been written by the processor and not yet read by the debugger, are wired on the two highest bits of the status register dbgu_sr. these bits can generate an interrupt. this feature per- mits handling under interrupt a debug link between a debug monitor running on the target system and a debugger. chip identifier the debug unit features two chip identifier registers, dbgu_cidr (chip id register) and dbgu_exid (extension id). both registers contain a hard-wired value that is read-only. the first register contains the following fields: ext - shows the use of the extension identifier register nvptyp and nvpsiz - identifies the type of embedded non-volatile memory and its size arch - identifies the set of embedded peripheral sramsiz - indicates the size of the embedded sram eproc - indicates the embedded arm processor version - gives the revision of the silicon the second register is device-dependent and reads 0 if the bit ext is 0. ice access prevention the debug unit allows blockage of access to the system through the arm processor's ice interface. this feature is implemented via the register force ntrst (dbgu_fnr), that allows assertion of the ntrst signal of the ice interface. writing the bit fntrst (force ntrst) to 1 in this register prevents any activity on the tap controller. on standard devices, the bit fntrst resets to 0 and thus does not prevent ice access. this feature is especially useful on custom rom devices for customers who do not want their on-chip code to be visible.
320 AT91RM9200 1768b?atarm?08/03 debug unit user interface table 65. debug unit memory map offset register name access reset value 0x0000 control register dbgu_cr write-only ? 0x0004 mode register dbgu_mr read/write 0x0 0x0008 interrupt enable register dbgu_ier write-only ? 0x000c interrupt disable register dbgu_idr write-only ? 0x0010 interrupt mask register dbgu_imr read-only 0x0 0x0014 status register dbgu_sr read-only ? 0x0018 receive holding register dbgu_rhr read-only 0x0 0x001c transmit holding register dbgu_thr write-only ? 0x0020 baud rate generator register dbgu_brgr read/write 0x0 0x0024 - 0x003c reserved ? ? ? 0x0040 chip id register dbgu_cidr read-only ? 0x0044 chip id extension register dbgu_exid read-only ? 0x0048 force ntrst register dbgu_fnr read/write 0x0 0x004c - 0x00fc reserved ? ? ? 0x0100 - 0x0124 pdc area ? ? ?
321 AT91RM9200 1768b?atarm?08/03 debug unit control register name: dbgu_cr access type: write-only rstrx: reset receiver 0 = no effect. 1 = the receiver logic is reset and disabled. if a character is being received, the reception is aborted. rsttx: reset transmitter 0 = no effect. 1 = the transmitter logic is reset and disabled. if a character is being transmitted, the transmission is aborted. rxen: receiver enable 0 = no effect. 1 = the receiver is enabled if rxdis is 0. rxdis: receiver disable 0 = no effect. 1 = the receiver is disabled. if a character is being processed and rstrx is not set, the character is completed before the receiver is stopped. txen: transmitter enable 0 = no effect. 1 = the transmitter is enabled if txdis is 0. txdis: transmitter disable 0 = no effect. 1 = the transmitter is disabled. if a character is being processed and a character has been written the dbgu_thr and rsttx is not set, both characters are completed before the transmitter is stopped. rststa: reset status bits 0 = no effect. 1 = resets the status bits pare, frame and ovre in the dbgu_sr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????? rststa 76543210 txdis txen rxdis rxen rsttx rstrx ??
322 AT91RM9200 1768b?atarm?08/03 debug unit mode register name: dbgu_mr access type: read/write par: parity type chmode: channel mode 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 chmode ?? pa r ? 76543210 ???????? pa r par it y ty pe 000even parity 0 0 1 odd parity 0 1 0 space: parity forced to 0 0 1 1 mark: parity forced to 1 1xxno parity chmode mode description 0 0 normal mode 01automatic echo 1 0 local loopback 1 1 remote loopback
323 AT91RM9200 1768b?atarm?08/03 debug unit interrupt enable register name: dbgu_ier access type: write-only rxrdy: enable rxrdy interrupt txrdy: enable txrdy interrupt endrx: enable end of receive transfer interrupt endtx: enable end of transmit interrupt ovre: enable overrun error interrupt frame: enable framing error interrupt pare: enable parity error interrupt txempty: enable txempty interrupt txbufe: enable buffer empty interrupt rxbuff: enable buffer full interrupt commtx: enable commtx (from arm) interrupt commrx: enable commrx (from arm) interrupt 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 commrx commtx ?????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??? rxbuff txbufe ? txempty ? 76543210 pare frame ovre endtx endrx ? txrdy rxrdy
324 AT91RM9200 1768b?atarm?08/03 debug unit interrupt disable register name: dbgu_idr access type: write-only rxrdy: disable rxrdy interrupt txrdy: disable txrdy interrupt endrx: disable end of receive transfer interrupt endtx: disable end of transmit interrupt ovre: disable overrun error interrupt frame: disable framing error interrupt pare: disable parity error interrupt txempty: disable txempty interrupt txbufe: disable buffer empty interrupt rxbuff: disable buffer full interrupt commtx: disable commtx (from arm) interrupt commrx: disable commrx (from arm) interrupt 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 commrx commtx ?????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??? rxbuff txbufe ? txempty ? 76543210 pare frame ovre endtx endrx ? txrdy rxrdy
325 AT91RM9200 1768b?atarm?08/03 debug unit interrupt mask register name: dbgu_imr access type: read-only rxrdy: mask rxrdy interrupt txrdy: disable txrdy interrupt endrx: mask end of receive transfer interrupt endtx: mask end of transmit interrupt ovre: mask overrun error interrupt frame: mask framing error interrupt pare: mask parity error interrupt txempty: mask txempty interrupt txbufe: mask txbufe interrupt rxbuff: mask rxbuff interrupt commtx: mask commtx interrupt commrx: mask commrx interrupt 0 = the corresponding interrupt is disabled. 1 = the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 commrx commtx ?????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??? rxbuff txbufe ? txempty ? 76543210 pare frame ovre endtx endrx ? txrdy rxrdy
326 AT91RM9200 1768b?atarm?08/03 debug unit status register name: dbgu_sr access type: read-only rxrdy: receiver ready 0 = no character has been received since the last read of the dbgu_rhr or the receiver is disabled. 1 = at least one complete character has been received, transferred to dbgu_rhr and not yet read. txrdy: transmitter ready 0 = a character has been written to dbgu_thr and not yet transferred to the shift register, or the transmitter is disabled. 1 = there is no character written to dbgu_thr not yet transferred to the shift register. endrx: end of receiver transfer 0 = the end of transfer signal from the receiver peripheral data controller channel is inactive. 1 = the end of transfer signal from the receiver peripheral data controller channel is active. endtx: end of transmitter transfer 0 = the end of transfer signal from the transmitter peripheral data controller channel is inactive. 1 = the end of transfer signal from the transmitter peripheral data controller channel is active. ovre: overrun error 0 = no overrun error has occurred since the last rststa. 1 = at least one overrun error has occurred since the last rststa. frame: framing error 0 = no framing error has occurred since the last rststa. 1 = at least one framing error has occurred since the last rststa. pare: parity error 0 = no parity error has occurred since the last rststa. 1 = at least one parity error has occurred since the last rststa. txempty: transmitter empty 0 = there are characters in dbgu_thr, or characters being processed by the transmitter, or the transmitter is disabled. 1 = there are no characters in dbgu_thr and there are no characters being processed by the transmitter. txbufe: transmission buffer empty 0 = the buffer empty signal from the transmitter pdc channel is inactive. 1 = the buffer empty signal from the transmitter pdc channel is active. rxbuff: receive buffer full 0 = the buffer full signal from the receiver pdc channel is inactive. 1 = the buffer full signal from the receiver pdc channel is active. 31 30 29 28 27 26 25 24 commrx commtx ?????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??? rxbuff txbufe ? txempty ? 76543210 pare frame ovre endtx endrx ? txrdy rxrdy
327 AT91RM9200 1768b?atarm?08/03 commtx: debug communication channel write status 0 = commtx from the arm processor is inactive. 1 = commtx from the arm processor is active. commrx: debug communication channel read status 0 = commrx from the arm processor is inactive. 1 = commrx from the arm processor is active.
328 AT91RM9200 1768b?atarm?08/03 debug unit receiver holding register name: dbgu_rhr access type: read-only rxchr: received character last received character if rxrdy is set. debug unit transmit holding register name: dbgu_thr access type: write-only txchr: character to be transmitted next character to be transmitted after the current character if txrdy is not set. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 rxchr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 txchr
329 AT91RM9200 1768b?atarm?08/03 debug unit baud rate generator register name: dbgu_brgr access type: read/write cd: clock divisor 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 cd 76543210 cd cd baud rate clock 0 disabled 1mck 2 to 65535 mck / (cd x 16)
330 AT91RM9200 1768b?atarm?08/03 debug unit chip id register name: dbgu_cidr access type: read-only version: version of the device eproc: embedded processor nvpsiz: nonvolatile program memory size 31 30 29 28 27 26 25 24 ext nvptyp arch 23 22 21 20 19 18 17 16 arch sramsiz 15 14 13 12 11 10 9 8 0000 nvpsiz 76543210 eproc version eproc processor 0 0 1 arm946es 0 1 0 arm7tdmi 1 0 0 arm920t nvpsiz size 0000none 00018k bytes 001016k bytes 001132k bytes 0100reserved 010164k bytes 0110reserved 0111128k bytes 1000reserved 1001256k bytes 1010reserved 1011reserved 1100reserved 1101reserved 1110reserved 1111reserved
331 AT91RM9200 1768b?atarm?08/03 sramsiz: internal sram size arch: architecture identifier nvptyp: nonvolatile program memory type ext: extension flag 0 = chip id has a single register definition without extension 1 = an extended chip id exists. sramsiz size 0000reserved 00011k bytes 00102k bytes 0011reserved 0100reserved 01014k bytes 0110reserved 0111reserved 10008k bytes 100116k bytes 101032k bytes 101164k bytes 1100128k bytes 1101256k bytes 111096k bytes 1111512k bytes arch architecture hex dec 0x40 0100 0000 at91x40 series 0x63 0110 0011 at91x63 series 0x55 0101 0101 at91x55 series 0x42 0100 0010 at91x42 series 0x92 1001 0010 at91x92 series 0x34 0011 0100 at91x34 series nvptyp memory 000rom 0 0 1 romless or on-chip flash 1 0 0 sram emulating rom
332 AT91RM9200 1768b?atarm?08/03 debug unit chip id extension register name: dbgu_exid access type: read-only exid: chip id extension reads 0 if the bit ext in dbgu_cidr is 0. debug unit force ntrst register name: dbgu_fnr access type: read/write fntrst: force ntrst 0 = ntrst of the arm processor?s tap controller is driven by the ntrst pin. 1 = ntrst of the arm processor?s tap controller is held low. 31 30 29 28 27 26 25 24 exid 23 22 21 20 19 18 17 16 exid 15 14 13 12 11 10 9 8 exid 76543210 exid 31 30 29 28 27 26 25 24 ??????? ? 23 22 21 20 19 18 17 16 ??????? ? 15 14 13 12 11 10 9 8 ??????? ? 7654321 0 ??????? fntrst
333 AT91RM9200 1768b?atarm?08/03 parallel input/output controller (pio) overview the parallel input/output controller (pio) manages up to 32 fully programmable input/output lines. each i/o line may be dedicated as a general-purpose i/o or be assigned to a function of an embedded peripheral. this assures effective optimization of the pins of a product. each i/o line is associated with a bit number in all of the 32-bit registers of the 32-bit wide user interface. each i/o line of the pio controller features: an input change interrupt enabling level change on any i/o line. a glitch filter providing rejection of pulses lower than one-half of clock cycle. multi-drive capability similar to an open drain i/o line. control of the the pull-up of the i/o line. input visibility and output control. the pio controller also features a synchronous output providing up to 32 bits of data output in a single write operation. important features of the pio also include: up to 32 programmable i/o lines fully programmable through set/clear registers multiplexing of two peripheral functions per i/o line for each i/o line (whether assigned to a peripheral or used as general purpose i/o) ? input change interrupt ? glitch filter ? multi-drive option enables driving in open drain ? programmable pull up on each i/o line ? pin data status register, supplies visibility of the level on the pin at any time synchronous output, provides set and clear of several i/o lines in a single write
334 AT91RM9200 1768b?atarm?08/03 block diagram figure 147. block diagram figure 148. application block diagram up to 32 pins pmc embedded peripheral embedded peripheral embedded peripheral up to 32 peripheral ios up to 32 peripheral ios pio clock apb pin pin pin aic pio interrupt pio controller embedded peripheral embedded peripheral embedded peripheral on-chip peripherals pio controller on-chip peripheral drivers control & command driver keyboard driver keyboard driver general purpose i/os external devices
335 AT91RM9200 1768b?atarm?08/03 product dependencies pin multiplexing each pin is configurable, according to product definition as either a general-purpose i/o line only, or as an i/o line multiplexed with one or two peripheral i/os. as the multiplexing is hard- ware-defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the pio controllers required by their application. when an i/o line is general-purpose only, i.e. not multiplexed with any peripheral i/o, programming of the pio controller regarding the assignment to a peripheral has no effect and only the pio controller can control how the pin is driven by the product. external interrupt lines the interrupt signals fiq and irq0 to irqn are most generally multiplexed through the pio controllers. however, it is not necessary to assign the i/o line to the interrupt function as the pio controller has no effect on inputs and the interrupt lines (fiq or irqs) are used only as inputs. power management the power management controller controls the pio controller clock in order to save power. writing any of the registers of the user interface does not require the pio controller clock to be enabled. this means that the configuration of the i/o lines does not require the pio controller clock to be enabled. however, when the clock is disabled, not all of the features of the pio controller are available. note that the input change interrupt and the read of the pin level require the clock to be validated. after a hardware reset, the pio clock is disabled by default (see power management controller). the user must configure the power management controller before any access to the input line information. interrupt generation for interrupt handling, the pio controllers are considered as user peripherals. this means that the pio controller interrupt lines are connected among the interrupt sources 2 to 31. refer to the pio controller peripheral identifier in the product description to identify the inter- rupt sources dedicated to the pio controllers. the pio controller interrupt can be generated only if the pio controller clock is enabled.
336 AT91RM9200 1768b?atarm?08/03 functional description the pio controller features up to 32 fully-programmable i/o lines. most of the control logic associated to each i/o is represented in figure 149. figure 149. i/o line control logic pad 1 0 glitch filter pio_pudr pio_pusr pio_puer 1 0 pio_mddr pio_mdsr pio_mder 1 0 pio_codr pio_odsr pio_sodr 1 0 pio_pdr pio_psr pio_per 1 0 1 0 pio_bsr pio_absr pio_asr peripheral b output enable peripheral a output enable peripheral b output peripheral a output pio_odr pio_osr pio_oer peripheral b input peripheral a input 1 0 pio_ifdr pio_ifsr pio_ifer edge detector pio_pdsr pio_isr 1 0 pio_idr pio_imr pio_ier pio interrupt
337 AT91RM9200 1768b?atarm?08/03 pull-up resistor control each i/o line is designed with an embedded pull-up resistor. the value of this resistor is about 100 k ? (see the product electrical characteristics for more details about this value). the pull- up resistor can be enabled or disabled by writ ing respectively pio_puer (pull-up enable register) and pio_pudr (pull-up disable resistor). writing in these registers results in set- ting or clearing the corresponding bit in pio_pusr (pull-up status register). reading a 1 in pio_pusr means the pull-up is disabled and reading a 0 means the pull-up is enabled. control of the pull-up resistor is possible regardless of the configuration of the i/o line. after reset, all of the pull-ups are enabled, i.e. pio_pusr resets at the value 0x0. i/o line or peripheral function selection when a pin is multiplexed with one or two peripheral functions, the selection is controlled with the registers pio_per (pio enable register) and pio_pdr (pio disable register). the reg- ister pio_psr (pio status register) is the result of the set and clear registers and indicates whether the pin is controlled by the corresponding peripheral or by the pio controller. a value of 0 indicates that the pin is controlled by the corresponding on-chip peripheral selected in the pio_absr (ab select status register). a value of 1 indicates the pin is controlled by the pio controller. if a pin is used as a general purpose i/o line (not multiplexed with an on-chip peripheral), pio_per and pio_pdr have no effect and pio_psr returns 1 for the corresponding bit. after reset, most generally, the i/o lines are controlled by the pio controller, i.e. pio_psr resets at 1. however, in some events, it is important that pio lines are controlled by the peripheral (as in the case of memory chip select lines that must be driven inactive after reset or for address lines that must be driven low for booting out of an external memory). thus, the reset value of pio_psr is defined at the product level, depending on the multiplexing of the device. peripheral a or b selection the pio controller provides multiplexing of up to two peripheral functions on a single pin. the selection is performed by writing pio_asr (a select register) and pio_bsr (select b regis- ter). pio_absr (ab select status register) indicates which peripheral line is currently selected. for each pin, the corresponding bit at level 0 means peripheral a is selected whereas the corresponding bit at level 1 indicates that peripheral b is selected. note that multiplexing of peripheral lines a and b only affects the output line. the peripheral input lines are always connected to the pin input. after reset, pio_absr is 0, thus indicating that all the pio lines are configured on peripheral a. however, peripheral a generally does not drive the pin as the pio controller resets in i/o line mode. writing in pio_asr and pio_bsr manages pio_absr regardless of the configuration of the pin. however, assignment of a pin to a peripheral function requires a write in the correspond- ing peripheral selection register (pio_asr or pio_bsr) in addition to a write in pio_pdr. output control when the i/0 line is assigned to a peripheral function, i.e. the corresponding bit in pio_psr is at 0, the drive of the i/o line is controlled by the peripheral. peripheral a or b, depending on the value in pio_absr, determines whether the pin is driven or not. when the i/o line is controlled by the pio cont roller, the pin can be configured to be driven. this is done by writing pio_oer (output enable register) and pio_pdr (output disable register). the results of these write operations are detected in pio_osr (output status reg- ister). when a bit in this register is at 0, the corresponding i/o line is used as an input only. when the bit is at 1, the corresponding i/o line is driven by the pio controller.
338 AT91RM9200 1768b?atarm?08/03 the level driven on an i/o line can be determined by writing in pio_sodr (set output data register) and pio_codr (clear output data register). these write operations respectively set and clear pio_odsr (output data status register), which represents the data driven on the i/o lines. writing in pio_oer and pio_odr manages pio_osr whether the pin is con- figured to be controlled by the pio controller or assigned to a peripheral function. this enables configuration of the i/o line prior to setting it to be managed by the pio controller. similarly, writing in pio_sodr and pio_codr effects pio_odsr. this is important as it defines the first level driven on the i/o line. synchronous data output using the write operations in pio_sodr and pio_codr can require that several instructions be executed in order to define values on several bits. both clearing and setting i/o lines on an 8-bit port, for example, cannot be done at the same time, and thus might limit the application covered by the pio controller. to avoid these inconveniences, the pio controller features a synchronous data output to clear and set a number of i/o lines in a single write. this is performed by authorizing the writ- ing of pio_odsr (output data status register) from the register set pio_ower (output write enable register), pio_owdr (output write disable register) and pio_owsr (output write status register). the value of pio_owsr register is user-definable by writing in pio_ower and pio_owdr. it is used by the pio controller as a pio_odsr write authori- zation mask. authorizing the write of pio_odsr on a user-definable number of bits is especially useful, as it guarantees that the unauthorized bit will not be changed when writing it and thus avoids the need of a time consuming read-modify-write operation. after reset, the synchronous data output is disabled on all the i/o lines as pio_owsr resets at 0x0. multi drive control (open drain) each i/o can be independently programmed in open drain by using the multi drive feature. this feature permits several drivers to be connected on the i/o line which is driven low only by each device. an external pull-up resistor (or enabling of the internal one) is generally required to guarantee a high level on the line. the multi drive feature is controlled by pio_mder (multi-driver enable register) and pio_mddr (multi-driver disable register). the multi drive can be selected whether the i/o line is controlled by the pio controller or assigned to a peripheral function. pio_mdsr (multi- driver status register) indicates the pins that are configured to support external drivers. after reset, the multi drive feature is disabled on all pins, i.e. pio_mdsr resets at value 0x0. output line timings figure 150 shows how the outputs are driven either by writing pio_sodr or pio_codr, or by directly writing pio_odsr. this last case is valid only if the corresponding bit in pio_owsr is set. figure 150 also shows when the feedback in pio_pdsr is available.
339 AT91RM9200 1768b?atarm?08/03 figure 150. output line timings inputs the level on each i/o line can be read through pio_pdsr (peripheral data status register). this register indicates the level of the i/o lines regardless of their configuration, whether uniquely as an input or driven by the pio controller or driven by a peripheral. reading the i/o line levels requires the clock of the pio controller to be enabled, otherwise pio_pdsr reads the levels present on the i/o line at the time the clock was disabled. input glitch filtering optional input glitch filters are independently programmable on each i/o line. when the glitch filter is enabled, a glitch with a duration of less than 1/2 master clock (mck) cycle is automat- ically rejected, while a pulse with a duration of 1 master clock cycle or more is accepted. for pulse durations between 1/2 master clock cycle and 1 master clock cycle the pulse may or may not be taken into account, depending on the precise timing of its occurrence. thus for a pulse to be visible it must exceed 1 master clock cycle, whereas for a glitch to be reliably fil- tered out, its duration must not exceed 1/2 master clock cycle. the filter introduces one master clock cycle latency if the pin level change occurs before a rising edge. however, this latency does not appear if the pin level change occurs before a falling edge. this is illustrated in figure 151. the glitch filters are controlled by the register set; pio_ifer (input filter enable register), pio_ifdr (input filter disable register) and pio_ifsr (input filter status register). writing pio_ifer and pio_ifdr respectively sets and cl ears bits in pio_ifsr. this last register enables the glitch filter on the i/o lines. when the glitch filter is enabled, it does not modify the behavior of the inputs on the peripher- als. it acts only on the value read in pio_pdsr and on the input change interrupt detection. the glitch filters require that the pio controller clock is enabled. figure 151. input glitch filter timing mck write pio_sodr write pio_odsr at 1 pio_odsr pio_pdsr apb access apb access write pio_codr write pio_odsr at 0 2 cycles 2 cycles mck pin level pio_pdsr if pio_ifsr = 0 pio_pdsr if pio_ifsr = 1 2 cycles 1 cycle 1 cycle 1 cycle 1 cycle 1 cycle
340 AT91RM9200 1768b?atarm?08/03 input change interrupt the pio controller can be programmed to generate an interrupt when it detects an input change on an i/o line. the input change interrupt is controlled by writing pio_ier (interrupt enable register) and pio_idr (interrupt disable register), which respectively enable and disable the input change interrupt by setting and clearing the corresponding bit in pio_imr (interrupt mask register). as input change det ection is possible only by comparing two suc- cessive samplings of the input of the i/o line, the pio controller clock must be enabled. the input change interrupt is available, regardless of the configuration of the i/o line, i.e. config- ured as an input only, controlled by the pio controller or assigned to a peripheral function. when an input change is detected on an i/o line, the corresponding bit in pio_isr (interrupt status register) is set. if the corresponding bit in pio_imr is set, the pio controller interrupt line is asserted. the interrupt signals of the thirty-two channels are ored-wired together to generate a single interrupt signal to the advanced interrupt controller. when the software reads pio_isr, all the interrupts are automatically cleared. this signifies that all the interrupts that are pending when pio_isr is read must be handled. figure 152. input change interrupt timings mck pio_pdsr read pio_isr apb access pio_isr apb access
341 AT91RM9200 1768b?atarm?08/03 i/o lines programming example the programing example shown in table 66 below is used to define the following configuration. 4-bit output port on i/o lines 0 to 3, (should be written in a single write operation), open- drain, with pull-up resistor four output signals on i/o lines 4 to 7 (to drive leds for example), driven high and low, no pull-up resistor four input signals on i/o lines 8 to 11 (to read push-button states for example), with pull- up resistors, glitch filters and input change interrupts four input signals on i/o line 12 to 15 to read an external device status (polled, thus no input change interrupt), no pull-up resistor, no glitch filter i/o lines 16 to 19 assigned to peripheral a functions with pull-up resistor i/o lines 20 to 23 assigned to peripheral b functions, no pull-up resistor i/o lines 24 to 27 assigned to peripheral a with input change interrupt and pull-up resistor table 66. programming example register value to be written pio_per 0x0000 ffff pio_pdr 0x0fff 0000 pio_oer 0x0000 00ff pio_odr 0x0fff ff00 pio_ifer 0x0000 0f00 pio_ifdr 0x0fff f0ff pio_sodr 0x0000 0000 pio_codr 0x0fff ffff pio_ier 0x0f00 0f00 pio_idr 0x00ff f0ff pio_mder 0x0000 000f pio_mddr 0x0fff fff0 pio_pudr 0x00f0 00f0 pio_puer 0x0f0f ff0f pio_asr 0x0f0f 0000 pio_bsr 0x00f0 0000 pio_ower 0x0000 000f pio_owdr 0x0fff fff0
342 AT91RM9200 1768b?atarm?08/03 parallel input/output controller (pio) user interface each i/o line controlled by the pio controller is associated with a bit in each of the pio controller user interface registers. each register is 32 bits wide. if a parallel i/o line is not defined, writing to the corresponding bits has no effect. undefine d bits read zero. if the i/o line is not multiplexed with any peripheral, the i/o line is controlled by the pio controller and pio_psr returns 1 systematically. table 67. pio register mapping offset register name access reset value 0x0000 pio enable register pio_per write-only ? 0x0004 pio disable register pio_pdr write-only ? 0x0008 pio status register (1) pio_psr read-only 0x0000 0000 0x000c reserved 0x0010 pio output enable register pio_oer write-only ? 0x0014 pio output disable register pio_odr write-only ? 0x0018 pio output status register pio_osr read-only 0x0000 0000 0x001c reserved 0x0020 pio glitch input filter enable register pio_ifer write-only ? 0x0024 pio glitch input filter disable register pio_ifdr write-only ? 0x0028 pio glitch input filter status register pio_ifsr read-only 0x0000 0000 0x002c reserved 0x0030 pio set output data register pio_sodr write-only ? 0x0034 pio clear output data register pio_codr write-only ? 0x0038 pio output data status register (2) pio_odsr read-only 0x0000 0000 0x003c pio pin data status register (3) pio_pdsr read-only 0x0040 pio interrupt enable register pio_ier write-only ? 0x0044 pio interrupt disable register pio_idr write-only ? 0x0048 pio interrupt mask register pio_imr read-only 0x0000 0000 0x004c pio interrupt status register (4) pio_isr read-only 0x0000 0000 0x0050 pio multi-driver enable register pio_mder write-only ? 0x0054 pio multi-driver disable register pio_mddr write-only ? 0x0058 pio multi-driver status register pio_mdsr read-only 0x0000 0000 0x005c reserved 0x0060 pio pull-up disable register pio_pudr write-only ? 0x0064 pio pull-up enable register pio_puer write-only ? 0x0068 pio pad pull-up status register pio_pusr read-only 0x0000 0000 0x006c reserved
343 AT91RM9200 1768b?atarm?08/03 notes: 1. reset value of pio_psr depends on the product implementation. 2. pio_odsr is read-only or read/write depending on pio_owsr i/o lines. 3. reset value of pio_pdsr depends on the level of the i/o lines. 4. pio_isr is reset at 0x0. however, the first read of the register may read a different value as input changes may have occurred. 5. only this set of registers clears the status by writing 1 in the first register and sets the status by writing 1 in the secon d register. 0x0070 pio peripheral a select register (5) pio_asr write-only ? 0x0074 pio peripheral b select register (5) pio_bsr write-only ? 0x0078 pio ab status register (5) pio_absr read-only 0x0000 0000 0x007c to 0x009c reserved 0x00a0 pio output write enable pio_ower write-only ? 0x00a4 pio output write disable pio_owdr write-only ? 0x00a8 pio output write status register pio_owsr read-only 0x0000 0000 0x00ac reserved table 67. pio register mapping (continued) offset register name access reset value
344 AT91RM9200 1768b?atarm?08/03 pio enable register name: pio_per access type: write-only ? p0 - p31: pio enable 0 = no effect. 1 = enables the pio to control the corresponding pin (disables peripheral control of the pin). pio disable register name: pio_pdr access type: write-only p0 - p31: pio disable 0 = no effect. 1 = disables the pio from controlling the corresponding pin (enables peripheral control of the pin). 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
345 AT91RM9200 1768b?atarm?08/03 pio status register name: pio_psr access type: read-only p0 - p31: pio status 0 = pio is inactive on the corresponding i/o line (peripheral is active). 1 = pio is active on the corresponding i/o line (peripheral is inactive). pio output enable register name: pio_oer access type: write-only p0 - p31: output enable 0 = no effect. 1 = enables the output on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
346 AT91RM9200 1768b?atarm?08/03 pio output disable register name: pio_odr access type: write-only p0 - p31: output disable 0 = no effect. 1 = disables the output on the i/o line. pio output status register name: pio_osr access type: read-only p0 - p31: output status 0 = the i/o line is a pure input. 1 = the i/o line is enabled in output. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
347 AT91RM9200 1768b?atarm?08/03 pio input filter enable register name: pio_ifer access type: write-only p0 - p31: input filter enable 0 = no effect. 1 = enables the input glitch filter on the i/o line. pio input filter disable register name: pio_ifdr access type: write-only p0 - p31: input filter disable 0 = no effect. 1 = disables the input glitch filter on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
348 AT91RM9200 1768b?atarm?08/03 pio input filter status register name: pio_ifsr access type: read-only p0 - p31: input filer status 0 = the input glitch filter is disabled on the i/o line. 1 = the input glitch filter is enabled on the i/o line. pio set output data register name: pio_sodr access type: write-only p0 - p31: set output data 0 = no effect. 1 = sets the data to be driven on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
349 AT91RM9200 1768b?atarm?08/03 pio clear output data register name: pio_codr access type: write-only p0 - p31: set output data 0 = no effect. 1 = clears the data to be driven on the i/o line. pio output data status register name: pio_odsr access type: read-only or read/write p0 - p31: output data status 0 = the data to be driven on the i/o line is 0. 1 = the data to be driven on the i/o line is 1. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
350 AT91RM9200 1768b?atarm?08/03 pio pin data status register name: pio_pdsr access type: read-only p0 - p31: output data status 0 = the i/o line is at level 0. 1 = the i/o line is at level 1. pio interrupt enable register name: pio_ier access type: write-only p0 - p31: input change interrupt enable 0 = no effect. 1 = enables the input change interrupt on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
351 AT91RM9200 1768b?atarm?08/03 pio interrupt disable register name: pio_idr access type: write-only p0 - p31: input change interrupt disable 0 = no effect. 1 = disables the input change interrupt on the i/o line. pio interrupt mask register name: pio_imr access type: read-only p0 - p31: input change interrupt mask 0 = input change interrupt is disabled on the i/o line. 1 = input change interrupt is enabled on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
352 AT91RM9200 1768b?atarm?08/03 pio interrupt status register name: pio_imr access type: read-only p0 - p31: input change interrupt mask 0 = no input change has been detected on the i/o line since pio_isr was last read or since reset. 1 = at least one input change has been detected on the i/o line since pio_isr was last read or since reset. pio multi-driver enable register name: pio_mder access type: write-only p0 - p31: multi drive enable 0 = no effect. 1 = enables multi drive on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
353 AT91RM9200 1768b?atarm?08/03 pio multi-driver disable register name: pio_mddr access type: write-only p0 - p31: multi drive disable 0 = no effect. 1 = disables multi drive on the i/o line. pio multi-driver status register name: pio_mdsr access type: read-only p0 - p31: multi drive status 0 = the multi drive is disabled on the i/o line. the pin is driven at high and low level. 1 = the multi drive is enabled on the i/o line. the pin is driven at low level only. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
354 AT91RM9200 1768b?atarm?08/03 pio pull up disable register name: pio_pudr access type: write-only p0 - p31: pull up disable 0 = no effect. 1 = disables the pull up resistor on the i/o line. pio pull up enable register name: pio_puer access type: write-only p0 - p31: pull up enable 0 = no effect. 1 = enables the pull up resistor on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
355 AT91RM9200 1768b?atarm?08/03 pio pad pull up status register name: pio_pusr access type: read-only p0 - p31: pull up status 0 = pull up resistor is enabled on the i/o line. 1 = pull up resistor is disabled on the i/o line. pio peripheral a select register name: pio_asr access type: write-only p0 - p31: peripheral a select 0 = no effect. 1 = assigns the i/o line to the peripheral a function. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
356 AT91RM9200 1768b?atarm?08/03 pio peripheral b select register name: pio_bsr access type: write-only p0 - p31: peripheral b select 0 = no effect. 1 = assigns the i/o line to the peripheral b function. pio peripheral ab status register name: pio_absr access type: read-only p0 - p31: peripheral a b status 0 = the i/o line is assigned to the peripheral a. 1 = the i/o line is assigned to the peripheral b. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
357 AT91RM9200 1768b?atarm?08/03 pio output write enable register name: pio_ower access type: write-only p0 - p31: output write enable 0 = no effect. 1 = enables writing pio_odsr for the i/o line. pio output write disable register name: pio_owdr access type: write-only p0 - p31: output write disable 0 = no effect. 1 = disables writing pio_odsr for the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
358 AT91RM9200 1768b?atarm?08/03 pio output write status register name: pio_owsr access type: read-only p0 - p31: output write status 0 = writing pio_odsr does not affect the i/o line. 1 = writing pio_odsr affects the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
359 AT91RM9200 1768b?atarm?08/03 serial peripheral interface (spi) overview the serial peripheral interface (spi) circuit is a synchronous serial data link that provides communication with external devices in master or slave mode. it also allows communication between processors if an external processor is connected to the system. the serial peripheral interface is a shift register that serially transmits data bits to other spis. during a data transfer, one spi system acts as the master that controls the data flow, while the other system acts as the slave, having data shi fted into and out of it by the master. different cpus can take turn being masters (multiple master protocol versus single master protocol where one cpu is always the master while all of the others are always slaves), and one mas- ter may simultaneously shift data into multiple slaves. however, only one slave may drive its output to write data back to the master at any given time. a slave device is selected when the master asse rts its nss signal. if multiple slave devices exist, the master generates a separate slave select signal for each slave (npcs). the spi system consists of two data lines and two control lines: master out slave in (mosi): this data line supplies the output data from the master shifted into the input(s) of the slave(s). master in slave out (miso): this data line supplies the output data from a slave to the input of the master. there may be no more than one slave transmitting data during any particular transfer. serial clock (spck): this control line is driven by the master and regulates the flow of the data bits. the master may transmit data at a variety of baud rates; the spck line cycles once for each bit that is transmitted. slave select (nss): this control line allows slaves to be turned on and off by hardware. the main features of the spi are: supports communication with serial external devices ? 4 chip selects with external decoder support allow communication with up to 15 peripherals ? serial memories, such as dataflash and 3-wire eeproms ? serial peripherals, such as adcs, dacs, lcd controllers, can controllers and sensors ? external co-processors master or slave serial peripheral bus interface ? 8- to 16-bit programmable data length per chip select ? programmable phase and polarity per chip select ? programmable transfer delays between consecutive transfers and between clock and data per chip select ? programmable delay between consecutive transfers ? selectable mode fault detection connection to pdc channel capabilities optimizes data transfers ? one channel for the receiver, one channel for the transmitter ? next buffer support
360 AT91RM9200 1768b?atarm?08/03 block diagram figure 153. block diagram spi interface interrupt control pio pdc apb bridge pmc mck spi interrupt spck miso mosi npcs0/nss npcs1 npcs2 npcs3 asb apb
361 AT91RM9200 1768b?atarm?08/03 application block diagram figure 154. application block diagram: single master/multiple slave implementation spi master spck miso mosi npcs0 npcs1 npcs2 spck miso mosi nss slave 0 spck miso mosi nss slave 1 spck miso mosi nss slave 2 nc npcs3 table 68. signal description pin name pin description type master slave miso master in slave out input output mosi master out slave in output input spck serial clock output input npcs1-npcs3 peripheral chip selects output unused npcs0/nss peripheral chip select/slave select output input
362 AT91RM9200 1768b?atarm?08/03 product dependencies i/o lines the pins used for interfacing the compliant external devices may be multiplexed with pio lines. the programmer must first program the pio controllers to assign the spi pins to their peripheral functions. power management the spi may be clocked through the power management controller (pmc), thus the program- mer must first have to configure the pmc to enable the spi clock. interrupt the spi interface has an interrupt line connected to the advanced interrupt controller (aic). handling the spi interrupt requires programming the aic before configuring the spi. functional description master mode operations when configured in master mode, the serial peripheral interface controls data transfers to and from the slave(s) connected to the spi bus. the spi drives the chip select(s) to the slave(s) and the serial clock (spck). after enabling the spi, a data transfer begins when the core writes to the spi_tdr (transmit data register). transmit and receive buffers maintain the data flow at a constant rate with a reduced require- ment for high-priority interrupt servicing. when new data is available in the spi_tdr, the spi continues to transfer data. if the spi_rdr (receive data register) has not been read before new data is received, the overrun error (ovres) flag is set. note: as long as this flag is set, no data is loaded in the spi_rdr. the user has to read the status register to clear it. the programmable delay between the activation of the chip select and the start of the data transfer (dlybs), as well as the delay between each data transfer (dlybct), can be pro- grammed for each of the four external chip selects. all data transfer characteristics, including the two timing values, are programmed in registers spi_csr0 to spi_csr3 (chip select registers). in master mode, the peripheral selection can be defined in two different ways: fixed peripheral select: spi exchanges data with only one peripheral variable peripheral select: data can be exchanged with more than one peripheral figure 159 and figure 160 show the operation of the spi in master mode. for details concern- ing the flag and control bits in these diagra ms, see the tables in the programmer?s model, starting in section . fixed peripheral select this mode is used for transferring memory bl ocks without the extra overhead in the transmit data register to determine the peripheral. fixed peripheral select is activated by setting bit ps to zero in spi_mr (mode register). the peripheral is defined by the pcs field in spi_mr. this option is only available when the spi is programmed in master mode. variable peripheral select variable peripheral select is activated by setting bit ps to one. the pcs field in spi_tdr is used to select the destination peripheral. the data transfer characteristics are changed when the selected peripheral changes, according to the associated chip select register. the pcs field in the spi_mr has no effect. this option is only available when the spi is programmed in master mode.
363 AT91RM9200 1768b?atarm?08/03 chip selects the chip select lines are driven by the spi only if it is programmed in master mode. these lines are used to select the destination peripheral. the pcsdec field in spi_mr (mode reg- ister) selects one to four peripherals (pcsdec = 0) or up to 15 peripherals (pcsdec = 1). if variable peripheral select is active, the chip select signals are defined for each transfer in the pcs field in spi_tdr. chip select signals can thus be defined independently for each transfer. if fixed peripheral select is active, chip select signals are defined for all transfers by the field pcs in spi_mr. if a transfer with a new peripheral is necessary, the software must wait until the current transfer is completed, then change the value of pcs in spi_mr before writing new data in spi_tdr. the value on the npcs pins at the end of each transfer can be read in the spi_rdr (receive data register). by default, all npcs signals are high (equal to one) before and after each transfer. clock generation and transfer delays the spi baud rate clock is generated by dividing the master clock (mck) or the master clock divided by 32 (if div32 is set in the mode register) by a value between 4 and 510. the divisor is defined in the scbr field in each chip select register. the transfer speed can thus be defined independently for each chip select signal. figure 155 shows a chip select transfer chang e and consecutive transfers on the same chip selects. three delays can be programmed to modify the transfer waveforms: delay between chip selects, programmable only once for all the chip selects by writing the field dlybcs in the mode register. allows insertion of a delay between release of one chip select and before assertion of a new one. delay before spck, independently programmable for each chip select by writing the field dlybs. allows the start of spck to be delayed until after the chip select has been asserted. delay between consecutive transfers, independently programmable for each chip select by writing the field dlybct. allows insertion of a delay between two transfers occurring on the same chip select these delays allow the spi to be adapted to the interfaced peripherals and their speed and bus release time. figure 155. programmable delays chip select 1 chip select 2 spck dlybcs dlybs dlybct dlybct
364 AT91RM9200 1768b?atarm?08/03 mode fault detection a mode fault is detected when the spi is programmed in master mode and a low level is driven by an external master on the npcs0/nss signal. when a mode fault is detected, the modf bit in the spi_sr is set until the spi_sr is read and the spi is disabled until re-enabled by bit spien in the spi_cr (control register). by default, mode fault detection is enabled. it is disabled by setting the modfdis bit in the spi mode register.
365 AT91RM9200 1768b?atarm?08/03 master mode flow diagram figure 156. master mode flow diagram spi enable tdre ps 1 0 0 1 1 1 0 same peripheral new peripheral npcs = spi_tdr(pcs) npcs = spi_mr(pcs) delay dlybs serializer = spi_tdr(td) tdre = 1 data transfer spi_rdr(rd) = serializer rdrf = 1 tdre ps npcs = 0xf delay dlybcs spi_tdr(pcs) npcs = 0xf delay dlybcs npcs = spi_tdr(pcs) fixed peripheral variable peripheral fixed peripheral variable peripheral delay dlybct 0
366 AT91RM9200 1768b?atarm?08/03 master mode block diagram figure 157. master mode block diagram 0 1 spi_mr(div32) mck mck/32 spck clock generator spi_csrx[15:0] s r q m o d f t d r e r d r f o v r e s p i e n s 0 1 spi_mr(ps) pcs spi_rdr serializer miso spi_mr(pcs) spidis spien spi_mr(mstr) spi_ier spi_idr spi_imr spi_sr mosi npcs3 npcs2 npcs1 npcs0 lsb msb spck spi interrupt rd pcs spi_tdr td
367 AT91RM9200 1768b?atarm?08/03 spi slave mode in slave mode, the spi waits for nss to go active low before receiving the serial clock from an external master. in slave mode, cpol, ncpha and bits fields of spi_csr0 are used to define the transfer characteristics. the other chip select registers are not used in slave mode. in slave mode, the low and high pulse durations of the input clock on spck must be longer than two master clock periods. figure 158. slave mode block diagram s r q t d r e r d r f o v r e s p i e n s serializer spck spidis spien spi_ier spi_idr spi_imr spi_sr miso lsb msb nss mosi spi_rdr rd spi_tdr td spi interrupt
368 AT91RM9200 1768b?atarm?08/03 data transfer four modes are used for data transfers. these modes correspond to combinations of a pair of parameters called clock polarity (cpol) and clock phase (ncpha) that determine the edges of the clock signal on which the data are driven and sampled. each of the two parameters has two possible states, resulting in four possibl e combinations that are incompatible with one another. thus a master/slave pair must use the same parameter pair values to communicate. if multiple slaves are used and fixed in differen t configurations, the master must reconfigure itself each time it needs to communicate with a different slave. table 69 shows the four modes and corresponding parameter settings. figure 159 and figure 160 show examples of data transfers. figure 159. spi transfer format (ncpha = 1, 8 bits per transfer) table 69. spi bus protocol mode spi mode cpol ncpha 000 101 210 311 spck (cpol = 0) (mode 1) spck (cpol = 1) (mode 3) 1 234 5 67 mosi (from master) miso (from slave) nss (to slave) spck cycle (for reference) 8 msb msb lsb lsb 6 6 6 5 5 4 4 3 3 2 2 1 1 * * not defined, but normally msb of previous character received.
369 AT91RM9200 1768b?atarm?08/03 figure 160. spi transfer format (ncpha = 0, 8 bits per transfer) spck (cpol = 0) (mode 0) spck (cpol = 1) (mode 2) 1 234 5 67 mosi (from master) miso (from slave) nss (to slave) spck cycle (for reference) 8 msb msb lsb lsb 6 6 6 5 5 4 4 3 3 2 2 1 1 * not defined but normally lsb of previous character transmitted. *
370 AT91RM9200 1768b?atarm?08/03 serial peripheral interface (spi) user interface table 70. spi register mapping offset register register name access reset 0x00 control register spi_cr write-only --- 0x04 mode register spi_mr read/write 0x0 0x08 receive data register spi_rdr read-only 0x0 0x0c transmit data register spi_tdr write-only --- 0x10 status register spi_sr read-only 0x000000f0 0x14 interrupt enable register spi_ier write-only --- 0x18 interrupt disable register spi_idr write-only --- 0x1c interrupt mask register spi_imr read-only 0x0 0x20 - 0x2c reserved 0x30 chip select register 0 spi_csr0 read/write 0x0 0x34 chip select register 1 spi_csr1 read/write 0x0 0x38 chip select register 2 spi_csr2 read/write 0x0 0x3c chip select register 3 spi_csr3 read/write 0x0 0x40 - 0xff reserved 0x100 - 0x124 reserved for the pdc
371 AT91RM9200 1768b?atarm?08/03 spi control register name: spi_cr access type: write-only spien: spi enable 0 = no effect. 1 = enables the spi to transfer and receive data. spidis: spi disable 0 = no effect. 1 = disables the spi. all pins are set in input mode and no data is received or transmitted. if a transfer is in progress, the transfer is finished before the spi is disabled. if both spien and spidis are equal to one when the control register is written, the spi is disabled swrst: spi software reset 0 = no effect. 1 = reset the spi. a software-triggered hardware reset of the spi interface is performed. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 swrst ? ? ? ? ? spidis spien
372 AT91RM9200 1768b?atarm?08/03 spi mode register name: spi_mr access type: read/write mstr: master/slave mode 0 = spi is in slave mode. 1 = spi is in master mode. ps: peripheral select 0 = fixed peripheral select. 1 = variable peripheral select. pcsdec: chip select decode 0 = the chip selects are directly connected to a peripheral device. 1 = the four chip select lines are connected to a 4- to 16-bit decoder. when pcsdec equals one, up to 16 chip select signals can be generated with the four lines using an external 4- to 16-bit decoder. the chip select registers define the characteristics of the 16 chip selects according to the following rules: spi_csr0 defines peripheral chip select signals 0 to 3. spi_csr1 defines peripheral chip select signals 4 to 7. spi_csr2 defines peripheral chip select signals 8 to 11. spi_csr3 defines peripheral chip select signals 12 to 15*. *note : the 16th state corresponds to a state in which all chip selects are inactive. this allows a different clock configuration to be defined by each chip select register . div32: clock selection 0 = the spi operates at mck. 1 = the spi operates at mck/32. modfdis: mode fault detection 0 = mode fault detection is enabled. 1 = mode fault detection is disabled. llb: local loopback enable 0 = local loopback path disabled 1 = local loopback path enabled llb controls the local loopback on the data serializer for testing in master mode only. 31 30 29 28 27 26 25 24 dlybcs 23 22 21 20 19 18 17 16 ???? pcs 15 14 13 12 11 10 9 8 ???????? 76543210 llb ? ? modfdis div32 pcsdec ps mstr
373 AT91RM9200 1768b?atarm?08/03 pcs: peripheral chip select this field is only used if fixed peripheral select is active (ps = 0). if pcsdec = 0: pcs = xxx0 npcs[3:0] = 1110 pcs = xx01 npcs[3:0] = 1101 pcs = x011 npcs[3:0] = 1011 pcs = 0111 npcs[3:0] = 0111 pcs = 1111 forbidden (no peripheral is selected) (x = don?t care) if pcsdec = 1: npcs[3:0] output signals = pcs dlybcs: delay between chip selects this field defines the delay from npcs inactive to the activation of another npcs. the dlybcs time guarantees non-over- lapping chip selects and solves bus contentions in case of peripherals having long data float times. if dlybcs is less than or equal to six, six mck periods (or 192 mck periods if div32 is set) will be inserted by default. otherwise, the following equation determines the delay: if div32 is 0: if div32 is 1: delay between chip selects dlybcs mck ? = delay between chip selects dlybcs 32 mck ? =
374 AT91RM9200 1768b?atarm?08/03 spi receive data register name: spi_rdr access type: read-only rd: receive data data received by the spi interface is stored in this register right-justified. unused bits read zero. pcs: peripheral chip select in master mode only, these bits indicate the value on the np cs pins at the end of a transfer. otherwise, these bits read zero. spi transmit data register name: spi_tdr access type: write-only td: transmit data data to be transmitted by the spi interface is stored in this register. information to be transmitted must be written to the transmit data register in a right-justified format. pcs: peripheral chip select this field is only used if variable peripheral select is active (ps = 1). if pcsdec = 0: pcs = xxx0 npcs[3:0] = 1110 pcs = xx01 npcs[3:0] = 1101 pcs = x011 npcs[3:0] = 1011 pcs = 0111 npcs[3:0] = 0111 pcs = 1111 forbidden (no peripheral is selected) (x = don?t care) if pcsdec = 1: npcs[3:0] output signals = pcs 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???? pcs 15 14 13 12 11 10 9 8 rd 76543210 rd 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???? pcs 15 14 13 12 11 10 9 8 td 76543210 td
375 AT91RM9200 1768b?atarm?08/03 spi status register name: spi_sr access type: read-only rdrf: receive data register full 0 = no data has been received since the last read of spi_rdr 1 = data has been received and the received data has been transferred from the serializer to spi_rdr since the last read of spi_rdr. tdre: transmit data register empty 0 = data has been written to spi_tdr and not yet transferred to the serializer. 1 = the last data written in the transmit data register has been transferred to the serializer. tdre equals zero when the spi is disabled or at reset. the spi enable command sets this bit to one. modf: mode fault error 0 = no mode fault has been detected since the last read of spi_sr. 1 = a mode fault occurred since the last read of the spi_sr. ovres: overrun error status 0 = no overrun has been detected since the last read of spi_sr. 1 = an overrun has occurred since the last read of spi_sr. an overrun occurs when spi_rdr is loaded at least twice from the serializer since the last read of the spi_rdr. endrx: end of rx buffer 0 = the receive counter re g ister has not reached 0 since the last write in spi_rcr or spi_rncr. 1 = the receive counter re g ister has reached 0 since the last write in spi_rcr or spi_rncr. endtx: end of tx buffer 0 = the transmit counter re g ister has not reached 0 since the last write in spi_tcr or spi_tncr. 1 = the transmit counter re g ister has reached 0 since the last write in spi_tcr or spi_tncr. rxbuff: rx buffer full 0 = spi_rcr or spi_rncr have a value other than 0. 1 = both spi_rcr and spi_rncr have a value of 0. txbufe: tx buffer empty 0 = spi_tcr or spi_tncr have a value other than 0. 1 = both spi_tcr and spi_tncr have a value of 0. spiens: spi enable status 0 = spi is disabled. 1 = spi is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????spiens 15 14 13 12 11 10 9 8 ???????? 76543210 txbufe rxbuff endtx endrx ovres modf tdre rdrf
376 AT91RM9200 1768b?atarm?08/03 spi interrupt enable register name: spi_ier access type: write-only rdrf: receive data register full interrupt enable tdre: spi transmit data register empty interrupt enable modf: mode fault error interrupt enable ovres: overrun error interrupt enable endrx: end of receive buffer interrupt enable endtx: end of transmit buffer interrupt enable rxbuff: receive buffer full interrupt enable txbufe: transmit buffer empty interrupt enable 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 txbufe rxbuff endtx endrx ovres modf tdre rdrf
377 AT91RM9200 1768b?atarm?08/03 spi interrupt disable register name: spi_idr access type: write-only rdrf: receive data register full interrupt disable tdre: spi transmit data register empty interrupt disable modf: mode fault error interrupt disable ovres: overrun error interrupt disable endrx: end of receive buffer interrupt disable endtx: end of transmit buffer interrupt disable rxbuff: receive buffer full interrupt disable txbufe: transmit buffer empty interrupt disable 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 txbufe rxbuff endtx endrx ovres modf tdre rdrf
378 AT91RM9200 1768b?atarm?08/03 spi interrupt mask register name: spi_imr access type: read-only rdrf: receive data register full interrupt mask tdre: spi transmit data register empty interrupt mask modf: mode fault error interrupt mask ovres: overrun error interrupt mask endrx: end of receive buffer interrupt mask endtx: end of transmit buffer interrupt mask rxbuff: receive buffer full interrupt mask txbufe: transmit buffer empty interrupt mask 0 = the corresponding interrupt is not enabled. 1 = the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 txbufe rxbuff endtx endrx ovres modf tdre rdrf
379 AT91RM9200 1768b?atarm?08/03 spi chip select register name: spi_csr0... spi_csr3 access type: read/write cpol: clock polarity 0 = the inactive state value of spck is logic level zero. 1 = the inactive state value of spck is logic level one. cpol is used to determine the inactive state value of the serial clock (spck). it is used with ncpha to produce the required clock/data relationship between master and slave devices. ncpha: clock phase 0 = data is changed on the leading edge of spck and captured on the following edge of spck. 1 = data is captured on the leading edge of spck and changed on the following edge of spck. ncpha determines which edge of spck causes data to change and which edge causes data to be captured. ncpha is used with cpol to produce the required clock/data relationship between master and slave devices. bits: bits per transfer the bits field determines the number of data bits transferred. reserved values should not be used. 31 30 29 28 27 26 25 24 dlybct 23 22 21 20 19 18 17 16 dlybs 15 14 13 12 11 10 9 8 scbr 76543210 bits ? ? ncpha cpol bits[3:0] bits per transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15 1000 16 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved
380 AT91RM9200 1768b?atarm?08/03 scbr: serial clock baud rate in master mode, the spi interface uses a modulus counter to derive the spck baud rate from the master clock mck. the baud rate is selected by writing a value from 2 to 255 in the field scbr. the following equation determines the spck baud rate: if div32 is 0: if div32 is 1: giving scbr a value of zero or one disables the baud rate generator. spck is disabled and assumes its inactive state value. no serial transfers may occur. at reset, baud rate is disabled. dlybs: delay before spck this field defines the delay from npcs valid to the first valid spck transition. when dlybs equals zero, the npcs valid to spck transition is 1/2 the spck clock period. otherwise, the following equations determine the delay: if div32 is 0: if div32 is 1: dlybct: delay between consecutive transfers this field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. the delay is always inserted after each transfer and before removing the chip select if needed. when dlybct equals zero, a minimum delay of four mck cycles are inserted (or 128 mck cycles when div32 is set) between two consecutive characters. otherwise, the following equation determines the delay: if div32 is 0: if div32 is 1: spck baudrate mck 2 scbr () ? = spck baudrate mck 64 scbr () ? = delay before spck dlybs mck ? = delay before spck 32 dlybs mck ? = delay between consecutive transfers 32 dlybct mck ? = delay between consecutive transfers 1024 dlybct mck ? =
381 AT91RM9200 1768b?atarm?08/03 two-wire interface (twi) overview the two-wire interface (twi) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 kbits per second, based on a byte- oriented transfer format. it can be used with any atmel two-wire bus serial eeprom. the twi is programmable as a master with sequential or single-byte access. a configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock frequencies. the main features of the twi are: compatibility with standard two-wire serial memory one, two or three bytes for slave address sequential read/write operations block diagram figure 161. block diagram application block diagram figure 162. application block diagram apb bridge pmc mck two-wire interface pio aic twi interrupt twck twd host with twi interface twd twck at24lc16 u1 at24lc16 u2 lcd controller u3 slave 1 slave 2 slave 3 rr vdd
382 AT91RM9200 1768b?atarm?08/03 product dependencies i/o lines both twd and twck are bi-directional lines, connected to a positive supply voltage via a cur- rent source or pull-up resistor (see figure 162 on page 381). when the bus is free, both lines are high. the output stages of devices connected to the bus must have an open-drain or open- collector to perform the wired-and function. twd and twck pins may be multiplexed with pio lines. to enable the twi, the programmer must perform the following steps: program the pio controller to: ? dedicate twd and twck as peripheral lines. ? define twd and twck as open-drain. power management enable the peripheral clock. the twi interface may be clocked through the power management controller (pmc), thus the programmer must first configure the pmc to enable the twi clock. interrupt the twi interface has an interrupt line connected to the advanced interrupt controller (aic). in order to handle interrupts, the aic must be programmed before configuring the twi. functional description transfer format the data put on the twd line must be eight bits long. data is transferred msb first; each byte must be followed by an acknowledgement. the number of bytes per transfer is unlimited (see figure 164 on page 383). each transfer begins with a start condition and terminates with a stop condition (see fig- ure 163 on page 382). a high-to-low transition on the twd line while twck is high defines the start condition. a low-to-high transition on the twd line while twck is high defines a stop condition. figure 163. start and stop conditions table 71. i/o lines description pin name pin description type twd two-wire serial data input/output twck two-wire serial clock input/output twd twck start stop
383 AT91RM9200 1768b?atarm?08/03 figure 164. transfer format modes of operation the twi has two modes of operations: master transmitter mode master receiver mode the twi control register (twi_cr) allows configuration of the interface in master mode. in this mode, it generates the clock according to the value programmed in the clock waveform generator register (twi_cwgr). this regi ster defines the twck signal completely, enabling the interface to be adapted to a wide range of clocks. transmitting data after the master initiates a start condition, it sends a 7-bit slave address, configured in the master mode register (dadr in twi_mmr), to notify the slave device. the bit following the slave address indicates the transfer direction (write or read). if this bit is 0, it indicates a write operation (transmit operation). if the bit is 1, it indicates a request for data read (receive operation). the twi transfers require the slave to acknowledge each received byte. during the acknowl- edge clock pulse, the master releases the data line (high), enabling the slave to pull it down in order to generate the acknowledge. the mast er polls the data line during this clock pulse and sets the nak bit in the status register if the slave does not acknowledge the byte. as with the other status bits, an interrupt can be generated if enabled in the interrupt enable register (twi_ier). after writing in the transmit-holding register (twi_thr), setting the start bit in the control register starts the transmission. the data is shifted in the internal shifter and when an acknowledge is detected, the txrdy bit is set until a new write in the twi_thr (see fig- ure 166 on page 384). the master generates a stop condition to end the transfer. the read sequence begins by setting the start bit. when the rxrdy bit is set in the status register, a character has been received in the receive-holding register (twi_rhr). the rxrdy bit is reset when reading the twi_rhr. the twi interface performs various transfer formats (7-bit slave address, 10-bit slave address). the three internal address bytes are configurable through the master mode register (twi_mmr). if the slave device supports only a 7-bit address, the iadrsz must be set to 0. for slave address higher than seven bits, the user must configure the address size (iadrsz ) and set the other slave address bits in the internal address register (twi_iadr). figure 165. master write with one, two or three bytes internal address and one data byte twd twck start address r/w ack data ack data ack stop s dadr w a iadr(23:16) a iadr(15:8) a iadr(7:0) a data a p s dadr w a iadr(15:8) a iadr(7:0) a p data a a iadr(7:0) a p data a s dadr w twd three bytes internal address two bytes internal address one byte internal address twd twd
384 AT91RM9200 1768b?atarm?08/03 figure 166. master write with one byte internal address and multiple data bytes figure 167. master read with one, two or three bytes internal address and one data byte figure 168. master read with one byte internal address and multiple data bytes s = start p = stop w = write/read a = acknowledge dadr= device address iadr = internal address figure 169 shows a byte write to an atmel at24lc512 eeprom. this demonstrates the use of internal addresses to access the device. a iadr(7:0) a data a s dadr w data a p data a txcomp txrdy write thr write thr write thr write thr twd s dadr w a iadr(23:16) a iadr(15:8) a iadr(7:0) a s dadr w a iadr(15:8) a iadr(7:0) a a iadr(7:0) a s dadr w data n p s dadr r a s dadr r a data n p s dadr r a data n p twd twd twd three bytes internal address two bytes internal address one byte internal address a iadr(7:0) a s dadr w s dadr r a data a data n p txcomp write start bit rxrdy write stop bit read rhr read rhr twd
385 AT91RM9200 1768b?atarm?08/03 figure 169. internal address usage read/write flowcharts the following flowcharts shown in figure 170 on page 386 and in figure 171 on page 387 give examples for read and write operations in master mode. a polling or interrupt method can be used to check the status bits. the interrupt method requires that the interrupt enable register (twi_ier) be configured first. s t a r t m s b device address 0 l s b r / w a c k m s b w r i t e a c k a c k l s b a c k first word address second word address data s t o p
386 AT91RM9200 1768b?atarm?08/03 figure 170. twi write in master mode set twi clock: twi_cwgr = clock set the control register: - master enable - slave disable twi_cr = twi_svdis + twi_msen set the master mode register: - device slave address - internal address size - transfer direction bit write ==> bit mread = 0 internal address size = 0? load transmit register twi_thr = data to send start the transfer twi_cr = twi_start stop the transfer twi_cr = twi_stop read status register txrdy = 0? data to send? read status register txcomp = 0? end start set theinternal address twi_iadr = address yes twi_thr = data to send yes yes
387 AT91RM9200 1768b?atarm?08/03 figure 171. twi read in master mode set twi clock: twi_cwgr = clock set the control register: - master enable - slave disable twi_cr = twi_svdis + twi_msen set the master mode register: - device slave address - internal address size - transfer direction bit read ==> bit mread = 0 internal address size = 0? start the transfer twi_cr = twi_start stop the transfer twi_cr = twi_stop read status register rxrdy = 0? data to read? read status register txcomp = 0? end start set theinternal address twi_iadr = address yes yes yes yes
388 AT91RM9200 1768b?atarm?08/03 two-wire interface (twi) user interface table 72. twi register mapping offset register name access reset value 0x0000 control register twi_cr write-only n/a 0x0004 master mode register twi_mmr read/write 0x0000 0x0008 reserved 0x000c internal address register twi_iadr read/write 0x0000 0x0010 clock waveform generator register twi_cwgr read/write 0x0000 0x0020 status register twi_sr read-only 0x0008 0x0024 interrupt enable register twi_ier write-only n/a 0x0028 interrupt disable register twi_idr write-only n/a 0x002c interrupt mask register twi_imr read-only 0x0000 0x0030 receive holding register twi_rhr read-only 0x0000 0x0034 transmit holding register twi_thr read/write 0x0000
389 AT91RM9200 1768b?atarm?08/03 twi control register register name :twi_cr access type: write-only start: send a start condition 0 = no effect. 1 = a frame beginning with a start bit is transmitted according to the features defined in the mode register. this action is necessary when the twi peripheral wants to read data from a slave. when configured in master mode with a write operation, a frame is sent with the mode register as soon as the user writes a character in the holding register. stop: send a stop condition 0 = no effect. 1 = stop condition is sent just after completing the current byte transmission in master read or write mode. in single data byte master read or write, the start and stop must both be set. in multiple data bytes master read or write, the stop must be set before ack/nack bit transmission. in master read mode, if a nack bit is received, the stop is automatically performed. in multiple data write operation, when both thr and shift register are empty, a stop condition is automatically sent. msen: twi master transfer enabled 0 = no effect. 1 = if msdis = 0, the master data transfer is enabled. msdis: twi master transfer disabled 0 = no effect. 1 = the master data transfer is disabled, all pending data is transmitted. the shifter and holding characters (if it contains data) are transmitted in case of write operation. in read operation, the character being transferred must be completely received before disabling. swrst: software reset 0 = no effect. 1 = equivalent to a system reset. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 swrst ? ? ? msdis msen stop start
390 AT91RM9200 1768b?atarm?08/03 twi master mode register register name :twi_mmr address type : read/write iadrsz: internal device address size mread: master read direction 0 = master write direction. 1 = master read direction. dadr: device address the device address is used in master mode to access slave devices in read or write mode. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?dadr 15 14 13 12 11 10 9 8 ? ? ? mread ? ? iadrsz 76543210 ???????? iadrsz[9:8] 00 no internal device address 01 one-byte internal device address 10 two-byte internal device address 11 three-byte internal device address
391 AT91RM9200 1768b?atarm?08/03 twi internal address register register name :twi_iadr access type : read/write iadr: internal address 0, 1, 2 or 3 bytes depending on iadrsz. twi clock waveform generator register register name :twi_cwgr access type : read/write cldiv: clock low divider the twck low period is defined as follows: chdiv: clock high divider the twck high period is defined as follows: ckdiv: clock divider the ckdiv is used to increase both twck high and low periods. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 iadr 15 14 13 12 11 10 9 8 iadr 76543210 iadr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????? ckdiv 15 14 13 12 11 10 9 8 chdiv 76543210 cldiv t low cldiv ( 2 ckdiv () 3 ) + t mck = t high chdiv ( 2 ckdiv () 3 ) + t mck =
392 AT91RM9200 1768b?atarm?08/03 twi status register register name :twi_sr access type : read-only txcomp: transmission completed 0 = in master, during the length of the current frame. in slave, from start received to stop received. 1 = when both holding and shifter registers are empty and stop condition has been sent (in master) or received (in slave), or when msen is set (enable twi). rxrdy: receive holding register ready 0 = no character has been received since the last twi_rhr read operation. 1 = a byte has been received in thetwi_rhr since the last read. txrdy: transmit holding register ready 0 = the transmit holding register has not been transferred into shift register. set to 0 when writing into twi_thr register. 1 = as soon as data byte is transferred from twi_thr to internal shifter or if a nack error is detected, txrdy is set at the same time as txcomp and nack. txrdy is also set when msen is set (enable twi). ovre: overrun error 0 = twi_rhr has not been loaded while rxrdy was set 1 = twi_rhr has been loaded while rxrdy was set. reset by read in twi_sr when txcomp is set. unre: underrun error 0 = no underrun error 1 = no valid data in twi_thr (txrdy set) while trying to load the data shifter. this action automatically generated a stop bit in master mode. reset by read in twi_sr when txcomp is set. nack: not acknowledged 0 = each data byte has been correctly received by the far-end side twi slave component. 1 = a data byte has not been acknowledged by the slave component. set at the same time as txcomp. reset after read. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????nack 76543210 unre ovre ? ? ? txrdy rxrdy txcomp
393 AT91RM9200 1768b?atarm?08/03 twi interrupt enable register register name :twi_ier access type: write-only txcomp: transmission completed rxrdy: receive holding register ready txrdy: transmit holding register ready ovre: overrun error unre: underrun error nack: not acknowledge 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????nack 76543210 unre ovre ? ? ? txrdy rxrdy txcomp
394 AT91RM9200 1768b?atarm?08/03 twi interrupt disable register register name :twi_idr access type : write-only txcomp: transmission completed rxrdy: receive holding register ready txrdy: transmit holding register ready ovre: overrun error unre: underrun error nack: not acknowledge 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????nack 76543210 unre ovre ? ? ? txrdy rxrdy txcomp
395 AT91RM9200 1768b?atarm?08/03 twi interrupt mask register register name :twi_imr access type : read-only txcomp: transmission completed rxrdy: receive holding register ready txrdy: transmit holding register ready ovre: overrun error unre: underrun error nack: not acknowledge 0 = the corresponding interrupt is disabled. 1 = the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????nack 76543210 unre ovre ? ? ? txrdy rxrdy txcomp
396 AT91RM9200 1768b?atarm?08/03 twi receive holding register register name : twi_rhr access type : read-only rxdata: master or slave receive holding data twi transmit holding register register name :twi_thr access type: read/write txdata: master or slave transmit holding data 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 rxdata 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 txdata
397 AT91RM9200 1768b?atarm?08/03 universal synchronous asynchronous receiver transceiver (usart) overview the universal synchronous asynchronous receiv er transceiver (usart) provides one full duplex universal synchronous asynchronous serial link. data frame format is widely program- mable (data length, parity, number of stop bits) to support a maximum of standards. the receiver implements parity error, framing error and overrun error detection. the receiver time- out enables handling variable-length frames and the transmitter timeguard facilitates commu- nications with slow remote devices. multi-drop communications are also supported through address bit handling in reception and transmission. the usart features three test modes: remote loopback, local loopback and automatic echo. the usart supports specific operating mode s providing interfaces on rs485 busses, with iso7816 t = 0 or t = 1 smart card slots, infrared transceivers and connection to modem ports. the hardware handshaking feature enables an out-of-band flow control by automatic manage- ment of the pins rts and cts. the usart supports the connection to the peripheral data controller, which enables data transfers to the transmitter and from the receiver. the pdc provides chained buffer manage- ment without any intervention of the processor. important features of the usart are: programmable baud rate generator 5- to 9-bit full-duplex synchronous or asynchronous serial communications ? 1, 1.5 or 2 stop bits in asynchronous mode or 1 or 2 stop bits in synchronous mode ? parity generation and error detection ? framing error detection, overrun error detection ? msb- or lsb-first ? optional break generation and detection ? by 8 or by-16 over-sampling receiver frequency ? optional hardware handshaking rts-cts ? optional modem signal management dtr-dsr-dcd-ri ? receiver time-out and transmitter timeguard ? optional multi-drop mode with address generation and detection rs485 with driver control signal iso7816, t = 0 or t = 1 protocols for interfacing with smart cards ? nack handling, error counter with repetition and iteration limit irda modulation and demodulation ? communication at up to 115.2 kbps test modes ? remote loopback, local loopback, automatic echo supports connection of two peripheral data controller channels (pdc) ? offer buffer transfer without processor intervention
398 AT91RM9200 1768b?atarm?08/03 block diagram figure 172. usart block diagram peripheral data controller channel channel aic receiver apb usart interrupt rxd txd sck usart pio controller cts rts dtr dsr dcd ri transmitter modem signals control baud rate generator user interface pmc mck slck div mck/div
399 AT91RM9200 1768b?atarm?08/03 application block diagram figure 173. application block diagram i/o lines description product dependencies i/o lines the pins used for interfacing the usart may be multiplexed with the pio lines. the program- mer must first program the pio controller to assign the desired usart pins to their peripheral function. if i/o lines of the usart are not used by the application, they can be used for other purposes by the pio controller. all the pins of the modems may or may not not be implemented on the usart within a prod- uct. frequently, only the usart1 is fully equi pped with all the modem signals. for the other smart card slot usart rs232 drivers modem rs485 drivers differential bus irda transceivers modem driver field bus driver emv driver irda driver irlap rs232 drivers serial port serial driver ppp pstn table 73. i/o line description name description type active level sck serial clock i/o txd transmit serial data i/o rxd receive serial data input ri ring indicator input low dsr data set ready input low dcd data carrier detect input low dtr data terminal ready output low cts clear to send input low rts request to send output low
400 AT91RM9200 1768b?atarm?08/03 usarts of the product not equipped with the corresponding pin, the associated control bits and statuses have no effect on the behavior of the usart. power management the usart is not continuously clocked. the programmer must first enable the usart clock in the power management controller (pmc) before using the usart. however, if the applica- tion does not require usart operations, the usart clock can be stopped when not needed and be restarted later. in this case, the usart will resume its operations where it left off. configuring the usart does not require the usart clock to be enabled. interrupt the usart interrupt line is connected on one of the internal sources of the advanced inter- rupt controller. using the usart interrupt requires the aic to be programmed first. note that it is not recommended to use the usart interrupt line in edge sensitive mode. functional description the usart is capable of managing several types of serial synchronous or asynchronous communications. it supports the following communication modes. 5- to 9-bit full-duplex asynchronous serial communication: ? msb- or lsb-first ? 1, 1.5 or 2 stop bits ? parity even, odd, marked, space or none ? by-8 or by-16 over-sampling receiver frequency ? optional hardware handshaking ? optional modem signals management ? optional break management ? optional multi-drop serial communication high-speed 5- to 9-bit full-duplex synchronous serial communication: ? msb- or lsb-first ? 1 or 2 stop bits ? parity even, odd, marked, space or none ? by 8 or by-16 over-sampling frequency ? optional hardware handshaking ? optional modem signals management ? optional break management ? optional multi-drop serial communication rs485 with driver control signal iso7816, t0 or t1 protocols for interfacing with smart cards ? nack handling, error counter with repetition and iteration limit infrared irda modulation and demodulation test modes ? remote loopback, local loopback, automatic echo baud rate generator the baud rate generator provides the bit per iod clock named the baud rate clock to both the receiver and the transmitter. the baud rate generator clock source can be selected by setting the usclks field in the mode register (us_mr) between:
401 AT91RM9200 1768b?atarm?08/03 the master clock mck a division of the master clock, the divider being product dependent, but generally set to 8 the external clock, available on the sck pin the baud rate generator is based upon a 16- bit divider, which is programmed with the cd field of the baud rate generator register (us_brgr). if cd is programmed at 0, the baud rate generator does not generate any clock. if cd is programmed at 1, the divider is bypassed and becomes inactive. if the external sck clock is selected, the duration of the low and high levels of the signal pro- vided on the sck pin must be longer than a master clock (mck) period. the frequency of the signal provided on sck must be at least 4.5 times lower than mck. figure 174. baud rate generator baud rate in asynchronous mode if the usart is programmed to operate in asynchronous mode, the selected clock is first divided by cd, which is field programmed in the baud rate generator register (us_brgr). the resulting clock is provided to the receiver as a sampling clock and then divided by 16 or 8, depending on the programming of the over bit in us_mr. if over is set to 1, the receiver sampling is 8 times higher than the baud rate clock. if over is cleared, the sampling is performed at 16 times the baud rate clock. the following formula performs the calculation of the baud rate. this gives a maximum baud rate of mck divided by 8, assuming that mck is the highest pos- sible clock and that over is programmed at 1. mck/div 16-bit counter 0 baud rate clock cd cd sampling divider 0 1 >1 sampling clock reserved mck sck usclks over sck sync sync usclks = 3 1 0 2 3 0 1 0 1 fidi baudrate selectedclock 82 over ? () cd () -------------------------------------------- =
402 AT91RM9200 1768b?atarm?08/03 baud rate calculation example table 74 shows calculations of cd to obtain a baud rate at 38400 bauds for different source clock frequencies. this table also shows the actual resulting baud rate and the error. the baud rate is calculated with the following formula: the baud rate error is calculated with the following formula. it is not recommended to work with an error higher than 5%. baud rate in synchronous mode if the usart is programmed to operate in synchronous mode, the selected clock is simply divided by the field cd in us_brgr. table 74. baud rate example (over = 0) source clock expected baud rate calculation result cd actual baud rate error mhz bit/s bit/s 3 686 400 38 400 6.00 6 38 400.00 0.00% 4 915 200 38 400 8.00 8 38 400.00 0.00% 5 000 000 38 400 8.14 8 39 062.50 1.70% 7 372 800 38 400 12.00 12 38 400.00 0.00% 8 000 000 38 400 13.02 13 38 461.54 0.16% 12 000 000 38 400 19.53 20 37 500.00 2.40% 12 288 000 38 400 20.00 20 38 400.00 0.00% 14 318 180 38 400 23.30 23 38 908.10 1.31% 14 745 600 38 400 24.00 24 38 400.00 0.00% 18 432 000 38 400 30.00 30 38 400.00 0.00% 24 000 000 38 400 39.06 39 38 461.54 0.16% 24 576 000 38 400 40.00 40 38 400.00 0.00% 25 000 000 38 400 40.69 40 38 109.76 0.76% 32 000 000 38 400 52.08 52 38 461.54 0.16% 32 768 000 38 400 53.33 53 38 641.51 0.63% 33 000 000 38 400 53.71 54 38 194.44 0.54% 40 000 000 38 400 65.10 65 38 461.54 0.16% 50 000 000 38 400 81.38 81 38 580.25 0.47% 60 000 000 38 400 97.66 98 38 265.31 0.35% 70 000 000 38 400 113.93 114 38 377.19 0.06% baudrate mck cd 16 ? = error 1 expectedbaudrate actualbaudrate -------------------------------------------------- - ?? ?? ? = baudrate selectedclock cd ------------------------------------- - =
403 AT91RM9200 1768b?atarm?08/03 in synchronous mode, if the external clock is selected (usclks = 3), the clock is provided directly by the signal on the usart sck pin. no division is active . the value written in us_brgr has no effect. the external clock frequency must be at least 4.5 times lower than the system clock. when either the external clock sck or the inte rnal clock divided (mck/div) is selected, the value programmed in cd must be even if the user has to ensure a 50:50 mark/space ratio on the sck pin. if the internal clock mck is selected, the baud rate generator ensures a 50:50 duty cycle on the sck pin, even if the value programmed in cd is odd. baud rate in iso 7816 mode the iso7816 specification defines the bit rate with the following formula: where: b is the bit rate di is the bit-rate adjustment factor fi is the clock frequency division factor f is the iso7816 clock frequency (hz) di is a binary value encoded on a 4-bit field, named di, as represented in table 75. fi is a binary value encoded on a 4-bit field, named fi, as represented in table 76. table 77 shows the resulting fi/di ratio, which is the ratio between the iso7816 clock and the baud rate clock.. if the usart is configured in iso7816 mode, the clock selected by the usclks field in the mode register (us_mr) is first divided by the value programmed in the field cd in the baud b di fi ----- - f = table 75. binary and decimal values for d di field 0001 0010 0011 0100 0101 0110 1000 1001 di (decimal) 1 2 4 8 16 32 12 20 table 76. binary and decimal values for f fi field 0000 0001 0010 0011 0100 0101 0110 1001 1010 1011 1100 1101 fi (decimal 372 372 558 744 1116 1488 1860 512 768 1024 1536 2048 table 77. possible values for the fi/di ratio fi/di 372 558 774 1116 1488 1806 512 768 1024 1536 2048 1 372 558 744 1116 1488 1860 512 768 1024 1536 2048 2 186 279 372 558 744 930 256 384 512 768 1024 4 93 139.5 186 279 372 465 128 192 256 384 512 8 46.5 69.75 93 139.5 186 232.5 64 96 128 192 256 16 23.25 34.87 46.5 69.75 93 116.2 32 48 64 96 128 32 11.62 17.43 23.25 34.87 46.5 58.13 16 24 32 48 64 12 31 46.5 62 93 124 155 42.66 64 85.33 128 170.6 20 18.6 27.9 37.2 55.8 74.4 93 25.6 38.4 51.2 76.8 102.4
404 AT91RM9200 1768b?atarm?08/03 rate generator register (us_brgr). the resulting clock can be provided to the sck pin to feed the smart card clock inputs. this means that the clko bit can be set in us_mr. this clock is then divided by the value programmed in the fi_di_ratio field in the fi_di_ratio register (us_fidi). this is performed by the sampling divider, which performs a division by up to 2047 in iso7816 mode. the non-integer values of the fi/di ratio are not sup- ported and the user must program the fi_di_ratio field to a value as close as possible to the expected value. the fi_di_ratio field resets to the value 0x174 (372 in decimal) and is the most common divider between the iso7816 clock and the bit rate (fi = 372, di = 1). figure 175 shows the relation between the elementary time unit, corresponding to a bit time, and the iso 7816 clock. figure 175. elementary time unit (etu) receiver and transmitter control after reset, the receiver is disabled. the user must enable the receiver by setting the rxen bit in the control register (us_cr). however, the receiver registers can be programmed before the receiver clock is enabled. after reset, the transmitter is disabled. the user must enable it by setting the txen bit in the control register (us_cr). however, the transmitter registers can be programmed before being enabled. the receiver and the transmitter can be enabled together or independently. at any time, the software can perform a reset on the receiver or the transmitter of the usart by setting the corresponding bit, rstrx and rstt x respectively, in the control register (us_cr). the reset commands have the same effect as a hardware reset on the correspond- ing logic. regardless of what the receiver or the transmitter is performing, the communication is immediately stopped. the user can also independently disable the receiver or the transmitter by setting rxdis and txdis respectively in us_cr. if the receiver is disabled during a c haracter reception, the usart waits until the end of reception of the current character, then the reception is stopped. if the transmitter is disabled while it is operating, the usart waits the end of transmission of both the current character and character being stored in the transmit holding register (us_thr). if a time guard is programmed, it is handled normally. 1 etu iso7816 clock on sck iso7816 i/o line on txd fi_di_ratio iso7816 clock cycles
405 AT91RM9200 1768b?atarm?08/03 synchronous and asynchronous modes transmitter operations the transmitter performs the same in both synchronous and asynchronous operating modes (sync = 0 or sync = 1). one start bit, up to 9 data bits, one optional parity bit and up to two stop bits are successively shifted out on the txd pin at each falling edge of the programmed serial clock. the number of data bits is selected by the chrl field and the mode9 bit in the mode regis- ter (us_mr). nine bits are selected by setting the mode 9 bit regardless of the chrl field. the parity bit is set according to the par fi eld in us_mr. the even, odd, space, marked or none parity bit can be configured. the msbf field in us_mr configures which data bit is sent first. if written at 1, the most significant bit is sent first. at 0, the less significant bit is sent first. the number of stop bits is selected by the nbstop field in us_mr. the 1.5 stop bit is sup- ported in asynchronous mode only. figure 176. character transmit the characters are sent by writing in the transmit holding register (us_thr). the transmit- ter reports two status bits in the channel status register (us_csr): txrdy (transmitter ready), which indicates that us_thr is empty and txempty, which indicates that all the characters written in us_thr have been processed. when the current character processing is completed, the last character written in us_thr is transferred into the shift register of the transmitter and us_thr becomes empty, thus txrdy raises. both txrdy and txempty bits are low since the transmitter is disabled. writing a character in us_thr while txrdy is active has no effect and the written character is lost. figure 177. transmitter status d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit example: 8-bit, parity enabled one stop baud rate clock d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock start bit write us_thr d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit txrdy txempty
406 AT91RM9200 1768b?atarm?08/03 asynchronous receiver if the usart is programmed in asynchronous operating mode (sync = 0), the receiver over- samples the rxd input line. the oversampling is either 16 or 8 times the baud rate clock, depending on the over bit in the mode register (us_mr). the receiver samples the rxd line. if the line is sampled during one half of a bit time at 0, a start bit is detected and data, parity and stop bits are successively sampled on the bit rate clock. if the oversampling is 16, (over at 0), a start is detected at the eighth sample at 0. then, data bits, parity bit and stop bit are sampled on each 16 sampling clock cycle. if the oversampling is 8 (over at 1), a start bit is detected at the fourth sample at 0. then, data bits, parity bit and stop bit are sampled on each 8 sampling clock cycle. the number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter, i.e. respectively chrl, mode9, msbf and par. the number of stop bits has no effect on the receiver as it considers only one stop bit, regardless of the field nbstop, so that resynchronization between the receiver and the transmitter can occur. moreover, as soon as the stop bit is sampled, the receiver starts looking for a new start bit so that resynchro- nization can also be accomplished when the transmitter is operating with one stop bit. figure 178 and figure 179 illustrate start det ection and character reception when usart operates in asynchronous mode. figure 178. asynchronous start detection figure 179. asynchronous character reception sampling clock (x16) rxd start detection sampling baud rate clock rxd start rejection sampling 12345678 12345670 1234 12345678 9 10111213141516 d0 sampling d0 d1 d2 d3 d4 d5 d6 d7 rxd parity bit stop bit example: 8-bit, parity enabled baud rate clock start detection 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples
407 AT91RM9200 1768b?atarm?08/03 synchronous receiver in synchronous mode (sync = 1), the receiver samples the rxd signal on each rising edge of the baud rate clock. if a low level is detected, it is considered as a start. all data bits, the par- ity bit and the stop bits are sampled and the receiver waits for the next start bit. synchronous mode operations provide a high speed transfer capability. configuration fields and bits are the same as in asynchronous mode. figure 180 illustrates a character reception in synchronous mode. figure 180. synchronous mode character reception receiver operations when a character reception is completed, it is transferred to the receive holding register (us_rhr) and the rxrdy bit in the status register (us_csr) rises. if a character is com- pleted while the rxrdy is set, the ovre (overrun error) bit is set. the last character is transferred into us_rhr and overwrites the previous one. the ovre bit is cleared by writing the control register (us_cr) with the rststa (reset status) bit at 1. figure 181. receiver status parity the usart supports five parity modes selected by programming the par field in the mode register (us_mr). the par field also enables the multidrop mode, which is discussed in a separate paragraph. even and odd parity bit generation and error detection are supported. if even parity is selected, the parity generator of the transmitter drives the parity bit at 1 if a number of 1s in the character data bit is even, and at 0 if the number of 1s is odd. accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. if the odd parity is selected, the parity generator of the d0 d1 d2 d3 d4 d5 d6 d7 rxd start sampling parity bit stop bit example: 8-bit, parity enabled 1 stop baud rate clock d0 d1 d2 d3 d4 d5 d6 d7 rxd start bit parity bit stop bit baud rate clock write us_cr rxrdy ovre d0 d1 d2 d3 d4 d5 d6 d7 start bit parity bit stop bit rststa = 1 read us_rhr
408 AT91RM9200 1768b?atarm?08/03 transmitter drives the parity bit at 0 if a number of 1s in the character data bit is even, and at 1 if the number of 1s is odd. accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. if the mark parity is used, the parity generator of the transmitter drives the parity bit at 1 for all characters. the receiver parity checker reports an error if the parity bit is sampled at 0.if the space parity is used, the parity generator of the transmitter drives the parity bit at 0 for all characters. the receiver parity checker reports an error if the parity bit is sampled at 1. if parity is disabled, the transmitter does not generate any parity bit and the receiver does not report any parity error. table 78 shows an example of the parity bit for the character 0x41 (character ascii ?a?) depending on the configuration of the usart. because there are two bits at 1, 1 bit is added when a parity is odd, or 0 is added when a parity is even. i when the receiver detects a parity error, it sets the pare (parity error) bit in the channel sta- tus register (us_csr). the pare bit can be cleared by writing the control register (us_cr) with the rststa bit at 1. figure 182 illustrates the parity bit status setting and clearing. figure 182. parity error multi-drop mode if the par field in the mode register (us_mr) is programmed to the value 0x3, the usart runs in multi-drop mode. this mode differentiates the data characters and the address charac- ters. data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit at 1. if the usart is configured in multi-drop mode, the receiver sets the pare parity error bit when the parity bit is high and the transmitter is able to send a character with the parity bit high when the control register is written with the senda bit at 1. table 78. parity bit examples character hexa binary parity bit paritymode a 0x41 0100 0001 1 odd a 0x41 0100 0001 0 even a 0x41 0100 0001 1 mark a 0x41 0100 0001 0 space a 0x41 0100 0001 none none d0 d1 d2 d3 d4 d5 d6 d7 rxd start bit bad parity bit stop bit baud rate clock write us_cr pare rxrdy rststa = 1
409 AT91RM9200 1768b?atarm?08/03 to handle parity error, the pare bit is cleared when the control register is written with the bit rststa at 1. the transmitter sends an address byte (parity bi t set) when senda is written to us_cr. in this case, the next byte written to us_thr is transmitted as an address. any character written in us_thr without having written the command senda is transmitted normally with the parity at 0. transmitter timeguard the timeguard feature enables the usart interface with slow remote devices. the timeguard function enables the transmitter to insert an idle state on the txd line between two characters. this idle state actually acts as a long stop bit. the duration of the idle state is programmed in the tg field of the transmitter timeguard reg- ister (us_ttgr). when this field is programmed at zero no timeguard is generated. otherwise, the transmitter holds a high level on txd after each transmitted byte during the number of bit periods programmed in tg in addition to the number of stop bits. as illustrated in figure 183, the behavior of txrdy and txempty status bits is modified by the programming of a timeguard. txrdy rises only when the start bit of the next character is sent, and thus remains at 0 during the timeguard transmission if a character has been written in us_thr. txempty remains low until the timeguard transmission is completed as the time- guard is part of the current character being transmitted. figure 183. timeguard operations table 79 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the baud rate. d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock start bit tg = 4 write us_thr d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit txrdy txempty tg = 4 table 79. maximum timeguard length depending on baud rate baud rate bit time timeguard bit/sec s ms 1 200 833 212.50 9 600 104 26.56 14400 69.4 17.71 19200 52.1 13.28 28800 34.7 8.85 33400 29.9 7.63
410 AT91RM9200 1768b?atarm?08/03 receiver time-out the receiver time-out provides support in handling variable-length frames. this feature detects an idle condition on the rxd line. when a time-out is detected, the bit timeout in the channel status register (us_csr) rises and can generate an interrupt, thus indicating to the driver an end of frame. the time-out delay period (during which the receiver waits for a new character) is programmed in the to field of the receiver time-out register (us_rtor). if the to field is programmed at 0, the receiver time-out is disabled and no time-out is detected. the timeout bit in us_csr remains at 0. otherwise, the receiver loads a 16-bit counter with the value pro- grammed in to. this counter is decremented at each bit period and reloaded each time a new character is received. if the counter reaches 0, the timeout bit in the status register rises. the user can either: obtain an interrupt when a time-out is detected after having received at least one character. this is performed by writing the control register (us_cr) with the sttto (start time-out) bit at 1. obtain a periodic interrupt while no character is received. this is performed by writing us_cr with the retto (reload and start time-out) bit at 1. if sttto is performed, the counter clock is stopped until a first character is received. the idle state on rxd before the start of the frame does not provide a time out. this prevents having to obtain a periodic interrupt and enables a wait of the end of frame when the idle state on rxd is detected. if retto is performed, the counter starts counting down immediately from the value to. this enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. figure 184 shows the block diagram of the receiver time out feature. figure 184. receiver time-out block diagram 56000 17.9 4.55 57600 17.4 4.43 115200 8.7 2.21 table 79. maximum timeguard length depending on baud rate (continued) baud rate bit time timeguard 16-bit time-out counter 0 to timeout baud rate clock = character received retto load clock 16-bit value sttto dq 1 clear
411 AT91RM9200 1768b?atarm?08/03 table 80 gives the maximum time-out period for some standard baud rates.t framing error the receiver is capable of detecting framing errors. a framing error happens when the stop bit of a received character is detected at level 0. this can occur if the receiver and the transmitter are fully desynchronized. a framing error is reported on the frame bit of the channel status register (us_csr). the frame bit is asserted in the middle of the stop bit as soon as the framing error is detected. it is cleared by writing the control register (us_cr) with the rststa bit at 1. figure 185. framing error status transmit break the user can request the transmitter to generate a break condition on the txd line. a break condition drives the txd line low during at least one complete character. it appears the same as a 0x00 character sent with the parity and the stop bits at 0. however, the transmitter holds the txd line at least during one character until the user requests the break condition to be removed. table 80. maximum time-out period baud rate bit time time -out bit/sec s ms 600 1 667 109 225 1 200 833 54 613 2 400 417 27 306 4 800 208 13 653 9 600 104 6 827 14400 69 4 551 19200 52 3 413 28800 35 2 276 33400 30 1 962 56000 18 1 170 57600 17 1 138 200000 5 328 d0 d1 d2 d3 d4 d5 d6 d7 rxd start bit parity bit stop bit baud rate clock write us_cr frame rxrdy rststa = 1
412 AT91RM9200 1768b?atarm?08/03 a break is transmitted by writing the control register (us_cr) with the sttbrk bit at 1. this can be performed at any time, either while the transmitter is empty (no character in either the shift register or in us_thr) or when a character is being transmitted. if a break is requested while a character is being shifted out, the char acter is first completed before the txd line is held low. once sttbrk command is requested further sttbrk commands are ignored until the end of the break is completed. the break condition is removed by writing us_cr with the stpbrk bit at 1. if the stpbrk is requested before the end of the minimum break duration (one character, including start, data, parity and stop bits), the transmitter ensures that the break condition completes. the transmitter considers the break as though it is a character, i.e. the sttbrk and stpbrk commands are taken into account only if the txrdy bit in us_csr is at 1 and the start of the break condition clears the txrdy and txempty bits as if a character is processed. writing us_cr with the both sttbrk and stpbrk bits at 1 can lead to an unpredictable result. all stpbrk commands requested without a previous sttbrk command are ignored. a byte written into the transmit holding register while a break is pending, but not started, is ignored. after the break condition, the transmitter returns the txd line to 1 for a minimum of 12 bit times. thus, the transmitter ensures that the remote receiver detects correctly the end of break and the start of the next character. if the timeguard is programmed with a value higher than 12, the txd line is held high for the timeguard period. after holding the txd line for this period, the transmitter resumes normal operations. figure 186 illustrates the effect of both the start break (sttbrk) and stop break (stp brk) commands on the txd line. figure 186. break transmission receive break the receiver detects a break condition when all data, parity and stop bits are low. this corre- sponds to detecting a framing error with data at 0x00, but frame remains low. when the low stop bit is detected, the receiver asserts the rxbrk bit in us_csr. this bit may be cleared by writing the control register (us_cr) with the bit rststa at 1. an end of receive break is detected by a high level for at least 2/16 of a bit period in asynchro- nous operating mode or one sample at high level in synchronous operating mode. the end of break detection also asserts the rxbrk bit. d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock write us_cr txrdy txempty stpbrk = 1 sttbrk = 1 break transmission end of break
413 AT91RM9200 1768b?atarm?08/03 hardware handshaking the usart features a hardware handshaking out-of-band flow control. the rts and cts pins are used to connect with the remote device, as shown in figure 187. figure 187. connection with a remote device for hardware handshaking setting the usart to operate with hardware handshaking is performed by writing the usart_mode field in the mode register (us_mr) to the value 0x2. the usart behavior when hardware handshaking is enabled is the same as the behavior in standard synchronous or asynchronous mode, except that the receiver drives the rts pin as described below and the level on the cts pin modifies the behavior of the transmitter as described below. using this mode requires using the pdc channel for reception. the transmit- ter can handle hardware handshaking in any case. figure 188 shows how the receiver operates if hardware handshaking is enabled. the rts pin is driven high if the receiver is disabled and if the status rxbuff (receive buffer full) coming from the pdc channel is high. normally, the remote device does not start transmitting while its cts pin (driven by rts) is high. as soon as the receiver is enabled, the rts falls, indicating to the remote device that it can start transmitting. defining a new buffer to the pdc clears the status bit rxbuff and, as a result, asserts the pin rts low. figure 188. receiver behavior when operating with hardware handshaking figure 189 shows how the transmitter operates if hardware handshaking is enabled. the cts pin disables the transmitter. if a character is being processing, the transmitter is disabled only after the completion of the current character and transmission of the next character happens as soon as the pin cts falls. figure 189. transmitter behavior when operating with hardware handshaking usart txd cts remote device rxd txd rxd rts rts cts rts rxbuff write us_cr rxen = 1 rxd rxdis = 1 cts txd
414 AT91RM9200 1768b?atarm?08/03 iso7816 mode the usart features an iso7816-compatible operating mode. this mode permits interfacing with smart cards and security access modules (sam) communicating through an iso7816 link. both t = 0 and t = 1 protocols defined by the iso7816 specification are supported. setting the usart in iso7816 mode is performed by writing the usart_mode field in the mode register (us_mr) to the value 0x4 for protocol t = 0 and to the value 0x5 for protocol t = 1. iso7816 mode overview the iso7816 is a half duplex communication on only one bidirectional line. the baud rate is determined by a division of the clock provided to the remote device (see ?baud rate genera- tor? on page 400). the usart connects to a smart card. as shown in figure 190. the txd line becomes bidirec- tional and the baud rate generator feeds the iso7816 clock on the sck pin. as the txd pin becomes bidirectional, its output remains driven by the output of the transmitter but only when the transmitter is active while its input is di rected to the input of the receiver. the usart is considered as the master of the communication as it generates the clock. figure 190. connection of a smart card to the usart when operating in iso7816, either in t = 0 or t = 1 modes, the character format is fixed. the configuration is 8 data bits, even parity and 1 or 2 stop bits, regardless of the values pro- grammed in the chrl, mode9, par and chmode fields. msbf can be used to transmit lsb or msb first. the usart cannot operate concurrently in both receiver and transmitter modes as the com- munication is unidirectional at a time. it has to be configured according to the required mode by enabling or disabling either the receiver or the transmitter as desired. enabling both the receiver and the transmitter at the same time in iso7816 mode may lead to unpredictable results. the iso7816 specification defines an inverse transmission format. data bits of the character must be transmitted on the i/o line at their negative value. the usart does not support this format and the user has to perform an exclusive or on the data before writing it in the trans- mit holding register (us_thr) or after reading it in the receive holding register (us_rhr). protocol t = 0 in t = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one guard time, which lasts two bit times. the transmitter shifts out the bits and does not drive the i/o line during the guard time. if no parity error is detected, the i/o line remains at 1 during the guard time and the transmitter can continue with the transmission of the next character, as shown in figure 191. if a parity error is detected by the receiver, it drives the i/o line at 0 during the guard time, as shown in figure 192. this error bit is also named nack, for non acknowledge. in this case, the character lasts 1 bit time more, as the guard time length is the same and is added to the error bit time which lasts 1 bit time. smart card sck clk txd i/o usart
415 AT91RM9200 1768b?atarm?08/03 when the usart is the receiver and it detects an error, it does not load the erroneous charac- ter in the receive holding register (us_rhr). it appropriately sets the pare bit in the status register (us_sr) so that the software can handle the error. figure 191. t = 0 protocol without parity error figure 192. t = 0 protocol with parity error receive error counter the usart receiver also records the total number of errors. this can be read in the number of error (us_ner) register. the nb_error s field can record up to 255 errors. reading us_ner automatically clears the nb_errors field. receive nack inhibit the usart can also be configured to inhibit an error. this can be achieved by setting the inack bit in the mode register (us_mr). if inack is at 1, no error signal is driven on the i/o line even if a parity bit is detected, but the inac k bit is set in the status register (us_sr). the inack bit can be cleared by writing the control register (us_cr) with the rstnack bit at 1. moreover, if inack is set, the erroneous received character is stored in the receive holding register, as if no error occurred. however, the rxrdy bit does not raise. transmit character repetition when the usart is transmitting a character and gets a nack, it can automatically repeat the character before moving on to the next one. repetition is enabled by writing the max_iteration field in the mode register (us_mr) at a value higher than 0. each charac- ter can be transmitted up to eight times; the first transmission plus seven repetitions. if max_iteration does not equal zero, the usart repeats the character as many times as the value loaded in max_iteration. when the usart repetition number reaches max_iteration, the iteration bit is set in the channel status register (us_csr). if the repetition of the character is acknowledged by the receiver, the repetitions are stopped and the iteration counter is cleared. the iteration bit in us_csr can be cleared by writing the control register with the rsit bit at 1. disable successive receive nack the receiver can limit the number of successive nacks sent back to the remote transmitter. this is programmed by setting the bit dsnack in the mode register (us_mr). the maximum number of nack transmitted is programmed in the max_iteration field. as soon as d0 d1 d2 d3 d4 d5 d6 d7 rxd parity bit baud rate clock start bit guard time 1 next start bit guard time 2 d0 d1 d2 d3 d4 d5 d6 d7 i/o parity bit baud rate clock start bit guard time 1 start bit guard time 2 d0 d1 error repetition
416 AT91RM9200 1768b?atarm?08/03 max_iteration is reached, the character is considered as correct, an acknowledge is sent on the line and the iteration bit in the channel status register is set. protocol t = 1 when operating in iso7816 protocol t = 1, the transmission is similar to an asynchronous for- mat with only one stop bit. the parity is generated when transmitting and checked when receiving. parity error detection sets the pare bit in the channel status register (us_csr). irda mode the usart features an irda mode supplying half-duplex point-to-point wireless communica- tion. it embeds the modulator and demodulator wh ich allows a glueles s connection to the infrared transceivers, as shown in figure 193. the modulator and demodulator are compliant with the irda specification version 1.1 and support data transfer speeds ranging from 2,4 kbps to 115,2 kbps. the usart irda mode is enabled by setting t he usart_mode field in the mode register (us_mr) to the value 0x8. the irda filter register (us_if) allows configuring the demodula- tor filter. the usart transmitter and receiver operate in a normal asynchronous mode and all parameters are accessible. note that the modulator and the demodulator are activated. figure 193. connection to irda transceivers the receiver and the transmitter must be enabled or disabled according to the direction of the transmission to be managed. irda modulation for baud rates up to and including 115.2 kbits/sec, the rzi modulation scheme is used. "0" is represented by a light pulse of 3/16th of a bit time. some examples of signal pulse duration are shown in table 81.. figure 194 shows an example of character transmission. irda transceivers rxd rx txd tx usart demodulator modulator receiver transmitter table 81. irda pulse duration baud rate pulse duration (3/16) 2.4 kb/s 78.13 s 9.6 kb/s 19.53 s 19.2 kb/s 9.77 s 38.4 kb/s 4.88 s 57.6 kb/s 3.26 s 115.2 kb/s 1.63 s
417 AT91RM9200 1768b?atarm?08/03 figure 194. irda modulation irda baud rate table 82 gives some examples of cd values, baud rate error and pulse duration. note that the requirement on the maximum acceptable error of +/- 1.87% must be met. bit period bit period 3 16 start bit data bits start bit 0 0 0 0 0 1 1 1 1 1 transmitter output txd table 82. irda baud rate error peripheral clock baud rate cd baud rate error pulse time 3 686 400 115 200 2 0.00% 1.63 20 000 000 115 200 11 1.38% 1.63 32 768 000 115 200 18 1.25% 1.63 40 000 000 115 200 22 1.38% 1.63 3 686 400 57 600 4 0.00% 3.26 20 000 000 57 600 22 1.38% 3.26 32 768 000 57 600 36 1.25% 3.26 40 000 000 57 600 43 0.93% 3.26 3 686 400 38 400 6 0.00% 4.88 20 000 000 38 400 33 1.38% 4.88 32 768 000 38 400 53 0.63% 4.88 40 000 000 38 400 65 0.16% 4.88 3 686 400 19 200 12 0.00% 9.77 20 000 000 19 200 65 0.16% 9.77 32 768 000 19 200 107 0.31% 9.77 40 000 000 19 200 130 0.16% 9.77 3 686 400 9 600 24 0.00% 19.53 20 000 000 9 600 130 0.16% 19.53 32 768 000 9 600 213 0.16% 19.53 40 000 000 9 600 260 0.16% 19.53 3 686 400 2 400 96 0.00% 78.13 20 000 000 2 400 521 0.03% 78.13 32 768 000 2 400 853 0.04% 78.13
418 AT91RM9200 1768b?atarm?08/03 irda demodulator the demodulator is based on the irda receive filter comprised of an 8-bit down counter which is loaded with the value programmed in us_i f. when a falling edge is detected on the rxd pin, the filter counter starts counting down at the master clock (mck) speed. if a rising edge is detected on the rxd pin, the counter stops and is reloaded with us_if. if no rising edge is detected when the counter reaches 0, the input of the receiver is driven low during one bit time. figure 195 illustrates the operations of the irda demodulator. figure 195. irda demodulator operations as the irda mode uses the same logic as the iso7816, note that the fi_di_ratio field in us_fidi must be set to a value higher than 0 in order to assure irda communications operate correctly. mck rxd receiver input pulse rejected 65432 6 1 driven low during 16 baud rate clock cycles 65432 0 pulse accepted counter value
419 AT91RM9200 1768b?atarm?08/03 rs485 mode the usart features the rs485 mode to enable line driver control. while operating in rs485 mode, the usart behaves as though in asynchronous or synchronous mode and configura- tion of all the parameters are possible. the difference is that the rts pin is driven low when the transmitter is operating. the behavior of the rts pin is controlled by the txempty bit. a typical connection of the usart to a rs485 bus is shown in figure 196. figure 196. typical connection to a rs485 bus. the usart is set in rs485 mode by programming the usart_mode field in the mode reg- ister (us_mr) to the value 0x1. the rts pin is at a level inverse of the txempty bit. significantly, the rts pin remains low when a timeguard is programmed so that the line can remain driven after the last character completion. figure 197 gives an example of the rts waveform during a character transmis- sion when the timeguard is enabled. figure 197. example of rts drive with timeguard usart rts txd rxd differential bus d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock tg = 4 write us_thr txrdy txempty rts
420 AT91RM9200 1768b?atarm?08/03 modem mode the usart features modem mode, which enables control of the signals: dtr (data terminal ready), dsr (data set ready), rts (request to send), cts (clear to send), dcd (data carrier detect) and ri (ring indicator). while operating in modem mode, the usart behaves as a dte (data terminal equipment) as it drives dtr and rts and can detect level change on dsr, dcd, cts and ri. setting the usart in modem mode is performed by writing the usart_mode field in the mode register (us_mr) to the value 0x3. while operating in modem mode the usart behaves as though in asynchronous mode and all the parameter configurations are available. table 83 gives the correspondence of the usart signals with modem connection standards. the control of the rts and dtr output pins is performed by witting the control register (us_cr) with the rtsdis, rtsen, dtrdis and dt ren bits respectively at 1. the disable command forces the corresponding pin to its inactive level, i.e. high. the enable commands force the corresponding pin to its active level, i.e. low. the level changes are detected on the ri, dsr, dcd and cts pins. if an input change is detected, the riic, dsric, dcdic and ctsic bits in the channel status register (us_csr) are set respectively and can trigger an inte rrupt. the status is automatically cleared when us_csr is read. furthermore, the cts automatically disables the transmitter when it is detected at its inactive state. if a character is being transmitted when the cts rises, the char- acter transmission is completed before the transmitter is actually disabled. test modes the usart can be programmed to operate in three different test modes. the internal loop- back capability allows on-board diagnostics. in the loopback mode the usart interface pins are disconnected or not and reconfigured for loopback internally or externally. normal mode as a reminder, the normal mode simply connects the rxd pin on the receiver input and the transmitter output on the txd pin. figure 198. normal mode configuration table 83. circuit references usart pin v24 ccitt direction txd 2 103 from terminal to modem rts 4 105 from terminal to modem dtr 20 108.2 from terminal to modem rxd 3 104 from modem to terminal cts 5 106 from terminal to modem dsr 6 107 from terminal to modem dcd 8 109 from terminal to modem ri 22 125 from terminal to modem receiver transmitter rxd txd
421 AT91RM9200 1768b?atarm?08/03 automatic echo automatic echo mode allows bit-by-bit retransmission. when a bit is received on the rxd pin, it is sent to the txd pin, as shown in figure 199. programming the transmitter has no effect on the txd pin. the rxd pin is still connected to the receiver input, thus the receiver remains active. figure 199. automatic echo local loopback the local loopback mode connects the output of the transmitter directly to the input of the receiver, as shown in figure 200. the txd and rxd pins are not used. the rxd pin has no effect on the receiver and the txd pin is continuously driven high, as in idle state. figure 200. local loopback remote loopback remote loopback mode directly connects the rxd pin to the txd pin, as shown in figure 201. the transmitter and the receiver are disabled and have no effect. this mode allows bit-by-bit retransmission. figure 201. remote loopback receiver transmitter rxd txd receiver transmitter rxd txd 1 receiver transmitter rxd txd 1
422 AT91RM9200 1768b?atarm?08/03 usart user interface table 84. usart memory map offset register name access reset state 0x0000 control register us_cr write-only ? 0x0004 mode register us_mr read/write ? 0x0008 interrupt enable register us_ier write-only ? 0x000c interrupt disable register us_idr write-only ? 0x0010 interrupt mask register us_imr read-only 0 0x0014 channel status register us_csr read-only ? 0x0018 receiver holding register us_rhr read-only 0 0x001c transmitter holding register us_thr write-only ? 0x0020 baud rate generator register us_brgr read/write 0 0x0024 receiver time-out register us_rtor read/write 0 0x0028 transmitter timeguard register us_ttgr read/write 0 0x2c to 0x3c reserved ??? 0x0040 fi di ratio register us_fidi read/write 0x174 0x0044 number of errors register us_ner read-only ? 0x0048 reserved ? ? ? 0x004c irda filter register us_if read/write 0 0x5c to 0xfc reserved ??? 0x100 to 0x128 reserved for pdc registers ? ? ?
423 AT91RM9200 1768b?atarm?08/03 usart control register name: us_cr access type: write-only rstrx: reset receiver 0 = no effect. 1 = resets the receiver. rsttx: reset transmitter 0 = no effect. 1 = resets the transmitter. rxen: receiver enable 0 = no effect. 1 = enables the receiver, if rxdis is 0. rxdis: receiver disable 0 = no effect. 1 = disables the receiver. txen: transmitter enable 0 = no effect. 1 = enables the transmitter if txdis is 0. txdis: transmitter disable 0 = no effect. 1 = disables the transmitter. rststa: reset status bits 0 = no effect. 1 = resets the status bits pare, frame, ovre and rxbrk in the us_csr. sttbrk: start break 0 = no effect. 1 = starts transmission of a break after the characters present in us_thr and the transmit shift register have been trans- mitted. no effect if a break is already being transmitted. stpbrk: stop break 0 = no effect. 1 = stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit peri- ods. no effect if no break is being transmitted. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????rtsdisrtsendtrdisdtren 15 14 13 12 11 10 9 8 retto rstnack rstit senda sttto stpbrk sttbrk rststa 76543210 txdis txen rxdis rxen rsttx rstrx ? ?
424 AT91RM9200 1768b?atarm?08/03 sttto: start time-out 0 = no effect 1 = starts waiting for a character before clocking the time-out counter. senda: send address 0 = no effect. 1 = in multi-drop mode only, the next character written to the us_thr is sent with the address bit set. rstit: reset iterations 0 = no effect. 1 = resets iteration in us_csr. no effect if the iso7816 is not enabled. rstnack: reset non acknowledge 0 = no effect 1 = resets nack in us_csr. retto: rearm time-out 0 = no effect 1 = restart time-out dtren: data terminal ready enable 0 = no effect. 1 = drives the pin dtr at 0. dtrdis: data terminal ready disable 0 = no effect. 1 = drives the pin dtr to 1. rtsen: request to send enable 0 = no effect. 1 = drives the pin rts to 0. rtsdis: request to send disable 0 = no effect. 1 = drives the pin rts to 1.
425 AT91RM9200 1768b?atarm?08/03 usart mode register name: us_mr access type: read/write usart_mode usclks: clock selection chrl: character length. 31 30 29 28 27 26 25 24 ? ? ? filter ? max_iteration 23 22 21 20 19 18 17 16 ? ? dsnack inack over clko mode9 msbf 15 14 13 12 11 10 9 8 chmode nbstop par sync 76543210 chrl usclks usart_mode usart_mode mode of the usart 0000normal 0001rs485 0010hardware handshaking 0011modem 0100is07816 protocol: t = 0 0101reserved 0110is07816 protocol: t = 1 0111reserved 1000irda 11xxreserved usclks selected clock 00mck 01mck / div 10reserved 11sck chrl character length 0 0 5 bits 0 1 6 bits 1 0 7 bits 1 1 8 bits
426 AT91RM9200 1768b?atarm?08/03 sync: synchronous mode select 0 = usart operates in asynchronous mode. 1 = usart operates in synchronous mode par: parity type nbstop: number of stop bits chmode: channel mode msbf: bit order 0 = least significant bit is sent/received first. 1 = most significant bit is sent/received first. mode9: 9-bit character length 0 = chrl defines character length. 1 = 9-bit character length. cklo: clock output select 0 = the usart does not drive the sck pin. 1 = the usart drives the sck pin if usclks does not select the external clock sck. over: oversampling mode 0 = 16x oversampling. 1 = 8x oversampling. par parity type 0 0 0 even parity 001odd parity 0 1 0 parity forced to 0 (space) 0 1 1 parity forced to 1 (mark) 10xno parity 1 1 x multi-drop mode nbstop asynchronous (sync = 0) synchronous (sync = 1) 0 0 1 stop bit 1 stop bit 0 1 1.5 stop bits reserved 1 0 2 stop bits 2 stop bits 1 1 reserved reserved chmode mode description 0 0 normal mode 0 1 automatic echo. receiver input is connected to the txd pin. 1 0 local loopback. transmitter output is connected to the receiver input.. 1 1 remote loopback. rxd pin is internally connected to the txd pin.
427 AT91RM9200 1768b?atarm?08/03 inack: inhibit non acknowledge 0 = the nack is generated. 1 = the nack is not generated. dsnack: disable successive nack 0 = nack is sent on the iso line as soon as a parity error occurs in the received character (unless inack is set). 1 = successive parity errors are counted up to the value specified in the max_iteration field. these parity errors gener- ate a nack on the iso line. as soon as this value is reached, no additional nack is sent on the iso line. the flag iteration is asserted. max_iteration defines the maximum number of iterations in mode iso7816, protocol t = 0. filter: infrared receive line filter 0 = the usart does not filter the receive line. 1 = the usart filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority).
428 AT91RM9200 1768b?atarm?08/03 usart interrupt enable register name: us_ier access type: write-only rxrdy: rxrdy interrupt enable txrdy: txrdy interrupt enable rxbrk: receiver break interrupt enable endrx: end of receive transfer interrupt enable endtx: end of transmit interrupt enable ovre: overrun error interrupt enable frame: framing error interrupt enable pare: parity error interrupt enable timeout: time-out interrupt enable txempty: txempty interrupt enable iteration: iteration interrupt enable txbufe: buffer empty interrupt enable rxbuff: buffer full interrupt enable nack: non acknowledge interrupt enable riic: ring indicator input change enable dsric: data set ready input change enable dcdic: data carrier detect input change interrupt enable ctsic: clear to send input change interrupt enable 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ? ? ? ? ctsic dcdic dsric riic 15 14 13 12 11 10 9 8 ? ? nack rxbuff txbufe iteration txempty timeout 76543210 pare frame ovre endtx endrx rxbrk txrdy rxrdy
429 AT91RM9200 1768b?atarm?08/03 usart interrupt disable register name: us_idr access type: write-only rxrdy: rxrdy interrupt disable txrdy: txrdy interrupt disable rxbrk: receiver break interrupt disable endrx: end of receive transfer interrupt disable endtx: end of transmit interrupt disable ovre: overrun error interrupt disable frame: framing error interrupt disable pare: parity error interrupt disable timeout: time-out interrupt disable txempty: txempty interrupt disable iteration: iteration interrupt disable txbufe: buffer empty interrupt disable rxbuff: buffer full interrupt disable nack: non acknowledge interrupt disable riic: ring indicator input change disable dsric: data set ready input change disable dcdic: data carrier detect i nput change interrupt disable ctsic: clear to send input change interrupt disable 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ? ? ? ? ctsic dcdic dsric riic 15 14 13 12 11 10 9 8 ? ? nack rxbuff txbufe iteration txempty timeout 76543210 pare frame ovre endtx endrx rxbrk txrdy rxrdy
430 AT91RM9200 1768b?atarm?08/03 usart interrupt mask register name: us_imr access type: read-only rxrdy: rxrdy interrupt mask txrdy: txrdy interrupt mask rxbrk: receiver break interrupt mask endrx: end of receive transfer interrupt mask endtx: end of transmit interrupt mask ovre: overrun error interrupt mask frame: framing error interrupt mask pare: parity error interrupt mask timeout: time-out interrupt mask txempty: txempty interrupt mask iteration: iteration interrupt mask txbufe: buffer empty interrupt mask rxbuff: buffer full interrupt mask nack: non acknowledge interrupt mask riic: ring indicator input change mask dsric: data set ready input change mask dcdic: data carrier detect input change interrupt mask ctsic: clear to send input change interrupt mask 0 = the corresponding interrupt is disabled. 1 = the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ? ? ? ? ctsic dcdic dsric riic 15 14 13 12 11 10 9 8 ? ? nack rxbuff txbufe iteration txempty timeout 76543210 pare frame ovre endtx endrx rxbrk txrdy rxrdy
431 AT91RM9200 1768b?atarm?08/03 usart channel status register name: us_csr access type: read-only rxrdy: receiver ready 0 = no complete character has been received since the last read of us_rhr or the receiver is disabled. if characters were being received when the receiver was disabled, rxrdy changes to 1 when the receiver is enabled. 1 = at least one complete character has been received and us_rhr has not yet been read. txrdy: transmitter ready 0 = a character is in the us_thr waiting to be transferred to the transmit shift register, or an sttbrk command has been requested, or the transmitter is disabled. as soon as the transmitter is enabled, txrdy becomes 1. 1 = there is no character in the us_thr. rxbrk: break received/end of break 0 = no break received or end of break detected since the last rststa. 1 = break received or end of break detected since the last rststa. endrx: end of receiver transfer 0 = the end of transfer signal from the receive pdc channel is inactive. 1 = the end of transfer signal from the receive pdc channel is active. endtx: end of transmitter transfer 0 = the end of transfer signal from the transmit pdc channel is inactive. 1 = the end of transfer signal from the transmit pdc channel is active. ovre: overrun error 0 = no overrun error has occurred since since the last rststa. 1 = at least one overrun error has occurred since the last rststa. frame: framing error 0 = no stop bit has been detected low since the last rststa. 1 = at least one stop bit has been detected low since the last rststa. pare: parity error 0 = no parity error has been detected since the last rststa. 1 = at least one parity error has been detected since the last rststa. timeout: receiver time-out 0 = there has not been a time-out since the last start time-out command or the time-out register is 0. 1 = there has been a time-out since the last start time-out command. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 cts dcd dsr ri ctsic dcdic dsric riic 15 14 13 12 11 10 9 8 ? ? nack rxbuff txbufe iteration txempty timeout 76543210 pare frame ovre endtx endrx rxbrk txrdy rxrdy
432 AT91RM9200 1768b?atarm?08/03 txempty: transmitter empty 0 = there are characters in either us_thr or the transmit shift register, or the transmitter is disabled. 1 = there is at least one character in either us_thr or the transmit shift register. iteration: max number of repetitions reached 0 = maximum number of repetitions has not been reached since the last rsit. 1 = maximum number of repetitions has been reached since the last rsit. txbufe: transmission buffer empty 0 = the signal buffer empty from the transmit pdc channel is inactive. 1 = the signal buffer empty from the transmit pdc channel is active. rxbuff: reception buffer full 0 = the signal buffer full from the receive pdc channel is inactive. 1 = the signal buffer full from the receive pdc channel is active. nack: non acknowledge 0 = no non acknowledge has not been detected since the last rstnack. 1 = at least one non acknowledge has been detected since the last rstnack. riic: ring indicator input change flag 0 = no input change has been detected on the ri pin since the last read of us_csr. 1 = at least one input change has been detected on the ri pin since the last read of us_csr. dsric: data set ready input change flag 0 = no input change has been detected on the dsr pin since the last read of us_csr. 1 = at least one input change has been detected on the dsr pin since the last read of us_csr. dcdic: data carrier detect input change flag 0 = no input change has been detected on the dcd pin since the last read of us_csr. 1 = at least one input change has been detected on the dcd pin since the last read of us_csr. ctsic: clear to send input change flag 0 = no input change has been detected on the cts pin since the last read of us_csr. 1 = at least one input change has been detected on the cts pin since the last read of us_csr. ri: image of ri input 0 = ri is at 0. 1 = ri is at 1. dsr: image of dsr input 0 = dsr is at 0 1 = dsr is at 1. dcd: image of dcd input 0 = dcd is at 0. 1 = dcd is at 1. cts: image of cts input 0 = cts is at 0. 1 = cts is at 1.
433 AT91RM9200 1768b?atarm?08/03 usart receive holding register name: us_rhr access type: read-only rxchr: received character last character received if rxrdy is set. usart transmit holding register name: us_thr access type: write-only txchr: character to be transmitted next character to be transmitted after the current character if txrdy is not set. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????rxchr 76543210 rxchr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????txchr 76543210 txchr
434 AT91RM9200 1768b?atarm?08/03 usart baud rate ge nerator register name: us_brgr access type: read/write cd: clock divider 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 cd 76543210 cd cd usart_mode iso7816 usart_mode = iso7816 sync = 0 sync = 1 over = 0 over = 1 0 baud rate clock disabled 1 to 65535 baud rate = selected clock/16/cd baud rate = selected clock/8/cd baud rate = selected clock /cd baud rate = selected clock/cd/fi_di_ratio
435 AT91RM9200 1768b?atarm?08/03 usart receiver ti me-out register name: us_rtor access type: read/write to: time-out value 0: the receiver time-out is disabled. 1 - 65535: the receiver time-out is enabled and the time-out delay is to x bit period. usart transmitter timeguard register name: us_ttgr access type: read/write tg: timeguard value 0: the transmitter timeguard is disabled. 1 - 255: the transmitter timeguard is enabled and the timeguard delay is tg x bit period. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 to 76543210 to 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 tg
436 AT91RM9200 1768b?atarm?08/03 usart fi di ratio register name: us_fidi access type: read/write reset value: 0x174 fi_di_ratio: fi over di ratio value 0: if iso7816 mode is selected, the baud rate generator generates no signal. 1-2047: if iso7816 mode is selected, the baud rate is the clock provided on sck divided by fi_di_ratio. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????? fi_di_ratio 76543210 fi_di_ratio
437 AT91RM9200 1768b?atarm?08/03 usart number of errors register name: us_ner access type: read-only nb_errors: number of errors total number of errors that occurred during an iso7816 transfer. this register automatically clears when read. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 nb_errors
438 AT91RM9200 1768b?atarm?08/03 usart irda filter register name: us_if access type: read/write irda_filter: irda filter sets the filter of the irda demodulator. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 irda_filter
441 AT91RM9200 1768b?atarm?08/03 serial synchronous controller (ssc) overview the atmel synchronous serial controller (ssc) provides a synchronous communication link with external devices. it supports many serial synchronous communication protocols generally used in audio and telecom applications such as i2s, short frame sync, long frame sync, etc. the ssc contains an independent receiver and transmitter and a common clock divider. the receiver and the transmitter each interface with three signals: the td/rd signal for data, the tk/rk signal for the clock and the tf/rf signal for the frame sync. transfers contain up to 16 data of up to 32 bits. they can be programmed to start automatically or on different events detected on the frame sync signal. the ssc?s high-level of programmability and its two dedicated pdc channels of up to 32 bits permit a continuous high bit rate data transfer without processor intervention. featuring connection to two pdc channels, the ssc permits interfacing with low processor overhead to the following: codecs in master or slave mode dac through dedicated serial interface, particularly i2s magnetic card reader features of the ssc are: provides serial synchronous communication links used in audio and telecom applications contains an independent receiver and transmitter and a common clock divider interfaced with two pdc channels (dma access) to reduce processor overhead offers a configurable frame sync and data length receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal receiver and transmitter include a data signal, a clock signal and a frame synchronization signal
442 AT91RM9200 1768b?atarm?08/03 block diagram figure 202. block diagram application block diagram figure 203. application block diagram ssc interface pdc apb bridge mck asb apb pio tf tk td rf rk rd interrupt control ssc interrupt pmc interrupt management power management test management ssc serial audio os or rtos driver codec frame management line interface time slot management
443 AT91RM9200 1768b?atarm?08/03 pin name list product dependencies i/o lines the pins used for interfacing the compliant external devices may be multiplexed with pio lines. before using the ssc receiver, the pio controller must be configured to dedicate the ssc receiver i/o lines to the ssc peripheral mode. before using the ssc transmitter, the pio controller must be configured to dedicate the ssc transmitter i/o lines to the ssc peripheral mode. power management the ssc is not continuously clocked. the ssc interface may be clocked through the power management controller (pmc), therefore the programmer must first configure the pmc to enable the ssc clock. interrupt the ssc interface has an interrupt line connected to the advanced interrupt controller (aic). handling interrupts requires programming the aic before configuring the ssc. all ssc interrupts can be enabled/disabled configuring the ssc interrupt mask register. each pending and unmasked ssc interrupt will assert the ssc interrupt line. the ssc interrupt ser- vice routine can get the interrupt origin by reading the ssc interrupt status register. table 85. i/o lines description pin name pin description type rf receiver frame synchro input/output rk receiver clock input/output rd receiver data input tf transmitter frame synchro input/output tk transmitter clock input/output td transmitter data output
444 AT91RM9200 1768b?atarm?08/03 functional description this chapter contains the functional description of the following: ssc functional block, clock management, data format, start, transmitter, receiver and frame sync. the receiver and transmitter operate separately. however, they can work synchronously by programming the receiver to use the transmit clock and/or to start a data transfer when trans- mission starts. alternatively, this can be done by programming the transmitter to use the receive clock and/or to start a data transfer when reception starts. the transmitter and the receiver can be programmed to operate with the clock signals provided on either the tk or rk pins. this allows the ssc to support many slave-mode data transfers. the maximum clock speed allowed on the tk and rk pins is the master clock divided by 2. each level of the clock must be stable for at least two master clock periods. figure 204. ssc functional block diagram interrupt control aic user interface apb transmitter td tf tk clock output controller frame sync controller transmit clock controller transmit shift register start selector transmit sync holding register transmit holding register load shift rx clock tx clock tk input tf tx pdc rf rd rf rk clock output controller frame sync controller receive clock controller receive shift register start selector receive sync holding register receive holding register load shift tx clock rx clock rk input rf rx pdc receiver tf mck clock divider pdc
445 AT91RM9200 1768b?atarm?08/03 clock management the transmitter clock can be generated by: an external clock received on the tk i/o pad the receiver clock the internal clock divider the receiver clock can be generated by: an external clock received on the rk i/o pad the transmitter clock the internal clock divider furthermore, the transmitter block can generate an external clock on the tk i/o pad, and the receiver block can generate an external clock on the rk i/o pad. this allows the ssc to support many master and slave-mode data transfers. clock divider figure 205. divided clock block diagram the master clock divider is determined by the 12-bit field div counter and comparator (so its maximal value is 4095) in the clock mode register ssc_cmr, allowing a master clock divi- sion by up to 8190. the divided clock is provided to both the receiver and transmitter. when this field is programmed to 0, the clock divider is not used and remains inactive. when div is set to a value equal or greater to 1, the divided clock has a frequency of master clock divided by 2 times div. each level of the divided clock has a duration of the master clock multiplied by div. this ensures a 50% duty cycle for the divided clock regardless if the div value is even or odd. figure 206. divided clock generation table 86. bit rate maximum minimum mck / 2 mck / 8190 mck divided clock clock divider / 2 12-bit counter ssc_cmr master clock divided clock div = 1 master clock divided clock div = 3 divided clock frequency = mck/2 divided clock frequency = mck/6
446 AT91RM9200 1768b?atarm?08/03 transmitter clock management the transmitter clock is generated from the receiver clock or the divider clock or an external clock scanned on the tk i/o pad. the transmitter clock is selected by the cks field in ssc_tcmr (transmit clock mode register). transmit clock can be inverted independently by the cki bits in ssc_tcmr. the transmitter can also drive the tk i/o pad c ontinuously or be limited to the actual data transfer. the clock output is configured by the ssc_tcmr register. the transmit clock inver- sion (cki) bits have no effect on the clock outputs. programming the tcmr register to select tk pin (cks field) and at the same time continuous transmit clock (cko field) might lead to unpredictable results. figure 207. transmitter clock management receiver clock management the receiver clock is generated from the transmitt er clock or the divider clock or an external clock scanned on the rk i/o pad. the receive clock is selected by the cks field in ssc_rcmr (receive clock mode register). receive clocks can be inverted independently by the cki bits in ssc_rcmr. the receiver can also drive the rk i/o pad continuously or be limited to the actual data trans- fer. the clock output is configured by the ssc_rcmr register. the receive clock inversion (cki) bits have no effect on the clock outputs. programming the rcmr register to select rk pin (cks field) and at the same time continuous receive clock (cko field) might lead to unpredictable results. figure 208. receiver clock management receiver clock divider clock transmitter clock ssc_tcmr.cki ssc_tcmr.cks tk ssc_tcmr.cko 1 0 tk transmitter clock divider clock receiver clock ssc_rcmr.cki ssc_rcmr.cks rk ssc_rcmr.cko rk 1 0
447 AT91RM9200 1768b?atarm?08/03 transmitter operations a transmitted frame is triggered by a start event and can be followed by synchronization data before data transmission. the start event is configured by setting the transmit clock mode register (ssc_tcmr). see ?start? on page 448. the frame synchronization is configured setting the transmit frame mode register (ssc_tfmr). see ?frame sync? on page 450. to transmit data, the transmitter uses a shift register clocked by the transmitter clock signal and the start mode selected in the ssc_tcmr. data is written by the application to the ssc_thr register then transferred to the shift register according to the data format selected. when both the ssc_thr and the transmit shift register are empty, the status flag txempty is set in ssc_sr. when the transmit holding register is transferred in the transmit shift reg- ister, the status flag txrdy is set in ssc_sr and additional data can be loaded in the holding register. figure 209. transmitter block diagram transmit shift register start selector ssc_tshr ssc_thr transmitter clock td ssc_tfmr.fslen ssc_tfmr.datlen ssc_cr.txen ssc_cr.txdis ssc_tcmr.sttdly ssc_tfmr.fsden ssc_tfmr.datnb ssc_sr.txen 0 1 1 0 ssc_tfmr.datdef ssc_tfmr.msbf ssc_tcmr.sttdly ssc_tfmr.fsden rf tf
448 AT91RM9200 1768b?atarm?08/03 receiver operations a received frame is triggered by a start event and can be followed by synchronization data before data transmission. the start event is configured setting the receive clock mode register (ssc_rcmr). see ?start? on page 448. the frame synchronization is configured setting the receive frame mode register (ssc_rfmr). see ?frame sync? on page 450. the receiver uses a shift register clocked by the receiver clock signal and the start mode selected in the ssc_rcmr. the data is transferred from the shift register in function of data format selected. when the receiver shift register is full, the ssc transfers this data in the holding register, the status flag rxrdy is set in ssc_sr and the data can be read in the receiver holding register, if another transfer occurs before read the rhr register, the status flag overun is set in ssc_sr and the receiver shift register is transferred in the rhr register. figure 210. receiver block diagram start the transmitter and receiver can both be programmed to start their operations when an event occurs, respectively in the transmit start se lection (start) field of ssc_tcmr and in the receive start selection (start) field of ssc_rcmr. under the following conditions the start event is independently programmable: continuous. in this case, the transmission starts as soon as a word is written in ssc_thr and the reception starts as soon as the receiver is enabled. synchronously with the transmitter/receiver on detection of a falling/rising edge on tk/rk on detection of a low level/high level on tk/rk on detection of a level change or an edge on tk/rk a start can be programmed in the same manner on either side of the transmit/receive clock register (rcmr/tcmr). thus, the start could be on tf (transmit) or rf (receive). detection on tf/rf input/output is done through the field fsos of the transmit / receive frame mode register (tfmr/rfmr). receive shift register start selector ssc_rhr ssc_rshr receiver clock rd ssc_rfmr.fslen ssc_rfmr.datlen rf ssc_cr.rxen ssc_cr.rxdis ssc_sr.rxen ssc_rfmr.msbf ssc_rcmr.sttdly ssc_rfmr.datnb tf
449 AT91RM9200 1768b?atarm?08/03 generating a frame sync signal is not possible without generating it on its related output. figure 211. transmit start mode figure 212. receive pulse/edge start modes x tk tf (input) td (output) td (output) td (output) td (output) td (output) td (output) xbob1 x bo b1 bo b1 bo b1 bo b1 bo b1 bo b1 b1 bo x x x sttdly sttdly sttdly sttdly sttdly sttdly start = falling edge on tf start = rising edge on tf start = low level on tf start = high level on tf start = any edge on tf start = level change on tf rk rf (input) rd (input) rd (input) rd (input) rd (input) rd (input) rd (input) xbob1 x bo b1 bo b1 bo b1 bo b1 bo b1 bo b1 b1 bo x x x sttdly sttdly sttdly sttdly sttdly sttdly start = falling edge on rf start = rising edge on rf start = low level on rf start = high level on rf start = any edge on rf start = level change on rf x
450 AT91RM9200 1768b?atarm?08/03 frame sync the transmitter and receiver frame sync pins, tf and rf, can be programmed to generate different kinds of frame synchronization signals. the frame sync output selection (fsos) field in the receive frame mode register (ssc_rfmr) and in the transmit frame mode register (ssc_tfmr) are used to select the required waveform. programmable low or high levels during data transfer are supported. programmable high levels before the start of data transfers or toggling are also supported. if a pulse waveform is selected, the frame sync length (fslen) field in ssc_rfmr and ssc_tfmr programs the length of the pulse, from 1-bit time up to 16-bit time. the periodicity of the receive and transmit frame sync pulse output can be programmed through the period divider selection (period) field in ssc_rcmr and ssc_tcmr. frame sync data frame sync data transmits or receives a specific tag during the frame synchro signal. during the frame sync signal, the receiver can sample the rd line and store the data in the receive sync holding register and the transmitter can transfer transmit sync holding regis- ter in the shifter register. the data length to be sampled/shifted out during the frame sync signal is programmed by the fslen field in ssc_rfmr/ssc_tfmr. concerning the receive frame sync data operation, if the frame sync length is equal to or lower than the delay between the start event and the actual data reception, the data sampling operation is performed in the receive sync holding register through the receive shift register. the transmit frame sync operation is performed by the transmitter only if the bit frame sync data enable (fsden) in ssc_tfmr is set. if the frame sync length is equal to or lower than the delay between the start event and the ac tual data transmission, the normal transmission has priority and the data contained in the transmit sync holding register is transferred in the transmit register then shifted out. frame s y nc ed g e detection the frame sync edge detection is programmed by the fsedge field in ssc_rfmr/ssc_tfmr. this sets the corresponding flags rxsyn/txsyn in the ssc sta- tus register (ssc_sr) on frame synchro edge detection (signals rf/tf). data format the data framing format of both the transmitter and the receiver are largely programmable through the transmitter frame mode register (ssc_tfmr) and the receiver frame mode register (ssc_rfmr). in either case, the user can independently select: the event that starts the data transfer (start). the delay in number of bit periods between the start event and the first data bit ( sttdly ). the length of the data (datlen) the number of data to be transferred for each start event (datnb). the length of synchronization transferred for each start event (fslen). the bit sense: most or lowest significant bit first (msbf). additionally, the transmitter can be used to transfer synchronization and select the level driven on the td pin while not in data transfer operation. this is done respectively by the frame sync data enable (fsden) and by t he data default value (datdef) bits in ssc_tfmr.
451 AT91RM9200 1768b?atarm?08/03 figure 213. transmit and receive frame format in edge/pulse start modes note: 1. input on falling edge on tf/rf example. table 87. data frame registers transmitter receiver field length comment ssc_tfmr ssc_rfmr datlen up to 32 size of word ssc_tfmr ssc_rfmr datnb up to 16 number word transmitter in frame ssc_tfmr ssc_rfmr msbf 1 most significant bit in first ssc_tfmr ssc_rfmr fslen up to 16 size of synchro data register ssc_tfmr datdef 0 or 1 data default value ended ssc_tfmr fsden enable send ssc_tshr ssc_tcmr ssc_rcmr period up to 512 frame size ssc_tcmr ssc_rcmr sttdly up to 255 size of transmit start delay sync data default sttdly sync data ignored rd default data datlen data data data datlen data data default default ignored sync data sync data fslen tf/rf (1) start start from ssc_tshr from ssc_thr from ssc_thr from ssc_thr from ssc_thr to ssc_rhr to ssc_rhr to ssc_rshr td (if fsden = 0) td (if fsden = 1) datnb period fromdatdef fromdatdef from datdef from datdef
452 AT91RM9200 1768b?atarm?08/03 figure 214. transmit frame format in continuous mode note: 1. sttdly is set to 0. in this example, ssc_thr is loaded twice. the value of fsden has no effect on transmission. syncdata cannot be output in continuous mode. figure 215. receive frame format in continuous mode note: 1. sttdly is set to 0. loop mode the receiver can be programmed to receive trans missions from the transmitter. this is done by setting the loop mode (loop) bit in ssc_rfmr. in this case, rd is connected to td, rf is connected to tf and rk is connected to tk. interrupt most bits in ssc_sr have a corresponding bit in interrupt management registers. the ssc controller can be programmed to generate an interrupt when it detects an event. the interrupt is controlled by writing ssc_ier (interrupt enable register) and ssc_idr (interrupt disable register), which respectively enable and disable the corresponding interrupt by setting and clearing the corresponding bit in ssc_imr (interrupt mask register), which controls the generation of interrupts by asserting the ssc interrupt line connected to the aic. datlen data datlen data default start from ssc_thr from ssc_thr td start: 1. txempty set to 1 2. write to the ssc_thr data datlen data datlen start = enable receiver to ssc_rhr to ssc_rhr rd
453 AT91RM9200 1768b?atarm?08/03 figure 216. interrupt block diagram ssc application examples the ssc can support several serial communication modes used in audio or high speed serial links. some standard applications are shown in the following figures. all serial link applications supported by the ssc are not listed here. figure 217. audio application block diagram pdc interrupt control ssc interrupt txbufe endtx rxbuff endrx rxrdy ovrun rxsync receiver transmitter txrdy txempty txsync ssc_ier ssc_idr ssc_imr set clear ssc rk rf rd td tf tk clock sck word select ws data sd i2s receiver clock sck word select ws data sd right channel left channel msb msb lsb
454 AT91RM9200 1768b?atarm?08/03 figure 218. codec application block diagram figure 219. time slot application block diagram ssc rk rf rd td tf tk serial data clock (sclk) frame sync (fsync) serial data out serial data in codec serial data clock (sclk) frame sync (fsync) serial data out serial data in first time slot dstart dend ssc rk rf rd td tf tk sclk fsync data out data in codec first time slot serial data clock (sclk) frame sync (fsync) serial data out serial data in codec second time slot first time slot second time slot dstart dend
455 AT91RM9200 1768b?atarm?08/03 serial synchronous controller (ssc) user interface table 88. ssc register mapping offset register register name access reset 0x0 control register ssc_cr write ? 0x4 clock mode register ssc_cmr read/write 0x0 0x8 reserved ? ? ? 0xc reserved ? ? ? 0x10 receive clock mode register ssc_rcmr read/write 0x0 0x14 receive frame mode register ssc_rfmr read/write 0x0 0x18 transmit clock mode register ssc_tcmr read/write 0x0 0x1c transmit frame mode register ssc_tfmr read/write 0x0 0x20 receive holding register ssc_rhr read 0x0 0x24 transmit holding register ssc_thr write ? 0x28 reserved ? ? ? 0x2c reserved ? ? ? 0x30 receive sync. holding register ssc_rshr read 0x0 0x34 transmit sync. holding register ssc_tshr read/write 0x0 0x38 reserved ? ? ? 0x3c reserved ? ? ? 0x40 status register ssc_sr read 0x000000cc 0x44 interrupt enable register ssc_ier write ? 0x48 interrupt disable register ssc_idr write ? 0x4c interrupt mask register ssc_imr read 0x0 0x50-0xff reserved ? ? ? 0x100- 0x124 reserved for peripheral data controller (pdc) ? ? ?
456 AT91RM9200 1768b?atarm?08/03 ssc control register name: ssc_cr access type: write-only rxen: receive enable 0: no effect. 1: enables data receive if rxdis is not set (1) . rxdis: receive disable 0: no effect. 1: disables data receive (1) . txen: transmit enable 0: no effect. 1: enables data transmit if txdis is not set (1) . txdis: transmit disable 0: no effect. 1: disables data transmit (1) . swrst: software reset 0: no effect. 1: performs a software reset. has priority on any other bit in ssc_cr. note: 1. only the data management is affected 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 swrst ? ? ? ? ? txdis txen 76543210 ??????rxdisrxen
457 AT91RM9200 1768b?atarm?08/03 ssc clock mode register name: ssc_cmr access type: read/write div: clock divider 0: the clock divider is not active. any other value: the divided clock equals the master clock divided by 2 times div. the maximum bit rate is mck/2. the minimum bit rate is mck/2 x 4095 = mck/8190. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???? div 76543210 div
458 AT91RM9200 1768b?atarm?08/03 ssc receive clock mode register name: ssc_rcmr access type: read/write cks: receive clock selection cko: receive clock output mode selection cki: receive clock inversion 0: the data and the frame sync signal are sampled on receive clock falling edge. 1: the data and the frame sync signal are shifted out on receive clock rising edge. cki does not affects the rk output clock signal. start: receive start selection 31 30 29 28 27 26 25 24 period 23 22 21 20 19 18 17 16 sttdly 15 14 13 12 11 10 9 8 ???? start 76543210 ??cki cko cks cks selected receive clock 0x0 divided clock 0x1 tk clock signal 0x2 rk pin 0x3 reserved cko receive clock out p ut mode rk pin 0x0 none input-only 0x1 continuous receive clock output 0x2-0x7 reserved start receive start 0x0 continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. 0x1 tr a n s m i t s t a r t 0x2 detection of a low level on rf input 0x3 detection of a high level on rf input 0x4 detection of a falling edge on rf input 0x5 detection of a rising edge on rf input 0x6 detection of any level change on rf input 0x7 detection of any edge on rf input 0x8-0xf reserved
459 AT91RM9200 1768b?atarm?08/03 sttdly: receive start delay if sttdly is not 0, a delay of sttdly clock cycles is in serted between the start event and the actual start of reception. when the receiver is programmed to start synchronously with the transmitter, the delay is also applied. please note: it is very important that sttdly be set carefully. if sttdly must be set, it should be done in relation to tag (receive sync data) reception. period: receive period divider selection this field selects the divider to apply to the selected receive clock in order to generate a new frame sync signal. if 0, no period signal is generated. if not 0, a period signal is generated each 2 x (period+1) receive clock.
460 AT91RM9200 1768b?atarm?08/03 ssc receive frame mode register name: ssc_rfmr access type: read/write datlen: data length 0x0 is not supported. the value of datlen can be set between 0x1 and 0x1f. the bit stream contains datlen + 1 data bits. moreover, it defines the transfer size performed by the pdc assigned to the receiver. if datlen is less than or equal to 7, data transfers are in bytes. if datlen is between 8 and 15 (included), half-words are transferred. for any other value, 32-bit words are transferred. loop: loop mode 0: normal operating mode. 1: rd is driven by td, rf is driven by tf and tk drives rk. msbf: most significant bit first 0: the lowest significant bit of the data register is sampled first in the bit stream. 1: the most significant bit of the data register is sampled first in the bit stream. datnb: data number per frame this field defines the number of data words to be received after each transfer start. if 0, only 1 data word is transferred. up to 16 data words can be transferred. fslen: receive frame sync length this field defines the length of the receive frame sync signal and the number of bits sampled and stored in the receive sync data register. only when fsos is set on negative or positive pulse. fsos: receive frame sync output selection 31 30 29 28 27 26 25 24 ???????fsedge 23 22 21 20 19 18 17 16 ? fsos fslen 15 14 13 12 11 10 9 8 ???? datnb 76543210 msbf ? loop datlen fsos selected receive frame s y nc si g nal rf pin 0x0 none input-only 0x1 negative pulse output 0x2 positive pulse output 0x3 driven low during data transfer output 0x4 driven high during data transfer output 0x5 toggling at each start of data transfer output 0x6-0x7 reserved undefined
461 AT91RM9200 1768b?atarm?08/03 fsedge: frame sync edge detection determines which edge on frame sync sets rxsyn in the ssc status register. fsedge frame sync edge detection 0x0 positive edge detection 0x1 negative edge detection
462 AT91RM9200 1768b?atarm?08/03 ssc transmit clock mode register name: ssc_tcmr access type: read/write cks: transmit clock selection cko: transmit clock out p ut mode selection cki: transmit clock inversion 0: the data and the frame sync signal are shifted out on transmit clock falling edge. 1: the data and the frame sync signal are shifted out on transmit clock rising edge. cki affects only the transmit clock and not the output clock signal. start: transmit start selection 31 30 29 28 27 26 25 24 period 23 22 21 20 19 18 17 16 sttdly 15 14 13 12 11 10 9 8 ???? start 76543210 ??cki cko cks cks selected transmit clock 0x0 divided clock 0x1 rk clock signal 0x2 tk pin 0x3 reserved cko transmit clock output mode tk pin 0x0 none input-only 0x1 continuous transmit clock output 0x2-0x7 reserved start transmit start 0x0 continuous, as soon as a word is written in the ssc_thr register (if transmit is enabled) and immediately after the end of transfer of the previous data. 0x1 receive start 0x2 detection of a low level on tf signal 0x3 detection of a high level on tf signal 0x4 detection of a falling edge on tf signal 0x5 detection of a rising edge on tf signal 0x6 detection of any level change on tf signal 0x7 detection of any edge on tf signal 0x8-0xf reserved
463 AT91RM9200 1768b?atarm?08/03 sttdly: transmit start delay if sttdly is not 0, a delay of sttdly clock cycles is inserted between the start event and the actual start of transmission of data. when the transmitter is programmed to start synchronously with the receiver, the delay is also applied. please note: sttdly must be set carefully. if sttdly is too short in respect to tag (transmit sync data) emission, data is emitted instead of the end of tag. period: transmit period divider selection this field selects the divider to apply to the selected transmit clock to generate a new frame sync signal. if 0, no period signal is generated. if not 0, a period signal is generated at each 2 x (period+1) transmit clock.
464 AT91RM9200 1768b?atarm?08/03 ssc transmit frame mode register name: ssc_tfmr access type: read/write datlen: data length 0x0 is not supported. the value of datlen can be set between 0x1 and 0x1f. the bit stream contains datlen + 1 data bits. moreover, it defines the transfer size performed by the pdc assigned to the receiver. if datlen is less than or equal to 7, data transfers are in bytes. if datlen is between 8 and 15 (included), half-words are transferred. for any other value, 32-bit words are transferred. datdef: data default value this bit defines the level driven on the td pin while out of transmission. note that if the pin is defined as multi-drive by th e pio controller, the pin is enabled only if the scc td output is 1. msbf: most significant bit first 0: the lowest significant bit of the data register is shifted out first in the bit stream. 1: the most significant bit of the data register is shifted out first in the bit stream. datnb: data number per frame this field defines the number of data words to be transferred after each transfer start. if 0, only 1 data word is transferred and up to 16 data words can be transferred. fslen: transmit frame sync length this field defines the length of the transmit frame sync signal and the number of bits shifted out from the transmit sync data register if fsden is 1. if 0, the transmit frame sync signal is generated during one transmit clock period and up to 16 clock period pulse length is possible. fsos: transmit frame sync output selection fsden: frame sync data enable 0: the td line is driven with the default value during the transmit frame sync signal. 1: ssc_tshr value is shifted out during the transmission of the transmit frame sync signal. 31 30 29 28 27 26 25 24 ???????fsedge 23 22 21 20 19 18 17 16 fsden fsos fslen 15 14 13 12 11 10 9 8 ???? datnb 76543210 m s b f ? dat d e f dat l e n fsos selected transmit frame s y nc si g nal tf p in 0x0 none input-only 0x1 negative pulse output 0x2 positive pulse output 0x3 driven low during data transfer output 0x4 driven high during data transfer output 0x5 toggling at each start of data transfer output 0x6-0x7 reserved undefined
465 AT91RM9200 1768b?atarm?08/03 fsedge: frame sync edge detection determines which edge on frame sync sets txsyn (status register). fsedge frame sync edge detection 0x0 positive edge detection 0x1 negative edge detection
466 AT91RM9200 1768b?atarm?08/03 ssc receive holding register name: ssc_rhr access type : read-only rdat: receive data right aligned regardless of the number of data bits defined by datlen in ssc_rfmr. ssc transmit holding register name: ssc_thr access type: write only tdat: transmit data right aligned regardless of the number of data bits defined by datlen in ssc_tfmr. 31 30 29 28 27 26 25 24 rdat 23 22 21 20 19 18 17 16 rdat 15 14 13 12 11 10 9 8 rdat 76543210 rdat 31 30 29 28 27 26 25 24 tdat 23 22 21 20 19 18 17 16 tdat 15 14 13 12 11 10 9 8 tdat 76543210 tdat
467 AT91RM9200 1768b?atarm?08/03 ssc receive synchroniza tion holding register name: ssc_rshr access type : read/write rsdat: receive synchronization data right aligned regardless of the number of data bits defined by fslen in ssc_rfmr. ssc transmit synchronization holding register name: ssc_tshr access type : read/write tsdat: transmit synchronization data right aligned regardless of the number of data bits defined by fslen in ssc_tfmr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rsdat 76543210 rsdat 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 tsdat 76543210 tsdat
468 AT91RM9200 1768b?atarm?08/03 ssc status register register name :ssc_sr access type : read-only txrdy: transmit ready 0: data has been loaded in ssc_thr and is waiting to be loaded in the transmit shift register. 1: ssc_thr is empty. txempty: transmit empty 0: data remains in ssc_thr or is currently transmitted from transmit shift register. 1: last data written in ssc_thr has been loaded in transmit shift register and transmitted by it. endtx: end of transmission 0: the register ssc_tcr has not reached 0 si nce the last write in ssc_tcr or ssc_tncr. 1: the register ssc_tcr has reached 0 sinc e the last write in ssc_tcr or ssc_tncr. txbufe: transmit buffer empty 0: ssc_tcr or ssc_tncr have a value other than 0. 1: both ssc_tcr and ssc_tncr have a value of 0. rxrdy: receive ready 0: ssc_rhr is empty. 1: data has been received and loaded in ssc_rhr. ovrun: receive overrun 0: no data has been loaded in ssc_rhr while previous data has not been read since the last read of the status register. 1: data has been loaded in ssc_rhr while previous data has not yet been read since the last read of the status register. endrx: end of reception 0: data is written on the receive counter register or receive next counter register. 1: end of pdc transfer when receive counter register has arrived at zero. rxbuff: receive buffer full 0: ssc_rcr or ssc_rncr have a value other than 0. 1: both ssc_rcr and ssc_rncr have a value of 0. txsyn: transmit sync 0: a tx sync has not occurred since the last read of the status register. 1: a tx sync has occurred since the last read of the status register. rxsyn: receive sync 0: a rx sync has not occurred since the last read of the status register. 1: a rx sync has occurred since the last read of the status register. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? rxen txen 15 14 13 12 11 10 9 8 ? ? ? ? rxsyn txsyn ? ? 76543210 rxbuff endrx ovrun rxrdy txbufe endtx txempty txrdy
469 AT91RM9200 1768b?atarm?08/03 txen: transmit enable 0: transmit data is disabled. 1: transmit data is enabled. rxen: receive enable 0: receive data is disabled. 1: receive data is enabled.
470 AT91RM9200 1768b?atarm?08/03 ssc interrupt enable register register name :ssc_ier access type : write-only txrdy: transmit ready txempty: transmit empty endtx: end of transmission txbufe: transmit buffer empty rxrdy: receive ready ovrun: receive overrun endrx: end of reception rxbuff: receive buffer full txsyn: tx sync rxsyn: rx sync 0: no effect. 1: enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? ? ? rxsyn txsyn ? ? 76543210 rxbuff endrx ovrun rxrdy txbufe endtx txempty txrdy
471 AT91RM9200 1768b?atarm?08/03 ssc interrupt disable register register name :ssc_idr access type : write-only txrdy: transmit ready txempty: transmit empty endtx: end of transmission txbufe: transmit buffer empty rxrdy: receive ready ovrun: receive overrun endrx: end of reception rxbuff: receive buffer full txsyn: tx sync rxsyn: rx sync 0: no effect. 1: disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? ? ? rxsyn txsyn ? ? 76543210 rxbuff endrx ovrun rxrdy txbufe endtx txempty txrdy
472 AT91RM9200 1768b?atarm?08/03 ssc interrupt mask register register name :ssc_imr access type : read-only txrdy: transmit ready txempty: transmit empty endtx: end of transmission txbufe: transmit buffer empty rxrdy: receive ready ovrun: receive overrun endrx: end of reception rxbuff: receive buffer full txsyn: tx sync rxsyn: rx sync 0: the corresponding interrupt is disabled. 1: the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? ? ? rxsyn txsyn ? ? 76543210 rxbuff endrx ovrun rxrdy txbufe endtx txempty txrdy
473 AT91RM9200 1768b?atarm?08/03 timer counter (tc) overview the timer counter (tc) includes three identical 16-bit timer counter channels. each channel can be independently programmed to perform a wide range of functions includ- ing frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. each channel has three external clock inputs, five internal clock inputs and two multi-purpose input/output signals which can be configured by the user. ea ch channel drives an internal interrupt signal which can be programmed to generate processor interrupts. the timer counter block has two global registers which act upon all three tc channels. the block control register allows the three channels to be started simultaneously with the same instruction. the block mode register defines the external clock inputs for each channel, allowing them to be chained. key features of the timer counter are: three 16-bit timer counter channels a wide range of functions including: ? frequency measurement ? event counting ? interval measurement ? pulse generation ?delay timing ? pulse width modulation ? up/down capabilities each channel is user-configurable and contains: ? three external clock inputs ? five internal clock inputs ? two multi-purpose input/output signals internal interrupt signal two global registers that act on all three tc channels
474 AT91RM9200 1768b?atarm?08/03 block diagram figure 220. timer counter block diagram table 89. signal name description block/channel signal name description channel signal xc0, xc1, xc2 external clock inputs tioa capture mode: general-purpose input waveform mode: general-purpose output tiob capture mode: general-purpose input waveform mode: general-purpose input/output int interrupt signal output sync synchronization input signal block signal tclk0, tclk1, tclk2 external clock inputs tioa0 tioa signal for channel 0 tiob0 tiob signal for channel 0 tioa1 tioa signal for channel 1 tiob1 tiob signal for channel 1 tioa2 tioa signal for channel 2 tiob2 tiob signal for channel 2 timer/counter channel 0 timer/counter channel 1 timer/counter channel 2 sync parallel i/o controller tc1xc1s tc0xc0s tc2xc2s int0 int1 int2 tioa0 tioa1 tioa2 tiob0 tiob1 tiob2 xc0 xc1 xc2 xc0 xc1 xc2 xc0 xc1 xc2 tclk0 tclk1 tclk2 tclk0 tclk1 tclk2 tclk0 tclk1 tclk2 tioa1 tioa2 tioa0 tioa2 tioa0 tioa1 advanced interrupt controller tclk0 tclk1 tclk2 tioa0 tiob0 tioa1 tiob1 tioa2 tiob2 timer counter tioa tiob tioa tiob tioa tiob sync sync timer_clock2 timer_clock3 timer_clock4 timer_clock5 timer_clock1
475 AT91RM9200 1768b?atarm?08/03 pin name list product dependencies for further details on the timer counter hardware implementation, see the specific product properties document. i/o lines the pins used for interfacing the compliant external devices may be multiplexed with pio lines. the programmer must first program the pio controllers to assign the tc pins to their peripheral functions. power management the tc must be clocked throu g h the power mana g ement controller ( pmc ) , thus the p ro g ram- mer must first confi g ure the pmc to enable the timer counter. interrupt the tc interface has an interrupt line connected to the advanced interrupt controller (aic). handling the tc interrupt requires programming the aic before configuring the tc. functional description tc description the three channels of the timer counter are independent and identical in operation. the reg- isters for channel programming are listed in table 90 on page 475. 16-bit counter each channel is organized around a 16-bit counter. the value of the counter is incremented at each positive edge of the selected clock. when the counter has reached the value 0xffff and passes to 0x0000, an overflow occurs and the covfs bit in tc_sr (status register) is set. the current value of the counter is accessible in real time by reading the counter value regis- ter, tc_cv. the counter can be reset by a trigger. in this case, the counter value passes to 0x0000 on the next valid edge of the selected clock. clock selection at block level, input clock signals of each channel can either be connected to the external inputs tclk0, tclk1 or tclk2, or be connected to the configurable i/o signals tioa0, tioa1 or tioa2 for chaining by programming the tc_bmr (block mode). see figure 221. each channel can independently select an internal or external clock source for its counter: internal clock signals: timer_clock1, timer_clock2, timer_clock3, timer_clock4, timer_clock5 external clock signals: xc0, xc1 or xc2 this selection is made by the tcclks bits in the tc channel mode register (capture mode). the selected clock can be inverted with the clki bit in tc_cmr (capture mode). this allows counting on the opposite edges of the clock. table 90. timer counter pin list pin name description type tclk0-tclk2 external clock input input tioa0-tioa2 i/o line a i/o tiob0-tiob2 i/o line b i/o
476 AT91RM9200 1768b?atarm?08/03 the burst function allows the clock to be va lidated when an external signal is high. the burst parameter in the mode register defines this signal (none, xc0, xc1, xc2). note: in all cases, if an external clock is used, the duration of each of its levels must be longer than the master clock period. the external clock frequency must be at least 2.5 times lower than the master clock figure 221. clock selection clock control the clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. see figure 222. the clock can be enabled or disabled by the user with the clken and the clkdis commands in the control register. in capture mode it can be disabled by an rb load event if ldbdis is set to 1 in tc_cmr. in waveform mode, it can be disabled by an rc compare event if cpcdis is set to 1 in tc_cmr. when disabled, the start or the stop actions have no effect: only a clken command in the control register can re-enable the clock. when the clock is enabled, the clksta bit is set in the status register. the clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the clock. the clock can be stopped by an rb load event in capture mode (ldbstop = 1 in tc_cmr) or a rc compare event in waveform mode (cpcstop = 1 in tc_cmr). the start and the stop commands have effect only if the clock is enabled. timer_clock1 timer_clock2 timer_clock3 timer_clock4 timer_clock5 xc0 xc1 xc2 tcclks clki burst 1 selected clock
477 AT91RM9200 1768b?atarm?08/03 figure 222. clock control tc operating modes each channel can independently operate in two different modes: capture mode provides measurement on signals. waveform mode provides wave generation. the tc operating mode is programmed with the wave bit in the tc channel mode register. in capture mode, tioa and tiob are configured as inputs. in waveform mode, tioa is always configured to be an output and tiob is an output if it is not selected to be the external trigger. trigger a trigger resets the counter and starts the counter clock. three types of triggers are common to both modes, and a fourth external trigger is available to each mode. the following triggers are common to both modes: software trigger: each channel has a software trigger, available by setting swtrg in tc_ccr. sync: each channel has a synchronization signal sync. when asserted, this signal has the same effect as a software trigger. the sync signals of all channels are asserted simultaneously by writing tc_bcr (block control) with sync set. compare rc trigger: rc is implemented in each channel and can provide a trigger when the counter value matches the rc value if cpctrg is set in tc_cmr. the channel can also be configured to have an external trigger. in capture mode, the external trigger signal can be selected between tioa and tiob. in waveform mode, an external event can be programmed on one of the following signals: tiob, xc0, xc1 or xc2. this external event can then be programmed to perform a trigger by setting enetrg in tc_cmr. if an external trigger is used, the duration of the pulses must be longer than the master clock period in order to be detected. regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. this means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock. qs r s r q clksta clken clkdis stop event disable event counter clock selected clock trigger
478 AT91RM9200 1768b?atarm?08/03 capture operating mode this mode is entered by clearing the wave parameter in tc_cmr (channel mode register). capture mode allows the tc channel to perform measurements such as pulse timing, fre- quency, period, duty cycle and phase on tioa and tiob signals which are considered as inputs. figure 223 shows the configuration of the tc channel when programmed in capture mode. capture registers a and b registers a and b (ra and rb) are used as captur e registers. this means that they can be loaded with the counter value when a programmable event occurs on the signal tioa. the ldra parameter in tc_cmr defines the tioa edge for the loading of register a, and the ldrb parameter defines the tioa edge for the loading of register b. ra is loaded only if it has not been loaded since the last trigger or if rb has been loaded since the last loading of ra. rb is loaded only if ra has been loaded since the last trigger or the last loading of rb. loading ra or rb before the read of the last value loaded sets the overrun error flag (lovrs) in tc_sr (status register). in this case, the old value is overwritten. trigger conditions in addition to the sync signal, the software trigger and the rc compare trigger, an external trigger can be defined. the abetrg bit in tc_cmr selects tioa or tiob input signal as an external trigger. the etrgedg parameter defines the edge (rising, falling or both) detected to generate an exter- nal trigger. if etrgedg = 0 (none), the external trigger is disabled.
479 AT91RM9200 1768b?atarm?08/03 figure 223. capture mode timer_clock1 timer_clock2 timer_clock3 timer_clock4 timer_clock5 xc0 xc1 xc2 tcclks clki qs r s r q clksta clken clkdis burst tiob register c capture register a capture register b compare rc = 16-bit counter abetrg swtrg etrgedg cpctrg tc1_imr trig ldrbs ldras etrgs tc1_sr lovrs covfs sync 1 mtiob tioa mtioa ldra ldbstop if ra is not loaded or rb is loaded if ra is loaded ldbdis cpcs int edge detector edge detector ldrb edge detector clk ovf reset timer/counter channel
480 AT91RM9200 1768b?atarm?08/03 waveform operating mode waveform operating mode is entered by se tting the wave parameter in tc_cmr (channel mode register). in waveform operating mode the tc channel generates 1 or 2 pwm signals with the same frequency and independently programmable duty cycles, or generates different types of one- shot or repetitive pulses. in this mode, tioa is configured as an output and tiob is defined as an output if it is not used as an external event (eevt parameter in tc_cmr). figure 224 shows the configuration of the tc channel when programmed in waveform oper- ating mode. waveform selection depending on the wavsel parameter in tc_cmr (channel mode register), the behavior of tc_cv varies. with any selection, ra, rb and rc can all be used as compare registers. ra compare is used to control the tioa output, rb compare is used to control the tiob out- put (if correctly configured) and rc compare is used to control tioa and/or tiob outputs.
481 AT91RM9200 1768b?atarm?08/03 figure 224. waveform mode tcclks clki qs r s r q clksta clken clkdis cpcdis burst tiob register a register b register c compare ra = compare rb = compare rc = cpcstop 16-bit counter eevt eevtedg sync swtrg enetrg wavsel tc1_imr trig acpc acpa aeevt aswtrg bcpc bcpb beevt bswtrg tioa mtioa tiob mtiob cpas covfs etrgs tc1_sr cpcs cpbs clk ovf reset output controller output controller int 1 edge detector timer/counter channel timer_clock1 timer_clock2 timer_clock3 timer_clock4 timer_clock5 xc0 xc1 xc2 wavsel
482 AT91RM9200 1768b?atarm?08/03 wavsel = 00 when wavsel = 00, the value of tc_cv is incremented from 0 to 0xffff. once 0xffff has been reached, the value of tc_cv is reset. incrementation of tc_cv starts again and the cycle continues. see figure 225. an external event trigger or a software trigger can reset the value of tc_cv. it is important to note that the trigger may occur at any time. see figure 226. rc compare cannot be programmed to generate a trigger in this configuration. at the same time, rc compare can stop the counter clock (cpcstop = 1 in tc_cmr) and/or disable the counter clock (cpcdis = 1 in tc_cmr). figure 225. wavsel= 00 without trigger figure 226. wavsel= 00 with trigger time counter value r c r b r a tiob tioa counter cleared by compare match with 0xffff 0xffff waveform examples time counter value r c r b r a tiob tioa counter cleared by compare match with 0xffff 0xffff waveform examples counter cleared by trigger
483 AT91RM9200 1768b?atarm?08/03 wavsel = 10 when wavsel = 10, the value of tc_cv is incremented from 0 to the value of rc, then auto- matically reset on a rc compare. once the value of tc_cv has been reset, it is then incremented and so on. see figure 227. it is important to note that tc_cv can be reset at any time by an external event or a software trigger if both are programmed correctly. see figure 228. in addition, rc compare can stop the counter clock (cpcstop = 1 in tc_cmr) and/or dis- able the counter clock (cpcdis = 1 in tc_cmr). figure 227. wavsel = 10 without trigger figure 228. wavsel = 10 with trigger time counter value r c r b r a tiob tioa counter cleared by compare match with rc 0xffff waveform examples time counter value r c r b r a tiob tioa counter cleared by compare match with rc 0xffff waveform examples counter cleared by trigger
484 AT91RM9200 1768b?atarm?08/03 wavsel = 01 when wavsel = 01, the value of tc_cv is incremented from 0 to 0xffff. once 0xffff is reached, the value of tc_cv is decremented to 0, then re-incremented to 0xffff and so on. see figure 229. a trigger such as an external event or a software trigger can modify tc_cv at any time. if a trigger occurs while tc_cv is incrementing, tc_cv then decrements. if a trigger is received while tc_cv is decrementing, tc_cv then increments. see figure 230. rc compare cannot be programmed to generate a trigger in this configuration. at the same time, rc compare can stop the counter clock (cpcstop = 1) and/or disable the counter clock (cpcdis = 1). figure 229. wavsel = 01 without trigger figure 230. wavsel = 01 with trigger time counter value r c r b r a tiob tioa counter decremented by compare match with 0xffff 0xffff waveform examples time counter value tiob tioa counter decremented by compare match with 0xffff 0xffff waveform examples counter decremented by trigger counter incremented by trigger r c r b r a
485 AT91RM9200 1768b?atarm?08/03 wavsel = 11 when wavsel = 11, the value of tc_cv is incremented from 0 to rc. once rc is reached, the value of tc_cv is decremented to 0, then re-incremented to rc and so on. see figure 231. a trigger such as an external event or a software trigger can modify tc_cv at any time. if a trigger occurs while tc_cv is incrementing, tc_cv then decrements. if a trigger is received while tc_cv is decrementing, tc_cv then increments. see figure 232. rc compare can stop the counter clock (cpcstop = 1) and/or disable the counter clock (cpcdis = 1). figure 231. wavsel = 11 without trigger figure 232. wavsel = 11 with trigger time counter value r c r b r a tiob tioa counter decremented by compare match with rc 0xffff waveform examples time counter value tiob tioa counter decremented by compare match with rc 0xffff waveform examples counter decremented by trigger counter incremented by trigger r c r b r a
486 AT91RM9200 1768b?atarm?08/03 external event/trigger conditions an external event can be programmed to be detected on one of the clock sources (xc0, xc1, xc2) or tiob. the external event selected can then be used as a trigger. the parameter eevt parameter in tc_cmr selects the external trigger. the eevtedg parameter defines the trigger edge for each of the possible external triggers (rising, falling or both). if eevtedg is cleared (none), no external event is defined. if tiob is defined as an external event signal (eevt = 0), tiob is no longer used as an output and the tc channel can only generate a waveform on tioa. when an external event is defined, it can be used as a trigger by setting bit enetrg in tc_cmr. as in capture mode, the sync signal and the software trigger are also available as triggers. rc compare can also be used as a trigger depending on the parameter wavsel. output controller the output controller defines the output level changes on tioa and tiob following an event. tiob control is used only if tiob is defined as output (not as an external event). the following events control tioa and tiob: software trigger, external event and rc com- pare. ra compare controls tioa and rb compare controls tiob. each of these events can be programmed to set, clear or toggle the output as defined in the corresponding parameter in tc_cmr.
487 AT91RM9200 1768b?atarm?08/03 timer counter (tc) user interface tc_bcr (block control register) and tc_bmr (block mode register) control the whole tc block. tc channels are con- trolled by the registers listed in table 92 . the offset of each of the channel registers in table 92 is in relation to the offset of the corresponding channel as mentioned in table 92 . notes: 1. read only if wave = 0 table 91. timer counter global memory map offset channel/register name access reset value 0x00 tc channel 0 see table 92 see table 92 see table 92 0x40 tc channel 1 0x80 tc channel 2 0xc0 tc block control register tc_bcr write-only ? 0xc4 tc block mode register tc_bmr read/write 0 table 92. timer counter channel memory map offset register name access reset value 0x00 channel control register tc_ccr write-only ? 0x04 channel mode register tc_cmr read/write 0 0x08 reserved ? 0x0c reserved ? 0x10 counter value tc_cv read-only 0 0x14 register a tc_ra read/write (1) 0 0x18 register b tc_rb read/write (1) 0 0x1c register c tc_rc read/write 0 0x20 status register tc_sr read-only 0 0x24 interrupt enable register tc_ier write-only ? 0x28 interrupt disable register tc_idr write-only ? 0x2c interrupt mask register tc_imr read-only 0
488 AT91RM9200 1768b?atarm?08/03 tc block control register register name: tc_bcr access type: write-only sync: synchro command 0 = no effect. 1 = asserts the sync signal which generates a software trigger simultaneously for each of the channels. tc block mode register register name: tc_bmr access type: read/write tc0xc0s: external clock signal 0 selection tc1xc1s: external clock signal 1 selection 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????sync 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? tc2xc2s tcxc1s tc0xc0s tc0xc0s signal connected to xc0 00tclk0 0 1 none 10tioa1 11tioa2 tc1xc1s signal connected to xc1 00tclk1 0 1 none 10tioa0 11tioa2
489 AT91RM9200 1768b?atarm?08/03 tc2xc2s: external clock signal 2 selection tc channel control register register name: tc_ccr access type: write-only clken: counter clock enable command 0 = no effect. 1 = enables the clock if clkdis is not 1. clkdis: counter clock disable command 0 = no effect. 1 = disables the clock. swtrg: software trigger command 0 = no effect. 1 = a software trigger is performed: the counter is reset and the clock is started. tc2xc2s signal connected to xc2 00tclk2 0 1 none 10tioa0 11tioa1 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ? ? ? swtrg clkdis clken
490 AT91RM9200 1768b?atarm?08/03 tc channel mode re gister: capture mode register name: tc_cmr access type: read/write tcclks: clock selection clki: clock invert 0 = counter is incremented on rising edge of the clock. 1 = counter is incremented on falling edge of the clock. burst: burst signal selection ldbstop: counter clock stopped with rb loading 0 = counter clock is not stopped when rb loading occurs. 1 = counter clock is stopped when rb loading occurs. ldbdis: counter clock disable with rb loading 0 = counter clock is not disabled when rb loading occurs. 1 = counter clock is disabled when rb loading occurs. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ? ? ? ? ldrb ldra 15 14 13 12 11 10 9 8 wave = 0 cpctrg ? ? ? abetrg etrgedg 76543210 ldbdis ldbstop burst clki tcclks tcclks clock selected 0 0 0 timer_clock1 0 0 1 timer_clock2 0 1 0 timer_clock3 0 1 1 timer_clock4 1 0 0 timer_clock5 101xc0 110xc1 111xc2 burst 0 0 the clock is not gated by an external signal. 0 1 xc0 is anded with the selected clock. 1 0 xc1 is anded with the selected clock. 1 1 xc2 is anded with the selected clock.
491 AT91RM9200 1768b?atarm?08/03 etrgedg: external trigger edge selection abetrg: tioa or tiob external trigger selection 0 = tiob is used as an external trigger. 1 = tioa is used as an external trigger. cpctrg: rc compare trigger enable 0 = rc compare has no effect on the counter and its clock. 1 = rc compare resets the counter and starts the counter clock. wave 0 = capture mode is enabled. 1 = capture mode is disabled (waveform mode is enabled). ldra: ra loading selection ldrb: rb loading selection etrgedg edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge ldra edge 0 0 none 0 1 rising edge of tioa 1 0 falling edge of tioa 1 1 each edge of tioa ldrb edge 0 0 none 0 1 rising edge of tioa 1 0 falling edge of tioa 1 1 each edge of tioa
492 AT91RM9200 1768b?atarm?08/03 tc channel mode regi ster: waveform mode register name: tc_cmr access type: read/write tcclks: clock selection clki: clock invert 0 = counter is incremented on rising edge of the clock. 1 = counter is incremented on falling edge of the clock. burst: burst signal selection cpcstop: counter clock stopped with rc compare 0 = counter clock is not stopped when counter reaches rc. 1 = counter clock is stopped when counter reaches rc. cpcdis: counter clock disable with rc compare 0 = counter clock is not disabled when counter reaches rc. 1 = counter clock is disabled when counter reaches rc. 31 30 29 28 27 26 25 24 bswtrg beevt bcpc bcpb 23 22 21 20 19 18 17 16 aswtrg aeevt acpc acpa 15 14 13 12 11 10 9 8 wave = 1 wavsel enetrg eevt eevtedg 76543210 cpcdis cpcstop burst clki tcclks tcclks clock selected 0 0 0 timer_clock1 0 0 1 timer_clock2 0 1 0 timer_clock3 0 1 1 timer_clock4 1 0 0 timer_clock5 101xc0 110xc1 111xc2 burst 0 0 the clock is not gated by an external signal. 0 1 xc0 is anded with the selected clock. 1 0 xc1 is anded with the selected clock. 1 1 xc2 is anded with the selected clock.
493 AT91RM9200 1768b?atarm?08/03 eevtedg: external event edge selection eevt: external event selection note: 1. if tiob is chosen as the external event signal, it is configured as an input and no longer generates waveforms . enetrg: external event trigger enable 0 = the external event has no effect on the counter and its clock. in this case, the selected external event only controls the tioa output. 1 = the external event resets the counter and starts the counter clock. wavsel: waveform selection wave = 1 0 = waveform mode is disabled (capture mode is enabled). 1 = waveform mode is enabled. acpa: ra compare effect on tioa acpc: rc compare effect on tioa eevtedg edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge eevt signal selected as external event tiob direction 0 0 tiob input (1) 01xc0 output 10xc1 output 11xc2 output wavsel effect 0 0 up mode without automatic trigger on rc compare 1 0 up mode with automatic trigger on rc compare 0 1 updown mode without automatic trigger on rc compare 1 1 updown mode with automatic trigger on rc compare acpa effect 0 0 none 01set 10clear 1 1 toggle acpc effect 0 0 none 01set 10clear 1 1 toggle
494 AT91RM9200 1768b?atarm?08/03 aeevt: external event effect on tioa aswtrg: software trigger effect on tioa bcpb: rb compare effect on tiob bcpc: rc compare effect on tiob beevt: external event effect on tiob bswtrg: software trigger effect on tiob aeevt effect 0 0 none 01set 10clear 1 1 toggle aswtrg effect 0 0 none 01set 10clear 1 1 toggle bcpb effect 0 0 none 01set 10clear 1 1 toggle bcpc effect 0 0 none 01set 10clear 1 1 toggle beevt effect 0 0 none 01set 10clear 1 1 toggle bswtrg effect 0 0 none 01set 10clear 1 1 toggle
495 AT91RM9200 1768b?atarm?08/03 tc counter value register register name: tc_cv access type: read-only cv: counter value cv contains the counter value in real time. tc register a register name: tc_ra access type: read-only if wave = 0, read/write if wave = 1 ra: register a ra contains the register a value in real time. tc register b register name: tc_rb access type: read-only if wave = 0, read/write if wave = 1 rb: register b rb contains the register b value in real time. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 cv 76543210 cv 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ra 76543210 ra 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rb 76543210 rb
496 AT91RM9200 1768b?atarm?08/03 tc register c register name: tc_rc access type: read/write rc: register c rc contains the register c value in real time. tc status register register name: tc_sr access type: read-only covfs: counter overflow status 0 = no counter overflow has occurred since the last read of the status register. 1 = a counter overflow has occurred since the last read of the status register. lovrs: load overrun status 0 = load overrun has not occurred since the last read of the status register or wave = 1. 1 = ra or rb have been loaded at least twice without any read of the corresponding register since the last read of the sta- tus register, if wave = 0. cpas: ra compare status 0 = ra compare has not occurred since the last read of the status register or wave = 0. 1 = ra compare has occurred since the last read of the status register, if wave = 1. cpbs: rb compare status 0 = rb compare has not occurred since the last read of the status register or wave = 0. 1 = rb compare has occurred since the last read of the status register, if wave = 1. cpcs: rc compare status 0 = rc compare has not occurred since the last read of the status register. 1 = rc compare has occurred since the last read of the status register. ldras: ra loading status 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rc 76543210 rc 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?????mtiobmtioaclksta 15 14 13 12 11 10 9 8 ???????? 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
497 AT91RM9200 1768b?atarm?08/03 0 = ra load has not occurred since the last read of the status register or wave = 1. 1 = ra load has occurred since the last read of the status register, if wave = 0. ldrbs: rb loading status 0 = rb load has not occurred since the last read of the status register or wave = 1. 1 = rb load has occurred since the last read of the status register, if wave = 0. etrgs: external trigger status 0 = external trigger has not occurred since the last read of the status register. 1 = external trigger has occurred since the last read of the status register. clksta: clock enabling status 0 = clock is disabled. 1 = clock is enabled. mtioa: tioa mirror 0 = tioa is low. if wave = 0, this means that tioa pin is low. if wave = 1, this means that tioa is driven low. 1 = tioa is high. if wave = 0, this means that tioa pin is high. if wave = 1, this means that tioa is driven high. mtiob: tiob mirror 0 = tiob is low. if wave = 0, this means that tiob pin is low. if wave = 1, this means that tiob is driven low. 1 = tiob is high. if wave = 0, this means that tiob pin is high. if wave = 1, this means that tiob is driven high.
498 AT91RM9200 1768b?atarm?08/03 tc interrupt enable register register name: tc_ier access type: write-only covfs: counter overflow 0 = no effect. 1 = enables the counter overflow interrupt. lovrs: load overrun 0 = no effect. 1 = enables the load overrun interrupt. cpas: ra compare 0 = no effect. 1 = enables the ra compare interrupt. cpbs: rb compare 0 = no effect. 1 = enables the rb compare interrupt. cpcs: rc compare 0 = no effect. 1 = enables the rc compare interrupt. ldras: ra loading 0 = no effect. 1 = enables the ra load interrupt. ldrbs: rb loading 0 = no effect. 1 = enables the rb load interrupt. etrgs: external trigger 0 = no effect. 1 = enables the external trigger interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
499 AT91RM9200 1768b?atarm?08/03 tc interrupt disable register register name: tc_idr access type: write-only covfs: counter overflow 0 = no effect. 1 = disables the counter overflow interrupt. lovrs: load overrun 0 = no effect. 1 = disables the load overrun interrupt (if wave = 0). cpas: ra compare 0 = no effect. 1 = disables the ra compare interrupt (if wave = 1). cpbs: rb compare 0 = no effect. 1 = disables the rb compare interrupt (if wave = 1). cpcs: rc compare 0 = no effect. 1 = disables the rc compare interrupt. ldras: ra loading 0 = no effect. 1 = disables the ra load interrupt (if wave = 0). ldrbs: rb loading 0 = no effect. 1 = disables the rb load interrupt (if wave = 0). etrgs: external trigger 0 = no effect. 1 = disables the external trigger interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
500 AT91RM9200 1768b?atarm?08/03 tc interrupt mask register register name: tc_imr access type: read-only covfs: counter overflow 0 = the counter overflow interrupt is disabled. 1 = the counter overflow interrupt is enabled. lovrs: load overrun 0 = the load overrun interrupt is disabled. 1 = the load overrun interrupt is enabled. cpas: ra compare 0 = the ra compare interrupt is disabled. 1 = the ra compare interrupt is enabled. cpbs: rb compare 0 = the rb compare interrupt is disabled. 1 = the rb compare interrupt is enabled. cpcs: rc compare 0 = the rc compare interrupt is disabled. 1 = the rc compare interrupt is enabled. ldras: ra loading 0 = the load ra interrupt is disabled. 1 = the load ra interrupt is enabled. ldrbs: rb loading 0 = the load rb interrupt is disabled. 1 = the load rb interrupt is enabled. etrgs: external trigger 0 = the external trigger interrupt is disabled. 1 = the external trigger interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
501 AT91RM9200 1768b?atarm?08/03 multimedia card interface (mci) overview the multimedia card interface (mci) supports the multimediacard (mmc) specification v2.2 and the sd memory card specification v1.0. the mci includes a command register, response registers, data registers, timeout counters and error detection logic that automatically handle the transmission of commands and, when required, the reception of the associated responses and data with limited processor overhead. the mci supports stream, block and multi-block data read and write, and is compatible with the peripheral data controller channels, minimizing processor intervention for large buffer transfers. the mci operates at a rate of up to master clock divided by 2 and supports interfacing of up to 16 slots (depending on the product). each slot may be used to interface with a multimediacard bus (up to 30 cards) or with an sd memory card. only one slot can be selected at a time (slots are multiplexed). a bit in the command register performs this selection. the sd memory card communication is based on a 9-pin interface (clock, command, four data and three power lines) and the multimediacard on a 7-pin interface (clock, command, one data and three power lines). the sd memory card interface also supports multimedia card operations. the main differ- ences between sd and multimedia cards are the initialization process and the bus topology. the main features of the mci are: compatibility with multimedia card specification version 2.2 compatibility with sd memory card specification version 1.0 cards clock rate up to master clock divided by 2 embedded power management to slow down clock rate when not used supports up to sixteen multiplexed slots (product-dependent) ? one slot for one multimediacard bus (up to 30 cards) or one sd memory card support for stream, block and multi-block data read and write supports connection to peripheral data controller ? minimizes processor intervention for large buffer transfers
502 AT91RM9200 1768b?atarm?08/03 block diagram figure 233. block diagram mci interface interrupt control pio pdc apb bridge pmc mck mci interrupt mcck mccda mcda0 mcda1 mcda2 mcda3 mccdb mcdb0 mcdb1 mcdb2 mcdb3 asb apb
503 AT91RM9200 1768b?atarm?08/03 application block diagram figure 234. application block diagram note: 1. i: input, o: output, pp: push/pull, od: open drain. 23456 17 mmc 23456 17 8 sdcard 9 physical layer mci interface application layer ex: file system, audio, security, etc. table 93. i/o lines description pin name pin description type (1) comments mccda/mccdb command/response i/o/pp/od cmd of an mmc or sd card mcck clock i clk of an mmc or sd card mcda0 - mcda3 data 0..3 of slot a i/o/pp dat0 of an mmc dat[0..3] of an sd card mcdb0 - mcdb3 data 0..3 of slot b i/o/pp dat0 of an mmc dat[0..3] of an sd card
504 AT91RM9200 1768b?atarm?08/03 product dependencies i/o lines the pins used for interfacing the multimedia cards or sd cards may be multiplexed with pio lines. the programmer must first program the pio controllers to assign the peripheral func- tions to mci pins. power management the mci may be clocked through the power management controller (pmc), so the program- mer must first to configure the pmc to enable the mci clock. interrupt the mci interface has an interrupt line connected to the advanced interrupt controller (aic). handling the mci interrupt requires programming the aic before configuring the mci. bus topology figure 235. multimedia memory card bus topology the multimedia card communication is based on a 7-pin serial bus interface. it has three com- munication lines and four supply lines. note: 1. i: input, o: output, pp: push/pull, od: open drain. figure 236. mmc bus connections table 94. bus topology pin number name type (1) description mci pin name 1 rsv nc not connected 2 cmd i/o/pp/od command/response mccda/mccdb 3 vss1 s supply voltage ground vss 4 vdd s supply voltage vdd 5 clk i clock mcck 6 vss2 s supply voltage ground vss 7 dat[0] i/o/pp data 0 mcda0/mcdb0 23456 17 mmc 23456 1 7 23456 1 7 23456 17 mcda0 mccda mcck mmc1 mmc2 mmc3 mci
505 AT91RM9200 1768b?atarm?08/03 figure 237. sd memory card bus topology the sd memory card bus includes the signals listed in table 95. note: 1. i: input, o: output, pp: push pull, od: open drain figure 238. sd card bus connections table 95. sd memory card bus signals pin number name type (1) description mci pin name 1 cd/dat[3] i/o/pp card detect/ data line bit 3 mcda3/mcdb3 2 cmd pp command/response mccda/mccdb 3 vss1 s supply voltage ground vss 4 vdd s supply voltage vdd 5 clk i clock mcck 6 vss2 s supply voltage ground vss 7 dat[0] i/o/pp data line bit 0 mcda0/mcdb0 8 dat[1] i/o/pp data line bit 1 mcda1/mcdb1 9 dat[2] i/o/pp data line bit 2 mcda2/mcdb2 23456 17 8 sd card 9 23456 17 mcda0 - mcda3 mccda mcck 8 sd card 1 9 23456 17 8 sd card 2 9 mcdb0 - mcdb3 mccdb
506 AT91RM9200 1768b?atarm?08/03 figure 239. mixing multimedia and sd memory cards when the mci is configured to operate with sd memory cards, the width of the data bus can be selected in the mci_sdcr register. clearing the sdcbus bit in this register means that the width is one bit and setting it means that the width is four bits. in the case of multimedia cards, only the data line 0 is used. the other data lines can be used as independent pios. multimedia card operations after a power-on reset, the cards are initialized by a special message-based multimedia card bus protocol. each message is represented by one of the following tokens: command: a command is a token that starts an operation. a command is sent from the host either to a single card (addressed command) or to all connected cards (broadcast command). a command is transferred serially on the cmd line. response: a response is a token which is sent from an addressed card or (synchronously) from all connected cards to the host as an answer to a previously received command. a response is transferred serially on the cmd line. data: data can be transferred from the card to the host or vice versa. data is transferred via the data line. card addressing is implemented using a session address assigned during the initialization phase by the bus controller to all currently connected cards. their unique cid number identi- fies individual cards. the structure of commands, responses and data blocks is described in the multimedia-card system specification version 2.2. see also table 96 on page 507. multimediacard bus data transfers are composed of these tokens. there are different types of operations. addressed operations always contain a command and a response token. in addition, some operations have a data token; the others transfer their information directly within the command or response structure. in this case, no data token is present in an operation. the bits on the dat and the cmd lines are transferred synchronous to the clock mcck. two types of data transfer commands are defined: sequential commands: these commands initiate a continuous data stream. they are terminated only when a stop command follows on the cmd line. this mode reduces the command overhead to an absolute minimum. block-oriented commands: these commands send a data block succeeded by crc bits. 23456 1 7 23456 1 7 23456 17 mmc1 mmc2 mmc3 mcda0 mcck mccda 23456 17 8 sd card 9 mcdb0 - mcdb3 mccdb
507 AT91RM9200 1768b?atarm?08/03 both read and write operations allow either single or multiple block transmission. a multiple block transmission is terminated when a stop command follows on the cmd line similarly to the sequential read. the mci provides a set of registers to perform the entire range of multimediacard operations. command- response operation after reset the mci is disabled and becomes valid after setting the mcien bit in the mci_cr control register. the bit pwsen allows savi ng power by dividing the mci clock by 2 power pwsdiv (mci_mr) when the bus is inactive. the command and the response of the card are clocked out with the rising edge of the mcck. all the timings for multimediacard are defined in the multimediacard system specification version 2.2. the two bus modes (open drain and push/pull) needed to process all the operations are defined in the mci command register. the mci_cmdr allows a command to be carried out. for example, to perform an all_send_cid command: the command all_send_cid and the fields and values for the mci_cmdr control register are described in table 96 and table 97. the mci_argr contains the argument field of the command. to send a command, the user must perform the following steps: fill the argument register (mci_argr) with the command argument. set the command register (mci_cmdr) (see table 97). the command is sent immediately after writing the command register. the status bit cmdrdy in the status register (mci_sr) is asserted until the command is completed. if the host command n id cycles cid or ocr cmd s t content crc e z ****** z s t content z z z table 96. all_send_cid command description cmd index type argument resp abbreviation command description cmd2 bcr [31:0] stuff bits r2 all_send_cid asks all cards to send their cid numbers on the cmd line table 97. fields and values for mci_cmdr command register field value cmdnb (command number) 2 (cmd2) rsptyp (response type) 2 (r2: 136 bits response) spcmd (special command) 0 (not a special command) opcmd (open drain command) 1 maxlat (max latency for command to response) 0 (nid cycles ==> 5 cycles) trcmd (transfer command) 0 (no transfer) trdir (transfer direction) x (available only in transfer command) trtyp (transfer type) x (available only in transfer command)
508 AT91RM9200 1768b?atarm?08/03 command requires a response, it can be read in the mci response register (mci_rspr). the response size can be 48 bits up to 136 bits according to the command. the mci embeds an error detection to prevent any corrupted data during the transfer. the following flowchart shows how to send a command to the card and read the response if needed. in this example, the status register bi ts are polled but setting the appropriate bits in the interrupt enable register (mci_ier) allows using an interrupt method. figure 240. command/response functional flow diagram note: 1. if the command is send_op_cond, the crc error flag is always present (refer to r3 response in the multimediacard specification). data transfer operation the multimedia card allows several read/wri te operations (single block, multiple blocks, stream, etc.). these operations can be done using the peripheral data controller (pdc) features. if the pdcmode bit is set in mci_mr, then all reads and writes use the pdc facilities. in all cases, the block length must be defined in the mode register. return ok return error set the command argument mci_argr = argument (1) set the command mci_cmdr = command read mci_sr cmdrdy status error flags? read response if required ye s wait for command ready status flag check error bits in the status register (1) 0 1
509 AT91RM9200 1768b?atarm?08/03 read operation the following flowchart shows how to read a single block with or without use of pdc facilities. in this example, a polling method is used to wait for the end of read. similarly, the user can configure the interrupt enable register (mci_ier) to trigger an interrupt at the end of read. these two methods can be applied for all multimediacard read functions. figure 241. read functional flow diagram read status register mci_sr send command sel_desel_card to select the card send command set_blocklen read with pdc reset the pdcmode bit mci_mr &= ~pdcmode set the block length mci_mr |= (blocklenght <<16) number words read = blocklength/4 poll the bit rxrdy = 0? read data = mci_rdr send command read_single_block yes set the pdcmode bit mci_mr |= pdcmode set the block length mci_mr |= (blocklength << 16) configure the pdc channel pdc_rpr = data buffer address pdc_rcr = blocklength/4 pdc2_ptcr = pdc_rxten send command read_single_block read status register mci_sr poll the bit endrx = 0? yes return return yes no no no
510 AT91RM9200 1768b?atarm?08/03 write operation in write operation the mci mode register (mci_mr) is used to define the padding value when writing non-multiple block size. if the bit pdcpadv is 0, then 0x00 value is used when pad- ding data, otherwise 0xff is used. if set, the bit pdcmode enables pdc transfer. the following flowchart shows how to write a single block with or without use of pdc facilities. polling or interrupt method can be used to wait for the end of write according to the contents of the interrupt mask register (mci_imr). this flowchart can be adapted to perform all the multimedia card write functions. figure 242. write functional flow diagram read status register mci_sr send command sel_desel_card to select the card send command set_blocklen write using pdc reset the pdcmode bit mci_mr &= ~pdcmode set the block length mci_mr |= (blocklenght <<16) number words write = blocklength/4 poll the bit txrdy = 0? mci_tdr = data to write send command write_single_block yes set the pdcmode bit mci_mr |= pdcmode set the block length mci_mr |= (blocklength << 16) configure the pdc channel pdc_tpr = data buffer address to write pdc_tcr = blocklength/4 pdc2_ptcr = pdc_txten send command write_single_block read status register mci_sr poll the bit endtx = 0? yes return return no yes yes no no no
511 AT91RM9200 1768b?atarm?08/03 sd card operations the multimedia card interface allows processing of sd memory card (secure digital memory card) commands. the sd memory card will include a copyright protection mechanism that complies with the security requirements of the sdmi standard, is faster and applicable to higher memory capacity. the physical form factor, pin assignment and data transfer protocol are forward-com-patible with the multimedia card with some additions. the sd memory card communication is based on a 9-pin interface (clock, command, 4 x data and 3 x power lines). the communication protocol is defined as a part of this specifi- cation. the main difference between the sd memory card and the multimedia card is the initialization process. the sd card control register (mci_sdcr) allows selection of the card slot and the data bus width. the sd card bus allows dynamic configuration of the number of data lines. after power up, by default, the sd memory card will use only dat0 for data transfer. after initialization, the host can change the bus width (number of active data lines).
512 AT91RM9200 1768b?atarm?08/03 multimedia card (mci) user interface note: 1. the response register can be read by n accesses at the same mci_rspr or at consecutive addresses (0x20 to 0x2c). n depends on the size of the response. table 98. mci register mapping offset register register name read/write reset 0x00 control register mci_cr write --- 0x04 mode register mci_mr read/write 0x0 0x08 data timeout register mci_dtor read/write 0x0 0x0c sd card register mci_sdcr read/write 0x0 0x10 argument register mci_argr read/write 0x0 0x14 command register mci_cmdr write --- 0x18 - 0x1c reserved 0x20 response register (1) mci_rspr read 0x0 0x24 response register (1) mci_rspr read 0x0 0x28 response register (1) mci_rspr read 0x0 0x2c response register (1) mci_rspr read 0x0 0x30 receive data register mci_rdr read 0x0 0x34 transmit data register mci_tdr write --- 0x38 - 0x3c reserved 0x40 status register mci_sr read 0xc0e5 0x44 interrupt enable register mci_ier write --- 0x48 interrupt disable register mci_idr write --- 0x4c interrupt mask register mci_imr read 0x0 0x50-0xff reserved 0x100-0x124 reserved for the pdc
513 AT91RM9200 1768b?atarm?08/03 mci control register register name: mci_cr access type: write-only mcien: multi-media interface enable 0 = no effect. 1 = enables the multi-media interface if mcdis is 0. mcidis: multi-media interface disable 0 = no effect. 1 = disables the multi-media interface. pwsen: power save mode enable 0 = no effect. 1 = enables the power saving mode if pwsdis is 0. pwsdis: power save mode disable 0 = no effect. 1 = disables the power saving mode. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ? ? pwsdis pwsen mcidis mcien
514 AT91RM9200 1768b?atarm?08/03 mci mode register name: mci_mr access type: read/write clkdiv: clock divider multi-media card interface clock (mcck) is master clock (mck) divided by (2*(clkdiv+1)). pwsdiv: power saving divider multimedia card interface clock is divided by 2 (pwsdiv) when entering power saving mode. pdcpadv: pdc padding value 0 = 0x00 value is used when padding data in write transfer (not only pdc transfer). 1 = 0xff value is used when padding data in write transfer (not only pdc transfer). pdcmode: pdc-oriented mode 0 = disables pdc transfer 1 = enables pdc transfer. in this case, unre and ovre (mci_sr) are deactivated. blklen: data block length this field determines the size of the data block. bits 16 and 17 must be 0. 31 30 29 28 27 26 25 24 ? ? blklen 23 22 21 20 19 18 17 16 blklen 0 0 15 14 13 12 11 10 9 8 pdcmode pdcpadv ? ? ? pwsdiv 76543210 clkdiv
515 AT91RM9200 1768b?atarm?08/03 mci data timeout register name: mci_dtor access type: read/write dtocyc: data timeout cycle number dtomul: data timeout multiplier these fields determine the maximum number of master clock cycles that the mci waits between two data block transfers. it equals (dtocyc x multiplier). multiplier is defined by dtomul as shown in the following table: 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?dtomul dtocyc dtomul multiplier 0001 00116 0 1 0 128 0 1 1 256 1 0 0 1024 1 0 1 4096 1 1 0 65536 1 1 1 1048576
516 AT91RM9200 1768b?atarm?08/03 mci sd card register name: mci_sdcr access type: read/write sdcsel: sd card selector 0 = sd card a selected. 1 = sd card b selected. sdcbus 0 = 1-bit data bus 1 = 4-bit data bus mci argument register name: mci_argr access type: read/write arg: command argument 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 sdcbus ? ? ? sdcsel 31 30 29 28 27 26 25 24 arg 23 22 21 20 19 18 17 16 arg 15 14 13 12 11 10 9 8 arg 76543210 arg
517 AT91RM9200 1768b?atarm?08/03 mci command register name: mci_cmdr access type: write-only this register is write-protected while cmdrdy is 0 in mci_sr and in the case of a no interrupt command sent (bit spcmd). this means that the current command execution cannot be interrupted or modified. cmdnb: command number rsptyp: response type spcmd: special cmd opdcmd: open drain command 0 = push pull command 1 = open drain command 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ? ? ? ? trtype trdir trcmd 15 14 13 12 11 10 9 8 ? ? ? maxlat opdcmd spcmd 76543210 rsptyp cmdnb rsp response type 0 0 no response. 0 1 48-bit response. 1 0 136-bit response. 1 1 reserved. spcmd cmd 0 0 0 not a special cmd. 0 0 1 initialization cmd: 74 clock cycles for initialization sequence. 0 1 0 synchronized cmd: wait for the end of the current data block transfer before sending the pending command. 0 1 1 reserved. 1 0 0 interrupt command: corresponds to the interrupt mode (cmd40). 1 0 1 interrupt response: corresponds to the interrupt mode (cmd40).
518 AT91RM9200 1768b?atarm?08/03 maxlat: max latency for command to response 0 =5-cycle max latency 1 = 64-cycle max latency trcmd: transfer command trdir: transfer direction 0 = write 1 = read trtyp: transfer type mci sd response register name: mci_rspr access type: read-only rsp: response trcmd transfer type 0 0 no transfer. 0 1 start transfer. 1 0 stop transfer. 1 1 reserved. trtyp transfer type 00block. 0 1 multiple block. 10stream. 1 1 reserved. 31 30 29 28 27 26 25 24 rsp 23 22 21 20 19 18 17 16 rsp 15 14 13 12 11 10 9 8 rsp 76543210 rsp
519 AT91RM9200 1768b?atarm?08/03 mci sd receive data register name: mci_rdr access type: read-only data: data to read mci sd transmit data register name: mci_tdr access type: write-only data: data to write 31 30 29 28 27 26 25 24 data 23 22 21 20 19 18 17 16 data 15 14 13 12 11 10 9 8 data 76543210 data 31 30 29 28 27 26 25 24 data 23 22 21 20 19 18 17 16 data 15 14 13 12 11 10 9 8 data 76543210 data
520 AT91RM9200 1768b?atarm?08/03 mci status register name: mci_sr access type: read-only cmdrdy: command ready 0 = a command is in progress. 1 = the last command has been sent. cleared when writing in the mci_cmdr. rxrdy: receiver ready 0 = data has not yet been received since the last read of mci_rdr. 1 = data has been received since the last read of mci_rdr. txrdy: transmit ready 0= the last data written in mci_tdr has not yet been transferred in the shift register. 1= the last data written in mci_tdr has been transferred in the shift register. blke: data block ended 0 = a data block transfer is not yet finished. 1 = a data block transfer has ended. set at the end of the last block in pdcmode, otherwise at the end of the first block. cleared when reading the mci_sr. dtip: data transfer in progress 0 = no data transfer in progress. 1 = the current data transfer is still in progress, including crc16 calculation. cleared at the end of the crc16 calculation. notbusy: data not busy 0 = the card is not ready for new data transfer. 1 = the card is ready for new data transfer (data line dat0 high corresponding to a free data receive buffer in the card). endrx: end of rx buffer 0 = the receive counter re g ister has not reached 0 since the last write in mci_rcr or mci_rncr. 1 = the receive counter re g ister has reached 0 since the last write in mci_rcr or mci_rncr. endtx: end of tx buffer 0 = the transmit counter re g ister has not reached 0 since the last write in mci_tcr or mci_tncr. 1 = the transmit counter re g ister has reached 0 since the last write in mci_tcr or mci_tncr. rxbuff: rx buffer full 0 = mci_rcr or mci_rncr has a value other than 0. 1 = both mci_rcr and mci_rncr have a value of 0. txbufe: tx buffer empty 0 = mci_tcr or mci_tncr has a value other than 0. 1 = both mci_tcr and mci_tncr have a value of 0. 31 30 29 28 27 26 25 24 unre ovre ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? dtoe tcrce rtoe rende rcrce rdire rinde 15 14 13 12 11 10 9 8 txbufe rxbuff ? ? ? ? ? ? 76543210 endtx endrx notbusy dtip blke txrdy rxrdy cmdrdy
521 AT91RM9200 1768b?atarm?08/03 rinde: response index error 0 = no error. 1 = a mismatch is detected between the command index sent and the response index received. cleared when writing in the mci_cmdr. rdire: response direction error 0 = no error. 1 = the direction bit from card to host in the response has not been detected. rcrce: response crc error 0 = no error. 1 = a crc7 error has been detected in the response. cleared when writing in the mci_cmdr. rende: response end bit error 0 = no error. 1 = the end bit of the response has not been detected. cleared when writing in the mci_cmdr. rtoe: response time-out error 0 = no error. 1 = the response time-out set by maxlat in the mci_cmdr has been exceeded. cleared when writing in the mci_cmdr. dcrce: data crc error 0 = no error. 1 = a crc16 error has been detected in the last data block. cleared when sending a new data transfer command. dtoe: data time-out error 0 = no error. 1 = the data time-out set by dtocyc and dtomul in mci_dtor has been exceeded. cleared when writing in the mci_cmdr. ovre: overrun 0 = no error. 1 = at least one 8-bit received data has been lost (not read). cleared when sending a new data transfer command. unre: underrun 0 = no error. 1 = at least one 8-bit data has been sent without valid information (not written). cleared when sending a new data transfer command.
522 AT91RM9200 1768b?atarm?08/03 mci interrupt enable register name: mci_ier access type: write-only cmdrdy: command ready interrupt enable rxrdy: receiver ready interrupt enable txrdy: transmit ready interrupt enable blke: data block ended interrupt enable dtip: data transfer in progress interrupt enable notbusy: data not busy interrupt enable endrx: end of receive buffer interrupt enable endtx: end of transmit buffer interrupt enable rxbuff: receive buffer full interrupt enable txbufe: transmit buffer empty interrupt enable rinde: response index error interrupt enable rdire: response direction error interrupt enable rcrce: response crc error interrupt enable rende: response end bit error interrupt enable rtoe: response time-out error interrupt enable dcrce: data crc error interrupt enable dtoe: data time-out error interrupt enable ovre: overrun interrupt enable unre: underrun interrupt enable 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 unre ovre ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? dtoe tcrce rtoe rende rcrce rdire rinde 15 14 13 12 11 10 9 8 txbufe rxbuff ? ? ? ? ? ? 76543210 endtx endrx notbusy dtip blke txrdy rxrdy cmdrdy
523 AT91RM9200 1768b?atarm?08/03 mci interrupt disable register name: mci_idr access type: write-only cmdrdy: command ready interrupt disable rxrdy: receiver ready interrupt disable txrdy: transmit ready interrupt disable blke: data block ended interrupt disable dtip: data transfer in progress interrupt disable notbusy: data not busy interrupt disable endrx: end of receive buffer interrupt disable endtx: end of transmit buffer interrupt disable rxbuff: receive buffer full interrupt disable txbufe: transmit buffer empty interrupt disable rinde: response index error interrupt disable rdire: response direction error interrupt disable rcrce: response crc error interrupt disable rende: response end bit error interrupt disable rtoe: response time-out error interrupt disable dcrce: data crc error interrupt disable dtoe: data time-out error interrupt disable ovre: overrun interrupt disable unre: underrun interrupt disable 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 unre ovre ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? dtoe tcrce rtoe rende rcrce rdire rinde 15 14 13 12 11 10 9 8 txbufe rxbuff ? ? ? ? ? ? 76543210 endtx endrx notbusy dtip blke txrdy rxrdy cmdrdy
524 AT91RM9200 1768b?atarm?08/03 mci interrupt mask register name: mci_imr access type: read-only cmdrdy: command ready interrupt mask rxrdy: receiver ready interrupt mask txrdy: transmit ready interrupt mask blke: data block ended interrupt mask dtip: data transfer in progress interrupt mask notbusy: data not busy interrupt mask endrx: end of receive buffer interrupt mask endtx: end of transmit buffer interrupt mask rxbuff: receive buffer full interrupt mask txbufe: transmit buffer empty interrupt mask rinde: response index error interrupt mask rdire: response direction error interrupt mask rcrce: response crc error interrupt mask rende: response end bit error interrupt mask rtoe: response time-out error interrupt mask dcrce: data crc error interrupt mask dtoe: data time-out error interrupt mask ovre: overrun interrupt mask unre: underrun interrupt mask 0 = the corresponding interrupt is not enabled. 1 = the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 unre ovre ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? dtoe tcrce rtoe rende rcrce rdire rinde 15 14 13 12 11 10 9 8 txbufe rxbuff ? ? ? ? ? ? 76543210 endtx endrx notbusy dtip blke txrdy rxrdy cmdrdy
525 AT91RM9200 1768b?atarm?08/03 usb device port (udp) overview the usb device port (udp) is compliant with the universal serial bus (usb) v2.0 full-speed device specification. it is designed to be associated with atmel?s embedded usb transceiver and interfaced with an arm7tdmi and arm9tdmi core . the number and size of endpoints is product-dependent. each endpoint is associated with one or two banks of a dual-port ram used to store the current data payload. if two banks are used, one dpr bank is read or written by the processor, while the other is read or written by the usb device peripheral. this feature is ma ndatory for isochronous endpoints. thus the device maintains the maximum bandwidth (1m bytes/s) by working with endpoints with two banks of dpr. suspend and resume are automatically detected by the usb device, which notifies the pro- cessor by raising an interrupt. depending on the product, an external signal can be used to send a wake-up to the usb host controller. the main features of the udp are: usb v2.0 full-speed compliant, 12 mbits per second embedded usb v2.0 full-speed transceiver number and size of endpoints fully parametrizable in rtl embedded dual-port ram for endpoints suspend/resume logic ping-pong mode (2 memory banks) for isochronous and bulk endpoints
526 AT91RM9200 1768b?atarm?08/03 block diagram figure 243. usb device port block diagram access to the udp is via the apb bus interface. read and write to the data fifo are done by reading and writing 8-bit values to apb registers. the udp peripheral requires two clocks: one peripheral clock used by the mck domain and a 48 mhz clock used by the 12 mhz domain. a usb 2.0 full-speed pad is embedded and controlled by the sie. the signal external_resume is optional. it allows the udp peripheral to wake-up once in sys- tem mode. the host will then be notified that the device asks for a resume. this optional feature must be also negotiated with the host during the enumeration. atmel bridge 12 mhz suspend/resume logic w r a p p e r w r a p p e r u s e r i n t e r f a c e serial interface engine sie mck master clock domain dual port ram fifo udpck recovered 12 mhz domain udp_int usb device embedded usb transceiver dp dm external resume apb to mcu bus txoen eopn txd rxdm rxd rxdp
527 AT91RM9200 1768b?atarm?08/03 product dependencies the usb physical transceiver is integrated into the product. the bi-directional differential sig- nals dp and dm are available from the product boundary. two i/o lines may be used by the application: one to check that vbus is still available from the host. self-powered devices may use this entry to be notified that the host has been powered off. in this case, the board pull-up on dp must be disabled in order to prevent feeding current to the host. one to control the board pull-up on dp. thus, when the device is ready to communicate with the host, it activates its dp pull-up through this control line. i/o lines dp and dm are not controlled by any pio controllers. the embedded usb physical trans- ceiver is controlled by the usb device peripheral. to reserve an i/o line to check vbus, the programmer must first program the pio controller to assign this i/o in input pio mode. to reserve an i/o line to control the board pull-up, the programmer must first program the pio controller to assign this i/o in output pio mode. power management the usb device peripheral requires a 48 mhz clock. this clock must be generated by a pll with an accuracy of 0.25%. thus, the usb device receives two clocks from the power management controller (pmc): the master clock, mck, used to drive the peripheral user interface and the udpck used to inter- face with the bus usb signals (recovered 12 mhz domain). interrupt the usb device interface has an interrupt line connected to the advanced interrupt controller (aic). handling the usb device interrupt requires programming the aic before configuring the udp.
528 AT91RM9200 1768b?atarm?08/03 typical connection figure 244. board schematic to interface usb device peripheral usb_cnx is an input signal used to check if the host is connected usb_dp_pup is an output signal used to enable pull-up on dp. figure 244 shows automatic activation of pull-up after reset. 3v3 15pf 15pf 27 ? 33pf 15k ? 47k ? 100nf ddm ddp pan pam system reset 15k ? 22k ? 27 ? type b connector
529 AT91RM9200 1768b?atarm?08/03 functional description usb v2.0 full- speed introduction the usb v2.0 full-speed provides communicati on services between host and attached usb devices. each device is offered with a collection of communication flows (pipes) associated with each endpoint. software on the host communicates with an usb device through a set of communication flows. figure 245. example of usb v2.0 full-speed communication control usb v2.0 full-speed transfer types a communication flow is carried over one of four transfer types defined by the usb device. table 99. usb communication flow transfer direction bandwidth endpoint size error detection retrying control bi-directional not guaranteed 8, 16, 32, 64 yes automatic isochronous uni-directional guaranteed 1 - 1023 yes no interrupt uni-directional not guaranteed 64 yes yes bulk uni-directional not guaranteed 8, 16, 32, 64 yes yes ep0 usb host v1.1 software client 1 software client 2 data flow: bulk out transfer data flow: bulk in transfer data flow: control transfer data flow: control transfer ep1 ep2 usb device 1.1 block 1 usb device 1.1 block 2 ep5 ep4 ep0 data flow: isochronous in transfer data flow: isochronous out transfer
530 AT91RM9200 1768b?atarm?08/03 usb bus transactions each transfer results in one or more transacti ons over the usb bus. there are five kinds of transactions flowing across the bus in packets: 1. setup transaction 2. data in transaction 3. data out transaction 4. status in transaction 5. status out transaction usb transfer event definitions as shown in table 100, transfers are sequential events carried out on the usb bus. notes: 1. control transfer must use endpoints with no ping-pong attributes. 2. isochronous transfers must use endpoints with ping-pong attributes. 3. control transfers can be aborted using a stall handshake. table 100. usb transfer events control transfers (1) (3) setup transaction > data in transactions > status out transaction setup transaction > data out transactions > status in transaction setup transaction > status in transaction interrupt in transfer (device toward host) data in transaction > data in transaction interrupt out transfer (host toward device) data out transaction > data out transaction isochronous in transfer (2) (device toward host) data in transaction > data in transaction isochronous out transfer (2) (host toward device) data out transaction > data out transaction bulk in transfer (device toward host) data in transaction > data in transaction bulk out transfer (host toward device) data out transaction > data out transaction
531 AT91RM9200 1768b?atarm?08/03 handling transactions with us b v2.0 device peripheral setup transaction setup is a special type of host-to-device trans action used during control transfers. control transfers must be performed using endpoints with no ping-pong attributes. a setup transaction needs to be handled as soon as possible by the firmware. it is used to transmit requests from the host to the device. these requests are then handled by the usb device and may require more arguments. the arguments are sent to the device by a data out transaction which fol- lows the setup transaction. these requests may also return data. the data is carried out to the host by the next data in transaction which follows the setup transaction. a status transaction ends the control transfer. when a setup transfer is received by the usb endpoint: the usb device automatically acknowledges the setup packet rxsetup is set in the usb_csrx register an endpoint interrupt is generated while the rxsetup is not cleared. this interrupt is carried out to the microcontroller if interrupts are enabled for this endpoint. thus, firmware must detect the rxsetup polling the usb_csrx or catching an interrupt, read the setup packet in the fifo, then clear the rxsetup. rxsetup cannot be cleared before the setup packet has been read in the fifo. otherwise, the usb device would accept the next data out transfer and overwrite the setup packet in the fifo. figure 246. setup transaction followed by a data out transaction rx_data_bko (usb_csrx) ack pid data out data out pid nak pid ack pid data setup setup pid usb bus packets rxsetup flag set by usb device cleared by firmware set by usb device peripheral fifo (dpr) content data setup data xx xx out interrupt pending setup received setup handled by firmware data out received data out data out pid
532 AT91RM9200 1768b?atarm?08/03 data in transaction data in transactions are used in control, isochronous, bulk and interrupt transfers and conduct the transfer of data from the device to the host. data in transactions in isochronous transfer must be done using endpoints with ping-pong attributes. using endpoints without ping-pong attributes to perform a data in transaction, using a non ping-pong endpoint: 1. the microcontroller checks if it is possible to write in the fifo by polling txpktrdy in the endpoint?s usb_csrx register (txpktrdy must be cleared). 2. the microcontroller writes data to be sent in the endpoint?s fifo, writing zero or more byte values in the endpoint?s usb_fdrx register, 3. the microcontroller notifies the usb peripheral it has finished by setting the txpk- trdy in the endpoint?s usb_csrx register, 4. the microcontroller is notified that the endpoint?s fifo has been released by the usb device when txcomp in the endpoint?s usb_csrx register has been set. then an interrupt for the corresponding endpoint is pending while txcomp is set. txcomp is set by the usb device when it has received an ack pid signal for the data in packet. an interrupt is pending while txcomp is set. note: please refer to chapter 8 of the universal serial bus specification, rev 1.1, for more informa- tion on the data in protocol layer. figure 247. data in transfer for non ping-pong endpoint usb bus packets data in 2 data in nak ack data in 1 fifo (dpr) content load in data in 2 load in progress data in 1 cleared by firmware start to write data payload in fifo set by the firmware data payload written in fifo txcomp flag (usb_csrx) txpktrdy flag (usb_csrx) cleared by usb device pid data in data in pid pid pid pid ack pid progress prevous data in tx microcontroller load data in fifo data is sent on usb bus interrupt pending interrupt pending
533 AT91RM9200 1768b?atarm?08/03 using endpoints with ping-pong attribute the use of an endpoint with ping-pong attributes is necessary during isochronous transfer. to be able to guarantee a constant bandwidth, the microcontroller must prepare the next data payload to be sent while the current one is being sent by the usb device. thus two banks of memory are used. while one is available for the microcontroller, the other one is locked by the usb device. figure 248. bank swapping data in transfer for ping-pong endpoints when using a ping-pong endpoint, the following pr ocedures are required to perform data in transactions: 1. the microcontroller checks if it is possible to write in the fifo by polling txpktrdy to be cleared in the endpoint?s usb_csrx register. 2. the microcontroller writes the first data payload to be sent in the fifo (bank 0), writing zero or more byte values in the endpoint?s usb_fdrx register. 3. the microcontroller notifies the usb peripheral it has finished writing in bank 0 of the fifo by setting the txpktrdy in the endpoint?s usb_csrx register. 4. without waiting for txpktrdy to be cleared, the microcontroller writes the second data payload to be sent in the fifo (bank 1), writing zero or more byte values in the endpoint?s usb_fdrx register. 5. the microcontroller is notified that the first bank has been released by the usb device when txcomp in the endpoint?s usb_csrx register is set. an interrupt is pending while txcomp is being set. 6. once the microcontroller has received txcomp for the first bank, it notifies the usb device that it has prepared the second bank to be sent rising txpktrdy in the end- point?s usb_csrx register. 7. at this step, bank 0 is available and the microcontroller can prepare a third data pay- load to be sent . usb device usb bus read write read and write at the same time 1 st data payload 2 nd data payload 3 rd data payload 3 rd data payload 2 nd data payload 1 st data payload data in packet data in packet data in packet microcontroller endpoint 1 bank 0 endpoint 1 bank 1 endpoint 1 bank 0 endpoint 1 bank 0 endpoint 1 bank 0 endpoint 1 bank 1
534 AT91RM9200 1768b?atarm?08/03 figure 249. data in transfer for ping-pong endpoint warning: there is software critical path due to the fact that once the second bank is filled, the driver has to wait for tx_comp to set tx_pktrdy. if the delay between receiving tx_comp is set and tx_pktrdy is set is too long, some data in packets may be nacked, reducing the bandwidth. data in data in read by usb device read by usb device bank 1 bank 0 fifo (dpr) txcomp flag (usb_csrx) interrupt cleared by firmware set by usb device txpktrdy flag (usb_mcsrx) ack pid data in pid ack pid set by firmware, data payload written in fifo bank 1 cleared by usb device, data payload fully transmitted data in pid usb bus packets set by usb device set by firmware, data payload written in fifo bank 0 written by fifo (dpr) microcontroller written by microcontroller written by microcontroller microcontroller load data in bank 0 microcontroller load data in bank 1 usb device send bank 0 microcontroller load data in bank 0 usb device send bank 1 interrupt pending
535 AT91RM9200 1768b?atarm?08/03 data out transaction data out transactions are used in control, isochronous, bulk and interrupt transfers and con- duct the transfer of data from the host to the device. data out transactions in isochronous transfers must be done using endpoints with ping-pong attributes. data out transaction without ping-pong attributes to perform a data out transaction, using a non ping-pong endpoint: 1. the host generates a data out packet. 2. this packet is received by the usb device endpoint. while the fifo associated to this endpoint is being used by the microcontroller, a nak pid is returned to the host. once the fifo is available, data are written to the fifo by the usb device and an ack is automatically carried out to the host. 3. the microcontroller is notified that the usb device has received a data payload polling rx_data_bk0 in the endpoint?s usb_csrx register. an interrupt is pending for this endpoint while rx_data_bk0 is set. 4. the number of bytes available in the fifo is made available by reading rxbytecnt in the endpoint?s usb_csrx register. 5. the microcontroller carries out data received from the endpoint?s memory to its mem- ory. data received is available by reading the endpoint?s usb_fdrx register. 6. the microcontroller notifies the usb device that it has finished the transfer by clearing rx_data_bk0 in the endpoint?s usb_csrx register. 7. a new data out packet can be accepted by the usb device. figure 250. data out transfer for non ping-pong endpoints an interrupt is pending while the flag rx_data_bk0 is set. memory transfer between the usb device, the fifo and microcontroller memory can not be done after rx_data_bk0 has been cleared. otherwise, the usb device would accept the next data out transfer and over- write the current data out packet in the fifo. ack pid data out nak pid pid pid pid pid data out2 ack data out data out 1 usb bus packets rx_data_bk0 set by usb device cleared by firmware, data payload written in fifo fifo (dpr) content written by usb device microcontroller read data out 1 data out 1 data out 2 host resends the next data payload microcontroller transfers data host sends data payload data out2 data out2 host sends the next data payload written by usb device (usb_csrx) interrupt pending
536 AT91RM9200 1768b?atarm?08/03 using endpoints with ping-pong attributes during isochronous transfer, using an endpoint with ping-pong attributes is necessary. to be able to guarantee a constant bandwidth, the microcontroller must read the previous data pay- load sent by the host, while the current data payload is received by the usb device. thus two banks of memory are used. while one is available for the microcontroller, the other one is locked by the usb device. figure 251. bank swapping in data out transfers for ping-pong endpoints when using a ping-pong endpoint, the following procedures are required to perform data out transactions: 1. the host generates a data out packet. 2. this packet is received by the usb device endpoint. it is written in the endpoint?s fifo bank 0. 3. the usb device sends an ack pid packet to the host. the host can immediately send a second data out packet. it is accepted by the device and copied to fifo bank 1. 4. the microcontroller is notified that the usb device has received a data payload, polling rx_data_bk0 in the endpoint?s usb_csrx register. an interrupt is pending for this endpoint while rx_data_bk0 is set. 5. the number of bytes available in the fifo is made available by reading rxbytecnt in the endpoint?s usb_csrx register. 6. the microcontroller transfers out data received from the endpoint?s memory to the microcontroller?s memory. data received is made available by reading the endpoint?s usb_fdrx register. 7. the microcontroller notifies the usb peripheral device that it has finished the transfer by clearing rx_data_bk0 in the endpoint?s usb_csrx register. 8. a third data out packet can be accepted by the usb peripheral device and copied in the fifo bank 0. 9. if a second data out packet has been received, the microcontroller is notified by the flag rx_data_bk1 set in the endpoint?s usb_csrx register. an interrupt is pending for this endpoint while rx_data_bk1 is set. usb device usb bus read write write and read at the same time 1 st data payload 2 nd data payload 3 rd data payload 3 rd data payload 2 nd data payload 1 st data payload data in packet data in packet data in packet microcontroller endpoint 1 bank 0 endpoint 1 bank 1 endpoint 1 bank 0 endpoint 1 bank 0 endpoint 1 bank 0 endpoint 1 bank 1
537 AT91RM9200 1768b?atarm?08/03 10. the microcontroller transfers out data received from the endpoint?s memory to the microcontroller?s memory. data received is available by reading the endpoint?s usb_fdrx register. 11. the microcontroller notifies the usb device it has finished the transfer by clearing rx_data_bk1 in the endpoint?s usb_csrx register. 12. a fourth data out packet can be accepted by the usb device and copied in the fifo bank 0. figure 252. data out transfer for ping-pong endpoint note: an interrupt is pending while the rx_data_bk0 or rx_data_bk1 flag is set. warning : when rx_data_bk0 and rx_data_bk1 are both set, there is no way to deter- mine which one to clear first. thus the software must keep an internal counter to be sure to clear alternatively rx_data_bk0 then rx_data_bk1. this situation may occur when the software application is busy elsewhere and the two banks are filled by the usb host. once the application comes back to the usb driver, the two flags are set. a p data out pid ack data out 3 data out data out 2 data out data out 1 pid data out 3 data out 1 data out1 data out 2 data out 2 pid pid pid ack cleared by firmware usb bus packets rx_data_bk0 flag rx_data_bk1 flag set by usb device, data payload written in fifo endpoint bank 1 fifo (dpr) bank 0 bank 1 write by usb device write in progress read by microcontroller read by microcontroller set by usb device, data payload written in fifo endpoint bank 0 host sends first data payload microcontroller reads data 1 in bank 0, host sends second data payload microcontroller reads data2 in bank 1, host sends third data payload cleared by firmware write by usb device fifo (dpr) (usb_csrx) (usb_csrx) interrupt pending interrupt pending
538 AT91RM9200 1768b?atarm?08/03 status transaction a status transaction is a special type of host to device transaction used only in a control trans- fer. the control transfer must be performed using endpoints with no ping-pong attributes. according to the control sequence (read or write), the usb device sends or receives a status transaction. figure 253. control read and write sequences notes: 1. during the status in stage, the host waits for a zero length packet (data in transaction with no data) from the device using data1 pid. please refer to chapter 8 of the universal serial bus specification, rev. 1.1, to get more information on the protocol layer. 2. during the status out stage, the host emits a zero length packet to the device (data out transaction with no data). control read setup tx data out tx data out tx data stage control write setup stage setup stage setup tx setup tx no data control data in tx data in tx status stage status stage status in tx status out tx status in tx data stage setup stage status stage
539 AT91RM9200 1768b?atarm?08/03 status in transfer once a control request has been processed, the device returns a status to the host. this is a zero length data in transaction. 1. the microcontroller waits for txpktrdy in the usb_csrx endpoint?s register to be cleared. (at this step, txpktrdy must be cleared because the previous transaction was a setup transaction or a data out transaction.) 2. without writing anything to the usb_fdrx endpoint?s register, the microcontroller sets txpktrdy. the usb device generates a data in packet using data1 pid. 3. this packet is acknowledged by the host and txpktrdy is set in the usb_csrx end- point?s register. figure 254. data out followed by status in transfer. data in nak data out data out ack pid pid pid pid usb bus packets rx_data_bko (usb_csrx) cleared by firmware set by usb device cleared by usb device txpktrdy (usb_csrx) set by firmware host sends the last data payload to the device device sends a status in to the host interrupt pending
540 AT91RM9200 1768b?atarm?08/03 status out transfer once a control request has been processed and the requested data returned, the host acknowledges by sending a zero length packet. this is a zero length data out transaction. 1. the usb device receives a zero length packet. it sets rx_data_bk0 flag in the usb_csrx register and acknowledges the zero length packet. 2. the microcontroller is notified that the usb device has received a zero length packet sent by the host polling rx_data_bk0 in the usb_csrx register. an interrupt is pending while rx_data_bk0 is set. the number of bytes received in the endpoint?s usb_bcr register is equal to zero. 3. the microcontroller must clear rx_data_bk0. figure 255. data in followed by status out transfer data out data in data in ack pid pid pid ack pid rx_data_bko (usb_csrx) txcomp (usb_csrx) set by usb device usb bus packets cleared by firmware cleared by firmware set by usb device device sends a status out to host device sends the last data payload to host interrupt pending
541 AT91RM9200 1768b?atarm?08/03 stall handshake a stall handshake can be used in one of two distinct occasions. (for more information on the stall handshake, refer to chapter 8 of the universal serial bus specification, rev 1.1. ) a functional stall is used when the halt feature associated with the endpoint is set. (refer to chapter 9 of the universal serial bus specification, rev 1.1, for more information on the halt feature.) to abort the current request, a protocol stall is used, but uniquely with control transfer. the following procedure generates a stall packet: 1. the microcontroller sets the forcestall flag in the usb_csrx endpoint?s register. 2. the host receives the stall packet. 3. the microcontroller is notified that the device has sent the stall by polling the stallsent to be set. an endpoint interrupt is pending while stallsent is set. the microcontroller must clear stallsent to clear the interrupt. when a setup transaction is received after a stall handshake, stallsent must be cleared in order to prevent interrupts due to stallsent being set. figure 256. stall handshake (data in transfer) figure 257. stall handshake (data out transfer) data in stall pid pid usb bus packets cleared by firmware set by firmware forcestall stallsent set by usb device cleared by firmware interrupt pending data out pid stall pid data out usb bus packets cleared by firmware set by firmware forcestall stallsent set by usb device interrupt pending
542 AT91RM9200 1768b?atarm?08/03 controlling device states a usb device has several possible states. please refer to chapter 9 of the universal serial bus specification, rev 1.1 . figure 258. usb device state diagram movement from one state to another depends on the usb bus state or on standard requests sent through control transactions via the default endpoint (endpoint 0). after a period of bus inactivity, the udp device enters suspend mode. accepting sus- pend/resume requests from the usb host is mandatory. constraints in suspend mode are very strict for bus-powered applications; devices may not consume more than 500 ua on the usb bus. while in suspend mode, the host may wake up a device by sending a resume signal (bus activity) or a usb device may send a wake-up request to the host, e.g., waking up a pc by moving a usb mouse. the wake-up feature is not mandatory for all devices and must be negotiated with the host. attached suspended suspended suspended suspended hub reset or deconfigured hub configured bus inactive bus activity bus inactive bus activity bus inactive bus activity bus inactive bus activity reset reset address assigned device deconfigured device configured powered default address configured power interruption
543 AT91RM9200 1768b?atarm?08/03 from powered state to default state after its connection to a usb host, the usb device waits for an end-of-bus reset. the usb host stops driving a reset state once it has detected the device?s pull-up on dp. the unmasked flag endburst is set in the register udp_isr and an interrupt is triggered. the udp soft- ware enables the default endpoint, setting the epeds flag in the udp_csr[0] register and, optionally, enabling the interrupt for endpoint 0 by writing 1 to the udp_ier register. the enu- meration then begins by a control transfer. from default state to address state after a set address standard device request, the usb host peripheral enters the address state. before this, it achieves the st atus in transaction of the cont rol transfer, i.e., the udp device sets its new address once the txcomp flag in the udp_csr[0] register has been received and cleared. to move to address state, the driver software sets the fadden flag in the udp_glb_state, sets its new address, and sets the fen bit in the udp_faddr register. from address state to configured state once a valid set configuration standard request has been received and acknowledged, the device enables endpoints corresponding to the current configuration. this is done by setting the epeds and eptype fields in the udp_csrx registers and, optionally, enabling corre- sponding interrupts in the udp_ier register. enabling suspend when a suspend (no bus activity on the usb bus ) is detected, the rxsusp signal in the udp_isr register is set. this triggers an interrupt if the corresponding bit is set in the udp_imr register. this flag is cleared by writing to the udp_icr register. then the device enters suspend mode. as an example, the microcontroller switches to slow clock, disables the pll and main oscillator, and goes into idle mode. it may also switch off other devices on the board. the usb device peripheral clocks may be switched off. however, the transceiver and the usb peripheral must not be switched off, otherwise the resume is not detected. receiving a host resume in suspend mode, the usb transceiver and the usb peripheral must be powered to detect the resume. however, the usb device peripheral may not be clocked as the wakeup signal is asynchronous. once the resume is detected on the bus, the si gnal wakeup in the udp_isr is set. it may generate an interrupt if the corresponding bit in the udp_imr register is set. this interrupt may be used to wake-up the core, enable pll and main oscillators and configure clocks. the wakeup bit must be cleared as soon as possible by setting wakeup in the udp_icr register. sending an external resume the external resume is negotiated with the host and enabled by setting the esr bit in the usb_glb_state. an asynchronous event on the ext_resume_pin of the peripheral gener- ates a wakeup interrupt. on early versions of the usp peripheral, the k-state on the usb line is generated immediately. this means that the usb device must be able to answer to the host very quickly. on recent versions, the software sets the rmwupe bit in the udp_glb_state register once it is ready to communicate with the host. the k-state on the bus is then generated. the wakeup bit must be cleared as soon as possible by setting wakeup in the udp_icr register.
544 AT91RM9200 1768b?atarm?08/03 usb device port (udp) user interface table 101. usb device port memory map offset register name access reset state 0x000 frame number register usb_frm_num read 0x0000_0000 0x004 global state register usb_glb_stat read/write 0x0000_0010 0x008 function address register usb_faddr read/write 0x0000_0100 0x00c reserved ? ? ? 0x010 interrupt enable register usb_ier write 0x014 interrupt disable register usb_idr write 0x018 interrupt mask register usb_imr read 0x0000_1200 0x01c interrupt status register usb_isr read 0x0000_0000 0x020 interrupt clear register usb_icr write 0x024 reserved ? ? ? 0x028 reset endpoint register usb_rst_ep read/write 0x02c reserved ? ? ? 0x030 endpoint 0 control and status register usb _csr0 read/write 0x0000_0000 0x034 endpoint 1 control and status register usb _csr1 read/write 0x0000_0000 0x038 endpoint 2 control and status register usb _csr2 read/write 0x0000_0000 0x03c endpoint 3 control and status register usb _csr3 read/write 0x0000_0000 0x040 endpoint 4 control and status register usb _csr4 read/write 0x0000_0000 0x044 endpoint 5 control and status register usb _csr5 read/write 0x0000_0000 0x048 endpoint 6 control and status register usb _csr6 read/write 0x0000_0000 0x04c endpoint 7 control and status register usb _csr7 read/write 0x0000_0000 0x050 endpoint 0 fifo data register usb_fdr0 read/write 0x0000_0000 0x054 endpoint 1 fifo data register usb_fdr1 read/write 0x0000_0000 0x058 endpoint 2 fifo data register usb_fdr2 read/write 0x0000_0000 0x05c endpoint 3 fifo data register usb_fdr3 read/write 0x0000_0000 0x060 endpoint 4 fifo data register usb_fdr4 read/write 0x0000_0000 0x064 endpoint 5 fifo data register usb_fdr5 read/write 0x0000_0000 0x068 endpoint 6 fifo data register usb_fdr6 read/write 0x0000_0000 0x06c endpoint 7 fifo data register usb_fdr7 read/write 0x0000_0000 0x070 reserved ? ? ? 0x074 reserved ? ? ?
545 AT91RM9200 1768b?atarm?08/03 usb frame number register register name: usb_frm_num access type: read-only frm_num[10:0]: frame number as defined in the packet field formats this 11-bit value is incremented by the host on a per frame basis. this value is updated at each start of frame. value updated at the sof_eop (start of frame end of packet). frm_err: frame error this bit is set at sof_eop when the sof packet is received containing an error. this bit is reset upon receipt of sof_pid. frm_ok: frame ok this bit is set at sof_eop when the sof packet is received without any error. this bit is reset upon receipt of sof_pid (packet identification). in the interrupt status register, the sof interrupt is updat ed upon receiving sof_pid. this bit is set without waiting for eop. note: in the 8-bit register interface, frm_ok is bit 4 of frm_num_h and frm_err is bit 3 of frm_num_l. 31 30 29 28 27 26 25 24 --- --- --- --- --- --- --- --- 23 22 21 20 19 18 17 16 ? ? ? ? ? ? frm_ok frm_err 15 14 13 12 11 10 9 8 ????? frm_num 76543210 frm_num
546 AT91RM9200 1768b?atarm?08/03 usb global state register register name: usb_glb_stat access type: read/write this register is used to get and set the device state as specified in chapter 9 of the usb serial bus specification, rev.1.1 . fadden: function address enable read: 0 = device is not in address state. 1 = device is in address state. write: 0 = no effect, only a reset can bring back a device to the default state. 1 = set device in address state. this occurs after a successful set address request. beforehand, the usb_faddr register must have been initialized with set address parameters. set address must complete the status stage before setting fad- den. please refer to chapter 9 of the universal serial bus specification, rev. 1.1 to get more details. confg: configured read: 0 = device is not in configured state. 1 = device is in configured state. write: 0 = set device in a nonconfigured state 1 = set device in configured state. the device is set in configured state when it is in ad dress state and receives a successful set configuration request. please refer to chapter 9 of the universal serial bus specification, rev. 1.1 to get more details. esr: enable send resume 0 = disable the remote wake up sequence. 1 = remote wake up can be processed and the pin send_resume is enabled. rsminpr: a resume has been sent to the host read: 0 = no effect. 1 = a resume has been received from the host during remote wake up feature. rmwupe: remote wake up enable 0 = must be cleared after receiving any host packet or sof interrupt. 1 = enables the k-state on the usb cable if esr is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? ?? 76543210 ? ? ? rmwupe rsminpr esr confg fadden
547 AT91RM9200 1768b?atarm?08/03 usb function addr ess regi ster register name: usb_faddr access type: read/write fadd[6:0]: function address value the function address value must be programmed by firmware once the device receives a set address request from the host, and has achieved the status stage of the no-data control sequence. please refer to the universal serial bus specifica- tion, rev. 1.1 to get more information. after power up, or reset, the function address value is set to 0. fen: function enable read: 0 = function endpoint disabled. 1 = function endpoint enabled. write: 0 = disable function endpoint. 1 = default value. the function enable bit (fen) allows the microcontroller to enable or disable the function endpoints. the microcontroller sets this bit after receipt of a reset from the host. once this bit is set, the usb device is able to accept and transfer data packets from and to the host. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? ?fen 76543210 ?fadd
548 AT91RM9200 1768b?atarm?08/03 usb interrupt enable register register name: usb_ier access type: write-only ep0int: enable endpoint 0 interrupt ep1int: enable endpoint 1 interrupt ep2int: enable endpoint 2interrupt ep3int: enable endpoint 3 interrupt ep4int: enable endpoint 4 interrupt ep5int: enable endpoint 5 interrupt ep6int: enable endpoint 6 interrupt ep7int: enable endpoint 7 interrupt 0 = no effect. 1 = enable corresponding endpoint interrupt. rxsusp: enable usb suspend interrupt 0 = no effect. 1 = enable usb suspend interrupt. rxrsm: enable usb resume interrupt 0 = no effect. 1 = enable usb resume interrupt. extrsm: enable external resume interrupt 0 = no effect. 1 = enable external resume interrupt. sofint: enable start of frame interrupt 0 = no effect. 1 = enable start of frame interrupt. wakeup: enable usb bus wakeup interrupt 0 = no effect. 1 = enable usb bus interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? wakeup ? sofint extrsm rxrsm rxsusp 76543210 ep7int ep6int ep5int ep4int ep3int ep2int ep1int ep0int
549 AT91RM9200 1768b?atarm?08/03 usb interrupt disable register register name: usb_idr access type: write-only ep0int: disable endpoint 0 interrupt ep1int: disable endpoint 1 interrupt ep2int: disable endpoint 2 interrupt ep3int: disable endpoint 3 interrupt ep4int: disable endpoint 4 interrupt ep5int: disable endpoint 5 interrupt ep6int: disable endpoint 6 interrupt ep7int: disable endpoint 7 interrupt 0 = no effect. 1 = disable corresponding endpoint interrupt. rxsusp: disable usb suspend interrupt 0 = no effect. 1 = disable usb suspend interrupt. rxrsm: disable usb resume interrupt 0 = no effect. 1 = disable usb resume interrupt. extrsm: disable external resume interrupt 0 = no effect. 1 = disable external resume interrupt. sofint: disable start of frame interrupt 0 = no effect. 1 = disable start of frame interrupt wakeup: disable usb bus interrupt 0 = no effect. 1 = disable usb bus wakeup interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? wakeup ? sofint extrsm rxrsm rxsusp 76543210 ep7int ep6int ep5int ep4int ep3int ep2int ep1int ep0int
550 AT91RM9200 1768b?atarm?08/03 usb interrupt mask register register name: usb_imr access type: read-only ep0int: mask endpoint 0 interrupt ep1int: mask endpoint 1 interrupt ep2int: mask endpoint 2 interrupt ep3int: mask endpoint 3 interrupt ep4int: mask endpoint 4 interrupt ep5int: mask endpoint 5 interrupt ep6int: mask endpoint 6 interrupt ep7int: mask endpoint 7 interrupt 0 = corresponding endpoint interrupt is disabled. 1 = corresponding endpoint interrupt is enabled. rxsusp: mask usb suspend interrupt 0 = usb suspend interrupt is disabled. 1 = usb suspend interrupt is enabled. rxrsm: mask usb resume interrupt. 0 = usb resume interrupt is disabled. 1 = usb resume interrupt is enabled. extrsm: mask external resume interrupt 0 = external resume interrupt is disabled. 1 = external resume interrupt is enabled. sofint: mask start of frame interrupt 0 = start of frame interrupt is disabled. 1 = start of frame interrupt is enabled. wakeup: usb bus wakeup interrupt 0 = usb bus wakeup interrupt is disabled. 1 = usb bus wakeup interrupt is enabled. note: when the usb block is in suspend mode, the application may power down the usb logic. in this case, any usb host resume request that is made must be taken into account and, thus, the reset value of the rxrsm bit of the register usb_imr is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? wakeup ? sofint extrsm rxrsm rxsusp 76543210 ep7int ep6int ep5int ep4int ep3int ep2int ep1int ep0int
551 AT91RM9200 1768b?atarm?08/03 usb interrupt status register register name: usb_isr access type: read -only ep0int: endpoint 0 interrupt status 0 = no endpoint0 interrupt pending. 1 = endpoint0 interrupt has been raised. several signals can generate this interrupt. the reason can be found by reading usb_csr0: rxsetup set to 1 rx_data_bk0 set to 1 rx_data_bk1 set to 1 txcomp set to 1 stallsent set to 1 ep0int is a sticky bit. interrupt remains valid until ep0int is cleared by writing in the corresponding usb_csr0 bit. ep1int: endpoint 1 interrupt status 0 = no endpoint1 interrupt pending. 1 = endpoint1 interrupt has been raised. several signals can generate this interrupt. the reason can be found by reading usb_csr1: rxsetup set to 1 rx_data_bk0 set to 1 rx_data_bk1 set to 1 txcomp set to 1 stallsent set to 1 ep1int is a sticky bit. interrupt remains valid until ep1int is cleared by writing in the corresponding usb_csr1 bit. ep2int: endpoint 2 interrupt status 0 = no endpoint2 interrupt pending. 1 = endpoint2 interrupt has been raised. several signals can generate this interrupt. the reason can be found by reading usb_csr2: rxsetup set to 1 rx_data_bk0 set to 1 rx_data_bk1 set to 1 txcomp set to 1 stallsent set to 1 ep2int is a sticky bit. interrupt remains valid until ep2int is cleared by writing in the corresponding usb_csr2 bit. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? wakeup endbusres sofint extrsm rxrsm rxsusp 76543210 ep7int ep6int ep5int ep4int ep3int ep2int ep1int ep0int
552 AT91RM9200 1768b?atarm?08/03 ep3int: endpoint 3 interrupt status 0 = no endpoint3 interrupt pending. 1 = endpoint3 interrupt has been raised. several signals can generate this interrupt. the reason can be found by reading usb_csr3: rxsetup set to 1 rx_data_bk0 set to 1 rx_data_bk1 set to 1 txcomp set to 1 stallsent set to 1 ep3int is a sticky bit. interrupt remains valid until ep3int is cleared by writing in the corresponding usb_csr3 bit. ep4int: endpoint 4 interrupt status 0 = no endpoint4 interrupt pending. 1 = endpoint4 interrupt has been raised. several signals can generate this interrupt. the reason can be found by reading usb_csr4: rxsetup set to 1 rx_data_bk0 set to 1 rx_data_bk1 set to 1 txcomp set to 1 stallsent set to 1 ep4int is a sticky bit. interrupt remains valid until ep4int is cleared by writing in the corresponding usb_csr4 bit. ep5int: endpoint 5 interrupt status 0 = no endpoint5 interrupt pending. 1 = endpoint5 interrupt has been raised. several signals can generate this interrupt. the reason can be found by reading usb_csr5: rxsetup set to 1 rx_data_bk0 set to 1 rx_data_bk1 set to 1 txcomp set to 1 stallsent set to 1 ep5int is a sticky bit. interrupt remains valid until ep5int is cleared by writing in the corresponding usb_csr5 bit. ep6int: endpoint 6 interrupt status 0 = no endpoint6 interrupt pending. 1 = endpoint6 interrupt has been raised. several signals can generate this interrupt. the reason can be found by reading usb_csr6: rxsetup set to 1 rx_data_bk0 set to 1 rx_data_bk1 set to 1 txcomp set to 1 stallsent set to 1 ep6int is a sticky bit. interrupt remains valid until ep6int is cleared by writing in the corresponding usb_csr6 bit.
553 AT91RM9200 1768b?atarm?08/03 ep7int: endpoint 7 interrupt status 0 = no endpoint7 interrupt pending. 1 = endpoint7 interrupt has been raised. several signals can generate this interrupt. the reason can be found by reading usb_csr7: rxsetup set to 1 rx_data_bk0 set to 1 rx_data_bk1 set to 1 txcomp set to 1 stallsent set to 1 ep7int is a sticky bit. interrupt remains valid until ep7int is cleared by writing in the corresponding usb_csr7 bit. rxsusp: usb suspend interrupt status 0 = no usb suspend interrupt pending. 1 = usb suspend interrupt has been raised. the usb device sets this bit when it detects no activity for 3ms. the usb device enters suspend mode. rxrsm: usb resume interrupt status 0 = no usb resume interrupt pending. 1 =usb resume interrupt has been raised. the usb device sets this bit when a usb resume signal is detected at its port. extrsm: external resume interrupt status 0 = no external resume interrupt pending. 1 = external resume interrupt has been raised. this interrupt is raised when, in suspend mode, an asynchronous rising edge on the send_resume is detected. if rmwupe = 1, a resume state is sent in the usb bus. sofint: start of frame interrupt status 0 = no start of frame interrupt pending. 1 = start of frame interrupt has been raised. this interrupt is raised each time a sof token has been detected. it can be used as a synchronization signal by using isochronous endpoints. endbusres: end of bus reset interrupt status 0 = no end of bus reset interrupt pending. 1 = end of bus reset interrupt has been raised. this interrupt is raised at the end of a usb reset sequence. the usb device must prepare to receive requests on the end- point 0. the host starts the enumeration, then performs the configuration. wakeup: usb resume interrupt status 0 = no wakeup interrupt pending. 1 = a wakeup interrupt (usb host sent a resume or reset) occurred since the last clear.
554 AT91RM9200 1768b?atarm?08/03 usb interrupt clear register register name: usb_icr access type: write-only rxsusp: clear usb suspend interrupt 0 = no effect. 1 = clear usb suspend interrupt. rxrsm: clear usb resume interrupt 0 = no effect. 1 = clear usb resume interrupt. extrsm: clear external resume interrupt 0 = no effect. 1 = clear external resume interrupt. sofint: clear start of frame interrupt 0 = no effect. 1 = clear start of frame interrupt. endburst: clear end of bus reset interrupt 0 = no effect. 1 = clear start of frame interrupt. wakeup: clear wakeup interrupt 0 = no effect. 1 = clear wakeup interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? wakeup endburst sofint extrsm rxrsm rxsusp 76543210 ????????
555 AT91RM9200 1768b?atarm?08/03 usb reset endpoint register register name: usb_rst_ep access type: read/write ep0: reset endpoint 0 ep1: reset endpoint 1 ep2: reset endpoint 2 ep3: reset endpoint 3 ep4: reset endpoint 4 ep5: reset endpoint 5 ep6: reset endpoint 6 ep7: reset endpoint 7 this flag is used to reset the fifo associated with the endpoint and the bit rxbytecount in the register udp_csrx.it also resets the data toggle to data0. it is useful after removing a halt condition on a bulk endpoint. refer to chapter 5.8.5 in the usb serial bus specification, rev.1.1 . warning: this flag must be cleared at the end of the reset. it does not clear usb_csrx flags. 0 = no reset. 1 = forces the corresponding endpoint fif0 pointers to 0, therefore rxbytecnt field is read at 0 in usb_csrx register. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? ?? 76543210 ep7 ep6 ep5 ep4 ep3 ep2 ep1 ep0
556 AT91RM9200 1768b?atarm?08/03 usb endpoint control and status register register name: usb_csrx [x = 0. 7] access type: read/write txcomp: generates an in packet with data previously written in the dpr this flag generates an interrupt while it is set to one. write (cleared by the firmware) 0 = clear the flag, clear the interrupt. 1 = no effect. read (set by the usb peripheral) 0 = data in transaction has not been acknowledged by the host. 1 = data in transaction is achieved, acknowledged by the host. after having issued a data in transaction setting txpktrdy, t he device firmware waits for txcomp to be sure that the host has acknowledged the transaction. rx_data_bk0: receive data bank 0 this flag generates an interrupt while it is set to one. write (cleared by the firmware) 0 = notify usb peripheral device that data have been read in the fifo's bank 0. 1 = no effect. read (set by the usb peripheral) 0 = no data packet has been received in the fifo's bank 0 1 = a data packet has been received, it has been stored in the fifo's bank 0. when the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the fifo to the microcontroller memory. the number of bytes received is available in rxbytcent field. bank 0 fifo values are read through the usb_fdrx register. once a transfer is done, the device firmware must release bank 0 to the usb peripheral device by clearing rx_data_bk0. rxsetup: sends stall to the host (control endpoints) this flag generates an interrupt while it is set to one. read 0 = no setup packet available. 1 = a setup data packet has been sent by the host and is available in the fifo. write 0 = device firmware notifies the usb peripheral device that it has read the setup data in the fifo. 31 30 29 28 27 26 25 24 ????? rxbytecnt 23 22 21 20 19 18 17 16 rxbytecnt 15 14 13 12 11 10 9 8 epeds ? ? ? dtgle eptype 76543210 dir rx_data_ bk1 force stall txpktrdy stallsent isoerror rxsetup rx_data_ bk0 txcomp
557 AT91RM9200 1768b?atarm?08/03 1 = no effect. this flag is used to notify the usb device firmware that a valid setup data packet has been sent by the host and success- fully received by the usb device. the usb device firmware may transfer setup data from the fifo by reading the usb_fdrx register to the microcontroller memory. once a transfer has been done, rxsetup must be cleared by the device firmware. ensuing data out transactions is not accepted while rxsetup is set. stallsent: stall sent (control, bulk interrupt endpoints)/ isoerror (isochronous endpoints) this flag generates an interrupt while it is set to one. stallsent: this ends a stall handshake read 0 = the host has not acknowledged a stall. 1 = host has acknowledge the stall. write 0 = reset the stallsent flag, clear the interrupt. 1 = no effect. this is mandatory for the device firmware to clear this flag. otherwise the interrupt remains. please refer to chapters 8.4.4 and 9.4.5 of the universal serial bus specification, rev. 1.1 to get more information on the stall handshake. isoerror: a crc error has been detected in an isochronous transfer read 0 = no error in the previous isochronous transfer. 1 = crc error has been detected, data available in the fifo are corrupted. write 0 = reset the isoerror flag, clear the interrupt. 1 = no effect. txpktrdy: transmit packet ready this flag is cleared by the usb device. this flag is set by the usb device firmware. read 0 = data values can be written in the fifo. 1 = data values can not be written in the fifo. write 0 = no effect. 1 = a new data payload is has been written in the fifo by the firmware and is ready to be sent. this flag is used to generate a data in transaction (device to host). device firmware checks that it can write a data payload in the fifo, checking that txpktrdy is cleared. transfer to the fifo is done by writing in the usb_fdrx register. once the data payload has been transferred to the fifo, the firmware notifies the usb device setting txpktrdy to one. usb bus transactions can start. txcomp is set once the data payload has been received by the host. forcestall: force stall (used by control, bulk and isochronous endpoints) write-only 0 = no effect. 1 = send stall to the host.
558 AT91RM9200 1768b?atarm?08/03 please refer to chapters 8.4.4 and 9.4.5 of the universal serial bus specification, rev. 1.1 to get more information on the stall handshake. control endpoints: during the data stage and status stage, this indicates that the microcontroller can not complete the request. bulk and interrupt endpoints: notify the host that the endpoint is halted. the host acknowledges the stall, device firmware is notified by the stallsent flag. rx_data_bk1: receive data bank 1 (only used by endpoints with ping-pong attributes) this flag generates an interrupt while it is set to one. write (cleared by the firmware) 0 = notify usb device that data have been read in the fifo?s bank 1. 1 = no effect. read (set by the usb peripheral) 0 = no data packet has been received in the fifo's bank 1. 1 = a data packet has been received, it has been stored in fifo's bank 1. when the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the fifo to microcontroller memory. the number of bytes received is available in rxbytecnt field. bank 1 fifo values are read through usb_fdrx register. once a transfer is done, the device firmware must release bank 1 to the usb device by clear- ing rx_data_bk1. dir: transfer direction (only available for control endpoints) read/write 0 = allow data out transactions in the control data stage. 1 = enable data in transactions in the control data stage. please refer to chapter 8.5.2 of the universal serial bus specification, rev. 1.1 to get more information on the control data stage. this bit must be set before usb_csrx/rxsetup is cleared at the end of the setup stage. according to the request sent in the setup data packet, the data stage is either a device to host (dir = 1) or host to device (dir = 0) data transfer. it is not necessary to check this bit to reverse direction for the status stage. eptype[2:0]: endpoint type dtgle: data toggle read-only 0 = identifies data0 packet. 1 = identifies data1 packet. please refer to chapter 8 of the universal serial bus specification, rev. 1.1 to get more information on data0, data1 packet definitions. read/write 000 control 001 isochronous out 101 isochronous in 010 bulk out 110 bulk in 011 interrupt out 111 interrupt in
559 AT91RM9200 1768b?atarm?08/03 epeds: endpoint enable disable read 0 = endpoint disabled. 1 = endpoint enabled. write 0 = disable endpoint. 1 = enable endpoint. rxbytecnt[10:0]: number of bytes available in the fifo read-only. when the host sends a data packet to the device, the usb device stores the data in the fifo and notifies the microcontrol- ler. the microcontroller can load the data from the fifo by reading rxbytecent bytes in the usb_fdrx register.
560 AT91RM9200 1768b?atarm?08/03 usb fifo data register register name: usb_fdrx [x = 0. 7] access type: read/write fifo_data[7:0]: fifo data value the microcontroller can push or pop values in the fifo through this register. rxbytecnt in the corresponding usb_csrx register is the number of bytes to be read from the fifo (sent by the host). the maximum number of bytes to write is fixed by the max packet size in the standard endpoint descriptor. it can not be more than the physical memory size associated to the endpoint. please refer to the universal serial bus specification, rev. 1.1 to get more information. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? ?? 76543210 fifo_data
561 AT91RM9200 1768b?atarm?08/03 usb host port (uhp) overview the usb host port interfaces the usb with the host application. it handles open hci protocol (open host controller interface) as well as usb v2.0 full-speed and low-speed protocols. it also provides a simple read/write protocol on the asb. the usb host port integrates a root hub and transceivers on downstream ports. it provides several high-speed half-duplex serial communication ports at a baud rate of 12 mbit/s. up to 127 usb devices (printer, camera, mouse, keyboard, disk, etc.) and the usb hub can be con- nected to the usb host in the usb ?tiered star? topology. the usb host port controller is fully compliant with the open hci specification. the standard ohci usb stack driver can be easily ported to atmel?s architecture in the same way all exist- ing class drivers run without hardware specialization. this means that all standard class devices are automatically detected and available to the user application. as an example, integrating an hid (human interface device) class driver provides a plug & play feature for all usb keyboards and mouses. key features of the usb host port are: compliance with open hci rev 1.0 specification compliance with usb v2.0 full speed and low speed specification supports both low-speed 1.5 mbps and full-speed 12 mbps usb devices root hub integrated with two downstream usb ports embedded usb transceivers (number of transceivers is product dependant) supports power management operates as a master on the asb bus block diagram figure 259. usb host port block diagram port s/m port s/m usb transceiver usb transceiver dp dm dp dm embedded usb v2.0 full-speed transceiver root hub and host sie list processor block fifo 64 x 8 hci slave block ohci registers ohci root hub registers asb ed & td regsisters control hci master block data uhp_int mck udpck
562 AT91RM9200 1768b?atarm?08/03 access to the usb host operational registers is achieved through the asb bus interface. the open hci host controller initializes master dma transfers with the asb bus as follows: fetches endpoint descriptors and transfer descriptors access to endpoint data from system memory access to the hc communication area write status and retire transfer descriptor all of the asb memory map is accessible to the usb host master dma. thus there is no need to define a dedicated physical memory area to the usb host. the usb root hub is integrated in the usb host. several usb downstream ports are available. the number of downstream ports can be determined by the software driver reading the root hub?s operational registers. device connection is automatically detected by the usb host port logic. warning: a pull-down must be connected to dp on the board. otherwise the usb host will permanently detect a device connection on this port. usb physical transceivers are integrated in the product and driven by the root hub?s ports. over current protection on ports can be activated by the usb host controller. atmel?s standard product does not dedicate pads to external over current protection. product dependencies i/o lines dps and dms are not controlled by any pio controllers. the embedded usb physical trans- ceivers are controlled by the usb host controller. power management the usb host controller requires a 48 mhz clock. this clock must be generated by a pll with a correct accuracy of 0.25%. thus the usb device peripheral receives two clocks from the power management controller (pmc): the master clock mck used to drive the peripheral user interface (mck domain) and the uhpclk 48 mhz clock used to interface with the bus usb signals (recovered 12 mhz domain). interrupt the usb host interface has an interrupt line co nnected to the advanced interrupt controller (aic). handling usb host interrupts requires programming the aic before configuring the uhp. functional description please refer to the open host controller interface specification for usb release 1.0.a. host controller interface there are two communication channels between the host controller and the host controller driver. the first channel uses a set of operational registers located on the usb host control- ler. the host controller is the target for all communications on this channel. the operational registers contain control, status and list pointer registers. they are mapped in the asb mem- ory mapped area. within the operational register set there is a pointer to a location in the processor address space named the host controller communication area (hcca). the hcca is the second communication channel. the host controller is the master for all commu- nication on this channel. the hcca contains the head pointers to the interrupt endpoint
563 AT91RM9200 1768b?atarm?08/03 descriptor lists, the head pointer to the done queue and status information associated with start-of-frame processing. the basic building blocks for communication across the interface are endpoint descriptors (ed, 4 double words) and transfer descriptors (td, 4 or 8 double words). the host controller assigns an endpoint descriptor to each endpoint in the system. a queue of transfer descrip- tors is linked to the endpoint descriptor for the specific endpoint. figure 260. usb host communication channels host controller driver figure 261. usb host drivers operational registers mode hcca status event frame int ratio control bulk host controller communications area interrupt 0 interrupt 1 interrupt 2 interrupt 31 done . . . . . . open hci shared ram device register in memory space device enumeration = transfer descriptor = endpoint descriptor . . . host controller hardware hub driver host controller driver usbd driver mini driver class driver class driver user application kernel drivers user space hardware
564 AT91RM9200 1768b?atarm?08/03 usb handling is done through several layers as follows: host controller hardware and serial engine: transmit and receive usb data on the bus. host controller driver: drives the host controller hardware and handle the usb protocol usb bus driver and hub driver: handles usb commands and enumeration. offers a hardware independent interface. mini driver: handles device specific commands. class driver: handles standard devices. this acts as a generic driver for a class of devices, for example the hid driver. typical connection figure 262. board schematic to interface uhp device controller as device connection is automatically detected by the usb host port logic, a pull-down must be connected on dp and dm on the board. otherwise the usb host will permanently detect a device connection on this port. 47pf 47pf 27 ? hdma or hdmb hdpa or hdpb 27 ? 15k ? 15k ? 10nf 100nf 10 f 5v 0.20a type a connector
565 AT91RM9200 1768b?atarm?08/03 ethernet mac (emac) overview the ethernet mac is the hardware implementation of the mac sub-layer osi reference model between the physical layer (phy) and the logica l link layer (llc). it controls the data exchange between a host and a phy layer according to ethernet ieee 802.3u data frame for- mat. the ethernet mac contains the required logic and transmit and receive fifos for dma management. in addition, it is interfaced through mdio/mdc pins for phy layer management. the ethernet mac can transfer data in media-independent interface (mii) or reduced media- independent interface (rmii) modes depending on the pinout configuration. the aim of the reduced interface is to lower the pin count for a switch product that can be con- nected to multiple phy interfaces. the characteristics specific to rmii mode are: single clock at 50 mhz frequency reduction of required control pins reduction of data paths to di-bit (2-bit wide) by doubling clock frequency 10 mbits/sec. and 100 mbits/sec. data capability the major features of the emac are: compatibility with ieee standard 802.3 10 and 100 mbits per second data throughput capability full- and half-duplex operation mii or rmii interface to the physical layer register interface to address, status and control registers dma interface interrupt generation to signal receive and transmit completion 28-byte transmit and 28-byte receive fifos automatic pad and crc generation on transmitted frames address checking logic to recognize four 48-bit addresses supports promiscuous mode where all valid frames are copied to memory supports physical layer management through mdio interface control of alarm and update time/calendar data in
566 AT91RM9200 1768b?atarm?08/03 block diagram figure 263. block diagram application block diagram figure 264. ethernet mac application block diagram ethernet mac interrupt control pio apb bridge pmc mck emac irq etxck-erxck-erefck exten-exter ecrs-ecol erxer-erxdv erx0-erx3 etx0-etx3 dma apb asb emdc emdio ef100 tcp/ip socket api udp tcp ip arp/rarp snmp snmp agent mib functions http telnet ftp web server telnet server ftp server web pages telnet console ethernet driver emac (802.3 compliant) physical medium independant layer (mii or rmii) physical medium dependant layer (10 base-t phy) link connector (rj45) network
567 AT91RM9200 1768b?atarm?08/03 product dependencies i/o lines the pins used for interfacing the compliant external devices may be multiplexed with pio lines. the programmer must first program the pio controllers to assign the emac pins to their peripheral functions. in rmii mode, unused pins (see table 102: mii/rmii signal mapping) can be used as general i/o lines. power management the emac may be clocked through the power management controller (pmc), so the pro- grammer must first configure the pmc to enable the emac clock. interrupt the emac has an interrupt line connected to the advanced interrupt controller (aic). han- dling the emac interrupt requires programming the aic before configuring the emac.
568 AT91RM9200 1768b?atarm?08/03 functional description the ethernet media access control (emac) engine is fully compatible with the ieee 802.3 ethernet standard. it manages frame transmission and reception including collision detection, preamble generation and detection, crc control and generation and transmitted frame padding. the mac functions are: frame encapsulation and decapsulation error detection media access management (mii, rmii) figure 265. emac functional block diagram address checker control registers ethernet receive ethernet transmit statistics registers dma interface register interface apb asb rmii/mii mdio mii/rmii emac
569 AT91RM9200 1768b?atarm?08/03 media independe nt interface general the ethernet mac is capable of interfacing to both rmii and mii interfaces. the rmii bit in the eth_cfg register controls the interface that is selected. when this bit is set, the rmii inter- face is selected, else the mii interface is selected. the mii and rmii interface are capable of both 10mb/s and 100mb/s data rates as described in the ieee 802.3u standard. the signals used by the mii and rmii interfaces are described in the table 102. the intent of the rmii is to provide a reduced pin count alternative to the ieee 802.3u mii. it uses 2 bits for transmit (etx0 and etx1) and two bits for receive (erx0 and erx1). there is a transmit enable (etxen), a receive error (erxer), a carrier sense (ecrs_dv), and a 50 mhz reference clock (etxck_refck) for 100mb/s data rate. rmii transmit and receive operation the same signals are used internally for both the rmii and the mii operations. the rmii maps these signals in a more pin-efficient manner. the transmit and receive bits are converted from a 4-bit parallel format to a 2-bit parallel scheme that is clocked at twice the rate. the carrier sense and data valid signals are combined into the ecrs_ecrsdv signal. this signal con- tains information on carrier sense, fifo status, and validity of the data. transmit error bit (etxer) and collision detect (ecol) are not used in rmii mode. table 102. pin configurations pin name mii rmii etxck_refck etxck: transmit clock refck: reference clock ecrs_ecrsdv ecrs: carrier sense ecrsdv: carrier sense/data valid ecol ecol: collision detect erxdv erxdv: data valid erx0 - erx3 erx0 - erx3: 4-bit receive data erx0 - erx1: 2-bit receive data erxer erxer: receive error erxer: receive error erxck erxck: receive clock etxen etxen: transmit enable etxen: transmit enable etx0-etx3 etx0 - etx3: 4-bit transmit data etx0 - etx1: 2-bit transmit data etxer etxer: transmit error
570 AT91RM9200 1768b?atarm?08/03 transmit/receive operation a standard ieee 802.3 packet consists of the following fields: preamble, start of frame delim- iter (sfd), destination address (da), source address (sa), length, data (logical link control data) and frame check sequence crc32 (fcs). note: frame length between 64 bytes and 1518 bytes. the packets are manchester-encoded and -decoded and transferred serially using nrz data with a clock. all fields are of fixed length except for the data field. the mac generates and appends the preamble, sfd and crc fields during transmission. the preamble and sfd fields are stripped during reception. preamble and start of frame delimiter (sfd) the preamble field is used to acquire bit synchronization with an incoming packet. when transmitted, each packet contains 62 bits of alternating 1,0 preamble. some of this preamble is lost as the packet travels through the network. byte alignment is performed with the start of frame delimiter (sfd) pattern that consists of two consecutive 1's. destination address the destination address (da) indicates the destination of the packet on the network and is used to filter unwanted packets. there are three types of address formats: physical, multicast and broadcast. the physical address is a unique address that corresponds only to a single node. all physical addresses have an msb of 0. multicast addresses begin with an msb of 1. the mac filters multicast addresses using a standard hashing algorithm that maps all multicas t addresses into a 6-bit value. this 6-bit value indexes a 64-bit array that filters the value. if the address consists of all ones, it is a broadcast address, indicating that the packet is intended for all nodes. source address the source address (sa) is the physical address of the node that sent the packet. source addresses cannot be multicast or broadcast addresses. this field is passed to buffer memory. length/type if the value of this field is less than or equal to 1500, then the length/type field indicates the number of bytes in the subsequent llc data field. if the value of this field is greater than or equal to 1536, then the length/type field indicates the nature of the mac client protocol (pro- tocol type). llc data the data field consists of anywhere from 46 to 1500 bytes. messages longer than 1500 bytes need to be broken into multiple packets. messages shorter than 46 bytes require appending a pad to bring the data field to the minimum length of 46 bytes. if the data field is padded, the number of valid data bytes is indicated in the length field. fcs field the frame check sequence (fcs) is a 32-bit crc field, calculated and appended to a packet during transmission to allow detection of errors when a packet is received. during reception, error free packets result in a specific pattern in the crc generator. packets with improper crc will be rejected. table 103. packet format preamble frame (1) alternating 1s/0s sfd da sa length/type llc data pad fcs up to 7 bytes 1 byte 6 bytes 6 bytes 2 bytes 4 bytes
571 AT91RM9200 1768b?atarm?08/03 frame format extensions the original ethernet standards defined the minimum frame size as 64 bytes and the maxi- mum as 1518 bytes. these numbers include all bytes from the destination mac address field through the frame check sequence field. the preamble and start frame delimiter fields are not included when quoting the size of a frame. the ieee 802.3ac standard extended the max- imum allowable frame size to 1522 bytes to allow a vlan tag to be inserted into the ethernet frame format. the bit big defined in the eth_cfg register aims to process packet with vlan tag. the vlan protocol permits insertion of an identifier, or tag, into the ethernet frame format to identify the vlan to which the frame belongs. it allows frames from stations to be assigned to logical groups. this provides various benefits, such as easing network administration, allowing formation of work groups, enhancing network security, and providing a means of limiting broadcast domains (refer to ieee standard 802.1q for definition of the vlan protocol). the 802.3ac standard defines only the implementation details of the vlan protocol that are spe- cific to ethernet. if present, the 4-byte vlan tag is inserted into the ethernet frame between the source mac address field and the length field. the first 2-bytes of the vlan tag consist of the ?802.1q tag type? and are always set to a value of 0x8100. the 0x8100 value is a reserved length/type field assignment that indicates the presence of the vlan tag, and signals that the traditional length/type field can be found at an offset of four bytes further into the frame. the last two bytes of the vlan tag contain the following information: the first three bits are a user priority field that may be used to assign a priority level to the ethernet frame. the following one bit is a canonical format indicator (cfi) used in ethernet frames to indicate the presence of a routing information field (rif). the last twelve bits are the vlan identifier (vid) that uniquely identifies the vlan to which the ethernet frame belongs. with the addition of vlan tagging, the 802.3ac standard permits the maximum length of an ethernet frame to be extended from 1518 bytes to 1522 bytes. table 104 illustrates the format of an ethernet frame that has been ?tagged? with a vlan identifier according to the ieee 802.3ac standard. table 104. ethernet frame with vlan tagging preamble 7 bytes start frame delimiter 1 byte dest. mac address 6 bytes source mac address 6 bytes length/type = 802.1q tag type 2 byte tag control information 2 bytes length / type 2 bytes mac client data 0 - n bytes pad 0 - p bytes frame check sequence 4 bytes
572 AT91RM9200 1768b?atarm?08/03 dma operations frame data is transferred to and from the ethernet mac via the dma interface. all transfers are 32-bit words and may be single accesses or bursts of two, three or four words. burst accesses do not cross 16-byte boundaries. the dma controller performs four types of operations on the asb bus. in order of priority, these operations are receive buffer manager read, receive buffer manager write, transmit data dma read and receive data dma write. transmitter mode transmit frame data needs to be stored in contiguous memory locations. it does not need to be word-aligned. the transmit address register is written with the address of the first byte to be transmitted. transmit is initiated by writing the number of bytes to transfer (length) to the transmit control register. the transmit channel then reads data from memory 32 bits at a time and places them in the transmit fifo. the transmit block starts frame transmission when three words have been loaded into the fifo. the transmit address register must be written before the transmit control register. while a frame is being transmitted, it is possible to set up one other frame for transmission by writing new values to the transmit address and control registers. reading the transmit address regis- ter returns the address of the buffer currently being accessed by the transmit fifo. reading the transmit control register returns the total number of bytes to be transmitted. the bnq bit in the transmit status register indicates whether another buffer can be safely queued. an interrupt is generated whenever this bit is set. frame assembly starts by adding preamble and the start frame delimiter. data is taken from the transmit fifo word-by-word. if necessary, padding is added to make the frame length 60 bytes. the crc is calculated as a 32-bit polynomial. this is inverted and appended to the end of the frame, making the frame length a minimum of 64 bytes. the crc is not appended if the ncrc bit is set in the transmit control register. in full-duplex mode, frames are transmitted immediately. back-to-back frames are transmitted at least 96 bit times apart to guarantee the inter-frame gap. in half-duplex mode, the transmitter checks carrier sense. if asserted, it waits for it to de-assert and then starts transmission after the inter-frame gap of 96 bit-times. if the collision signal is asserted during transmission, the transmitter transmits a jam sequence of 32 bits taken from the data register and then retries transmission after the backoff time has elapsed. an error is indicated and any further attempts aborted if 16 attempts cause collisions. if transmit dma underruns, bad crc is au tomatically appended using the same mechanism as jam insertion. underrun also causes txer to be asserted. receiver mode when a packet is received, it is checked for valid preamble, crc, alignment, length and address. if all these criteria are met, the packet is stored successfully in a receive buffer. if at the end of reception the crc is bad, then the received buffer is recovered. each received frame including crc is written to a single receive buffer. receive buffers are word-aligned and are capable of containing 1518 or 1522 bytes (big = 1 in eth_cfg) of data (the maximum length of an ethernet frame). the start location for each received frame is stored in memory in a list of receive buffer descriptors at a location pointed to by the receive buffer queue pointer register. each entry in
573 AT91RM9200 1768b?atarm?08/03 the list consists of two words. the first word is the address of the received buffer; the second is the receive status. table 105 defines an entry in the received buffer descriptor list. to receive frames, the buffer queue must be initialized by writing an appropriate address to bits [31:2] in the first word of each list entry. bit zero of word zero must be written with zero. after a frame is received, bit zero becomes set and the second word indicates what caused the frame to be copied to memory. the start location of the received buffer descriptor list should be written to the received buffer queue poi nter register before receive is enabled (by setting the receive enable bit in the network cont rol register). as soon as the received block starts writing received frame data to the receive fifo, the received buffer manager reads the first receive buffer location pointed to by the received buffer queue pointer register. if the filter block is active, the frame should be copied to memory; the receive data dma operation starts writing data into the receive buffer. if an error occurs, the buffer is recovered. if the frame is received without error, the queue entry is updated. the buffer pointer is rewritten to memory with its low-order bit set to indicate successful frame reception and a used buffer. the next word is written with the length of the frame and how the destination address was recognized. the next receive buffer location is then read from the following word or, if the current buffer pointer had its wrap bit set, the beginning of the table. the maximum number of buffer pointers before a wrap bit is seen is 1024. if a wrap bit is not seen by then, a wrap bit is assumed in that entry. the received buffer queue pointer register must be written with zero in its lower-order bit positions to enable the wrap function to work correctly. if bit zero is set when the receive buffer manager reads the location of the receive buffer, then the buffer has already been used and cannot be used again until software has processed the frame and cleared bit zero. in this case, the dm a block sets the buffer unavailable bit in the received status register and triggers an interrupt. the frame is discarded and the queue entry is reread on reception of the next frame to see if the buffer is now available. each discarded frame increments a statistics register that is cleared on being read. when there is network congestion, it is possible for the mac to be programmed to apply backpressure. this is when half-duplex mode collisions are forced on all received frames by transmitting 64 bits of data (a default pattern). reading the received buffer queue register returns the location of the queue entry currently being accessed. the queue wraps around to the start after either 1024 entries (i.e., 2048 words) or when the wrap bit is found to be set in bit 1 of the first word of an entry. table 105. received buffer descriptor list bit function word 0 31:2 base address of receive buffer 1 wrap bit. if this bit is set, the counter that is ored with the received buffer queue pointer register to give the pointer to entries in this table is cleared after the buffer is used. 0 ownership bit. 1 indicates software owns the pointer, 0 indicates that the dma owns the buffer. if this bit is not zero when the entry is read by the receiver, the buffer unavailable bit is set in the received status register and the receiver goes inactive. word 1 31 global all ones broadcast address detected 30 multicast hash match 29 unicast hash match
574 AT91RM9200 1768b?atarm?08/03 address checking whether or not a frame is stored depends on what is enabled in the network configuration reg- ister, the contents of the specific address and hash registers and the frame destination address. in this implementation of the mac the frame source address is not checked. a frame is not copied to memory if the mac is transmitting in half-duplex mode at the time a destination address is received. the hash register is 64 bits long and takes up two locations in the memory map. there are four 48-bit specific address registers, each taking up two memory locations. the first location contains the first four bytes of the address; the second location contains the last two bytes of the address stored in its least significant byte positions. the addresses stored can be specific, group, local or universal. ethernet frames are transmitted a byte at a time, lsb first. the first bit (i.e., the lsb of the first byte) of the destination address is the gro up/individual bit and is set one for multicast addresses and zero for unicast. this bit corresponds to bit 24 of the first word of the specific address register. the msb of the first byte of the destination address corresponds to bit 31 of the specific address register. the specific address registers are compared to the destination address of received frames once they have been activated. addresses are deactivated at reset or when the first byte [47:40] is written and activated or when the last byte [7:0] is written. if a receive frame address matches an active address, the local match si gnal is set and the store frame pulse signal is sent to the dma block via the hclk synchronization block. a frame can also be copied if a unicast or mu lticast hash match occurs, it has the broadcast address of all ones, or the copy all frames bit in the network configuration register is set. the broadcast address of 0xffffffff is recognized if the no broadcast bit in the network configuration register is zero. this sets the broadcast match signal and triggers the store frame signal. the unicast hash enable and the multicast hash enable bits in the network configuration regis- ter enable the reception of hash matched frames. so all multicast frames can be received by setting all bits in the hash register. the crc algorithm reduces the destination address to a 6-bit index into a 64-bit hash regis- ter.if the equivalent bit in the register is set, the frame is matched depending on whether the frame is multicast or unicast and the appropriate match signals are sent to the dma block. if the copy all frames bit is set in the network configuration register, the store frame pulse is always sent to the dma block as soon as any destination address is received. 28 external address (optional) 27 unknown source address (reserved for future use) 26 local address match (specific address 1 match) 25 local address match (specific address 2 match) 24 local address match (specific address 3 match) 23 local address match (specific address 4 match) 22:11 reserved; written to 0 10:0 length of frame including fcs table 105. received buffer descriptor list bit function
575 AT91RM9200 1768b?atarm?08/03 ethernet mac ( emac ) user interface table 106. emac register mapping offset register register name read/write reset 0x00 emac control register eth_ctl read/write 0x0 0x04 emac configuration register eth_cfg read/write 0x800 0x08 emac status register eth_sr read-only 0x6 0x0c emac transmit address register eth_tar read/write 0x0 0x10 emac transmit control register eth_tcr read/write 0x0 0x14 emac transmit status register eth_tsr read/write 0x18 0x18 emac receive buffer queue pointer eth_rbqp read/write 0x0 0x1c reserved ? read-only 0x0 0x20 emac receive status register eth_rsr read/write 0x0 0x24 emac interrupt status register eth_isr read/write 0x0 0x28 emac interrupt enable register eth_ier write-only ? 0x2c emac interrupt disable register eth_idr write-only ? 0x30 emac interrupt mask register eth_imr read-only 0xfff 0x34 emac phy maintenance register eth_man read/write 0x0 statistics registers (1) 0x40 frames transmitted ok register eth_fra read/write 0x0 0x44 single collision frame register eth_scol read/write 0x0 0x48 multiple collision frame register eth_mcol read/write 0x0 0x4c frames received ok register eth_ok read/write 0x0 0x50 frame check sequence error register eth_seqe read/write 0x0 0x54 alignment error register eth_ale read/write 0x0 0x58 deferred transmission frame register eth_dte read/write 0x0 0x5c late collision register eth_lcol read/write 0x0 0x60 excessive collision register eth_ecol read/write 0x0 0x64 carrier sense error register eth_cse read/write 0x0 0x68 transmit underrun error register eth_tue read/write 0x0 0x6c code error register eth_cde read/write 0x0 0x70 excessive length error register eth_elr read/write 0x0 0x74 receive jabber register eth_rjb read/write 0x0 0x78 undersize frame register eth_usf read/write 0x0 0x7c sqe test error register eth_sqee read/write 0x0 0x80 discarded rx frame register eth_drfc read/write 0x0 address registers 0x90 emac hash address high [63:32] eth_hsh read/write 0x0
576 AT91RM9200 1768b?atarm?08/03 note: for further details on the statistics registers, see table 107 on page 593. 0x94 emac hash address low [31:0] eth_hsl read/write 0x0 0x98 emac specific address 1 low, first 4 bytes eth_sa1l read/write 0x0 0x9c emac specific address 1 high, last 2 bytes eth_sa1h read/write 0x0 0xa0 emac specific address 2 low, first 4 bytes eth_sa2l read/write 0x0 0xa4 emac specific address 2 high, last 2 bytes eth_sa2h read/write 0x0 0xa8 emac specific address 3 low, first 4 bytes eth_sa3l read/write 0x0 0xac emac specific address 3 high, last 2 bytes eth_sa3h read/write 0x0 0xb0 emac specific address 4 low, first 4 bytes eth_sa4l read/write 0x0 0xb4 emac specific address 4 high, last 2 bytes eth_sa4h read/write 0x0 table 106. emac register mapping offset register register name read/write reset
577 AT91RM9200 1768b?atarm?08/03 emac control register name: eth_ctl access t yp e: read/write lb: loo p back o p tional. when set, loo p back si g nal is at hi g h level. lbl: loo p back local when set, connects etx [ 3:0 ] to erx [ 3:0 ] , etxen to erxdv, forces full du p lex and drives erxck and etxck_refck with mck divided b y 4. re: receive enable when set, enables the ethernet mac to receive data. te: transmit enable when set, enables the ethernet transmitter to send data. mpe: mana g ement port enable set to one to enable the mana g ement p ort. when zero, forces mdio to hi g h im p edance state. csr: clear statistics re g isters this bit is write-onl y . writin g a one clears the statistics re g isters. isr: increment statistics re g isters this bit is write-onl y . writin g a one increments all the statistics re g isters b y one for test p ur p oses. wes: write enable for statistics re g isters settin g this bit to one makes the statistics re g isters writable for functional test p ur p oses. bp: back pressure if this field is set, then in half-du p lex mode collisions are forced on all received frames b y transmittin g 64 bits of data ( default p attern ) . 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????bp 76543210 wes isr csr mpe te re lbl lb
578 AT91RM9200 1768b?atarm?08/03 emac configuration register name: eth_cfg access t yp e: read/write spd: s p eed set to 1 to indicate 100 mbit/sec, 0 for 10 mbit/sec. has no other functional effect. fd: full du p lex if set to 1, the transmit block i g nores the state of collision and carrier sense and allows receive while transmittin g . br: bit rate o p tional. caf: co py all frames when set to 1, all valid frames are received. nbc: no broadcast when set to 1, frames addressed to the broadcast address of all ones are not received. mti: multicast hash enable when set multicast frames are received when six bits of the crc of the destination address p oint to a bit that is set in the hash re g ister. uni: unicast hash enable when set, unicast frames are received when six bits of the crc of the destination address p oint to a bit that is set in the hash re g ister. big: receive 1522 b y tes when set, the mac receives u p to 1522 b y tes. normall y the mac receives frames u p to 1518 b y tes in len g th. this bit allows to receive extended ethernet frame with ?vlan ta g ? ( ieee 802.3ac ) eae: external address match enable o p tional. clk the s y stem clock ( mck ) is divided down to g enerate mdc ( the clock for the mdio ) . to conform with ieee standard 802.3 mdc must not exceed 2.5 mhz. at reset this field is set to 10 so that mck is divided b y 32. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? rmii rty clk eae big 76543210 uni mti nbc caf ? br fd spd clk mdc 00 mck divided by 8 01 mck divided by 16 10 mck divided by 32 11 mck divided by 64
579 AT91RM9200 1768b?atarm?08/03 rty: retr y test when set, the time between frames is alwa y s one time slot. for test p ur p oses onl y . must be cleared for normal o p eration. rmii: reduce mii when set, this bit enables the rmii o p eration mode. when reset, it selects the mii mode.
580 AT91RM9200 1768b?atarm?08/03 emac status register name: eth_sr access t yp e: read onl y link reserved. mdio 0 = mdio p in not set. 1 = mdio p in set. idle 0 = phy lo g ic is idle. 1 = phy lo g ic is runnin g . 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????idlemdiolink
581 AT91RM9200 1768b?atarm?08/03 emac transmit address register name: eth_tar access t yp e: read/write address: transmit address re g ister written with the address of the frame to be transmitted, read as the base address of the buffer bein g accessed b y the trans- mit fifo. note that if the two least si g nificant bits are not zero, transmit starts at the b y te indicated. 31 30 29 28 27 26 25 24 address 23 22 21 20 19 18 17 16 address 15 14 13 12 11 10 9 8 address 76543210 address
582 AT91RM9200 1768b?atarm?08/03 emac transmit control register name: eth_tcr access t yp e: read/write len: transmit frame len g th this re g ister is written to the number of b y tes to be transmitted excludin g the four crc b y tes unless the no crc bit is asserted. writin g these bits to an y non-zero value initiates a transmission. if the value is g reater than 1514 ( 1518 if no crc is bein g g enerated ) , an oversize frame is transmitted. this field is buffered so that a new frame can be q ueued while the p revious frame is still bein g transmitted. must alwa y s be written in address-then-len g th order. reads as the total number of b y tes to be transmitted ( i.e., this value does not chan g e as the frame is transmitted. ) frame transmission does not start until two 32-bit words have been loaded into the transmit fifo. the len g th must be g reat enou g h to ensure two words are loaded. ncrc: no crc if this bit is set, it is assumed that the crc is included in the len g th bein g written in the low-order bits and the mac does not a pp end crc to the transmitted frame. if the buffer is not at least 64 b y tes lon g , a short frame is sent. this field is buffered so that a new frame can be q ueued while the p revious frame is still bein g transmitted. reads as the value of the frame cur- rentl y bein g transmitted. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ncrc ? ? ? ? len 76543210 len
583 AT91RM9200 1768b?atarm?08/03 emac transmit status register name: eth_tsr access t yp e: read/write ovr: ethernet transmit buffer overrun software has written to the transmit address re g ister ( eth_tar ) or transmit control re g ister ( eth_tcr ) when bit bnq was not set. cleared b y writin g a one to this bit. col: collision occurred set b y the assertion of collision. cleared b y writin g a one to this bit. rle: retr y limit exceeded cleared b y writin g a one to this bit. idle: transmitter idle asserted when the transmitter has no frame to transmit. cleared when a len g th is written to transmit frame len g th p ortion of the transmit control re g ister. this bit is read-onl y . bnq: ethernet transmit buffer not queued software ma y write a new buffer address and len g th to the transmit dma controller when set. cleared b y havin g one frame read y to transmit and another in the p rocess of bein g transmitted. this bit is read-onl y . comp: transmit com p lete set when a frame has been transmitted. cleared b y writin g a one to this bit. und: transmit underrun set when transmit dma was not able to read data from memor y in time. if this ha pp ens, the transmitter forces bad crc. cleared b y writin g a one to this bit. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? und comp bnq idle rle col ovr
584 AT91RM9200 1768b?atarm?08/03 emac receive buffer queue pointer register name: eth_rbqp access t yp e: read/write address: receive buffer queue pointer written with the address of the start of the receive q ueue, reads as a p ointer to the current buffer bein g used. the receive buffer is forced to word ali g nment. 31 30 29 28 27 26 25 24 address 23 22 21 20 19 18 17 16 address 15 14 13 12 11 10 9 8 address 76543210 address
585 AT91RM9200 1768b?atarm?08/03 emac receive status register name: eth_rsr access t yp e: read/write bna: buffer not available an attem p t was made to g et a new buffer and the p ointer indicated that it was owned b y the p rocessor. the dma rereads the p ointer each time a new frame starts until a valid p ointer is found. this bit is set at each attem p t that fails even if it has not had a successful p ointer read since it has been cleared. cleared b y writin g a one to this bit. rec: frame received one or more frames have been received and p laced in memor y . cleared b y writin g a one to this bit. ovr: rx overrun the dma block was unable to store the receive frame to memor y , either because the asb bus was not g ranted in time or because a not ok hresp was returned. the buffer is recovered if this ha pp ens. cleared b y writin g a one to this bit. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????ovrrecbna
586 AT91RM9200 1768b?atarm?08/03 emac interrupt status register name: eth_isr access t yp e: read/write done: mana g ement done the phy maintenance re g ister has com p leted its o p eration. cleared on read. rcom: receive com p lete a frame has been stored in memor y . cleared on read. rbna: receive buffer not available cleared on read. tovr: transmit buffer overrun software has written to the transmit address re g ister ( eth_tar ) or transmit control re g ister ( eth_tcr ) when bnq of the transmit status re g ister ( eth_tsr ) was not set. cleared on read. tund: transmit buffer underrun ethernet transmit buffer underrun. the transmit dma did not com p lete fetch frame data in time for it to be transmitted. cleared on read. rtry: retr y limit retr y limit exceeded. cleared on read. tbre: transmit buffer re g ister em p t y software ma y write a new buffer address and len g th to the transmit dma controller. cleared b y havin g one frame read y to transmit and another in the p rocess of bein g transmitted. cleared on read. tcom: transmit com p lete set when a frame has been transmitted. cleared on read. tidle: transmit idle set when all frames have been transmitted. cleared on read. link set when link p in chan g es value. o p tional. rovr: rx overrun set when the rx overrun status bit is set. cleared on read. abt: abort set when an abort occurs durin g a dma transfer. cleared on read. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? ? ? abt rovr link tidle 76543210 tcom tbre rtry tund tovr rbna rcom done
587 AT91RM9200 1768b?atarm?08/03 emac interrupt enable register name: eth_ier access t yp e: write onl y done: mana g ement done interru p t enable rcom: receive com p lete interru p t enable rbna: receive buffer not available interru p t enable tovr: transmit buffer overrun interru p t enable tund: transmit buffer underrun interru p t enable rtry: retr y limit interru p t enable tbre: transmit buffer re g ister em p t y interru p t enable tcom: transmit com p lete interru p t enable tidle: transmit idle interru p t enable link: link interru p t enable rovr: rx overrun interru p t enable abt: abort interru p t enable 0: no effect. 1: enables the corres p ondin g interru p t. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? ? ? abt rovr link tidle 76543210 tcom tbre rtry tund tovr rbna rcom done
588 AT91RM9200 1768b?atarm?08/03 emac interrupt disable register name: eth_idr access t yp e: write onl y done: mana g ement done interru p t disable rcom: receive com p lete interru p t disable rbna: receive buffer not available interru p t disable tovr: transmit buffer overrun interru p t disable tund: transmit buffer underrun interru p t disable rtry: retr y limit interru p t disable tbre: transmit buffer re g ister em p t y interru p t disable tcom: transmit com p lete interru p t disable tidle: transmit idle interru p t disable link: link interru p t disable rovr: rx overrun interru p t disable abt: abort interru p t disable 0: no effect. 1: disables the corres p ondin g interru p t. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? ? ? abt rovr link tidle 76543210 tcom tbre rtry tund tovr rbna rcom done
589 AT91RM9200 1768b?atarm?08/03 emac interrupt mask register name: eth_imr access t yp e: read onl y done: mana g ement done interru p t mask rcom: receive com p lete interru p t mask rbna: receive buffer not available interru p t mask tovr: transmit buffer overrun interru p t mask tund: transmit buffer underrun interru p t mask rtry: retr y limit interru p t mask tbre: transmit buffer re g ister em p t y interru p t mask tcom: transmit com p lete interru p t mask tidle: transmit idle interru p t mask link: link interru p t mask rovr: rx overrun interru p t mask abt: abort interru p t mask 0: the corres p ondin g interru p t is enabled. 1: the corres p ondin g interru p t is not enabled. important note: the interru p t is disabled when the corres p ondin g bit is set. this is non-standard for at91 p roducts as g enerall y a mask bit set enables the interru p t. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? ? ? abt rovr link tidle 76543210 tcom tbre rtry tund tovr rbna rcom done
590 AT91RM9200 1768b?atarm?08/03 emac phy maintenance register name: eth_man access t yp e: read/write writin g to this re g ister starts the shift re g ister that controls the serial connection to the phy. on each shift c y cle the mdio p in becomes e q ual to the msb of the shift re g ister and lsb of the shift re g ister becomes e q ual to the value of the mdio p in. when the shiftin g is com p lete an interru p t is g enerated and the idle field is set in the network status re g ister. when read, g ives current shifted value. data for a write o p eration this is written with the data to be written to the phy. after a read o p eration this contains the data read from the phy. code must be written to 10 in accordance with ieee standard 802.3. reads as written. rega re g ister address. s p ecifies the re g ister in the phy to access. phya phy address. normall y is 0. rw read/write o p eration. 10 is read. 01 is write. an y other value is an invalid phy mana g ement frame. high must be written with 1 to make a valid phy mana g ement frame. conforms with ieee standard 802.3. low must be written with 0 to make a valid phy mana g ement frame. conforms with ieee standard 802.3. 31 30 29 28 27 26 25 24 low high rw phya 23 22 21 20 19 18 17 16 phya rega code 15 14 13 12 11 10 9 8 data 76543210 data
591 AT91RM9200 1768b?atarm?08/03 emac hash address high register name: eth_hsh access t yp e: read/write addr hash address bits 63 to 32. emac hash address low register name: eth_hsl access t yp e: read/write addr hash address bits 31 to 0. 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr
592 AT91RM9200 1768b?atarm?08/03 emac specific address (1, 2, 3 and 4) high register name: eth_sa1h,...eth_sa4h access t yp e: read/write addr unicast addresses ( 1, 2, 3 and 4 ) , bits 47:32. emac specific address (1, 2, 3 and 4) low register name: eth_sa1l,...eth_sa4l access t yp e: read/write addr unicast addresses ( 1, 2, 3 and 4 ) , bits 31:0. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 addr 76543210 addr 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr
593 AT91RM9200 1768b?atarm?08/03 emac statistics register block registers these re g isters reset to zero on a read and remain at all ones when the y count to their maximum value. the y should be read fre q uentl y enou g h to p revent loss of data. the statistics re g ister block contains the re g isters found in table 107 . table 107. statistics register block register register name description frames transmitted ok register eth_fra a 24-bit register counting the number of frames successfully transmitted. single collision frame register eth_scol a 16-bit register counting the number of frames experiencing a single collision before being transmitted and experiencing no carrier loss nor underrun. multiple collision frame register eth_mcol a 16-bit register counting the number of frames experiencing between two and fifteen collisions prior to being transmitted (62 - 1518 bytes, no carrier loss, no underrun). frames received ok register eth_ok a 24-bit register counting the number of good frames received, i.e., address recognized. a good frame is of length 64 to 1518 bytes and has no fcs, alignment or code errors. frame check sequence error register eth_seqe an 8-bit register counting address-recognized frames that are an integral number of bytes long, that have bad crc and that are 64 to 1518 bytes long. alignment error register eth_ale an 8-bit register counting frames that: - are address-recognized, - are not an integral number of bytes long, - have bad crc when their length is truncated to an integral number of bytes, - are between 64 and 1518 bytes long. deferred transmission frame register eth_dte a 16-bit register counting the number of frames experiencing deferral due to carrier sense active on their first attempt at transmission (no underrun or collision). late collision register eth_lcol an 8-bit register counting the number of frames that experience a collision after the slot time (512 bits) has expired. no carrier loss or underrun. a late collision is counted twice, i.e., both as a collision and a late collision. excessive collision register eth_ecol an 8-bit register counting the number of frames that failed to be transmitted because they experienced 16 collisions (64 - 1518 bytes, no carrier loss or underrun). carrier sense error register eth_cse an 8-bit register counting the number of frames for which carrier sense was not detected and that were maintained in half-duplex mode one slot time (512 bits) after the start of transmission (no excessive collision). transmit underrun error register eth_tue an 8-bit register counting the number of frames not transmitted due to a transmit dma underrun. if this register is incremented, then no other register is incremented. code error register eth_cde an 8-bit register counting the number of frames that are address-recognized, had rxer asserted during reception. if this counter is incremented, then no other counters are incremented. excessive length error register eth_elr an 8-bit register counting the number of frames received exceeding 1518 bytes in length but that do not have either a crc error, an alignment error or a code error. receive jabber register eth_rjb an 8-bit register counting the number of frames received exceeding 1518 bytes in length and having either a crc error, an alignment error or a code error.
594 AT91RM9200 1768b?atarm?08/03 undersize frame register eth_usf an 8-bit register counting the number of frames received less that are than 64 bytes in length but that do not have either a crc error, an alignment error or a code error. sqe test error register eth_sqee an 8-bit register counting the number of frames where pin ecol was not asserted within a slot time of pin etxen being deasserted. discarded rx frame register eth_drfc this 16-bit counter is incremented every time an address-recognized frame is received but cannot be copied to memory because the receive buffer is available. table 107. statistics register block (continued) register register name description
595 AT91RM9200 1768b?atarm?08/03 AT91RM9200 electrical characteristics absolute maximum ratings table 108. absolute maximum ratings* operating temperature (industrial) ........-40 c to +85 c *notice: stresses beyond those listed under ?absolute maxi- mum ratings? may cause permanent damage to the device. this is a stress rating only and func- tional operation of the device at these or other con- ditions beyond those indicated in the operational sections of this specification is not implied. expo- sure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ............................ -60c to +150c voltage on input pins with respect to ground ............................-0.3v to +3.6v maximum operating voltage (v ddcore , v ddpll and v ddosc ) ............................... 1.95v maximum operating voltage (v ddiom and v ddiop ) ................................................. 3.6v dc output current (sda10, sdcke, sdwe, ras, cas) .................. 16 ma dc output current (any other pin) ........................................................ 8 ma
596 AT91RM9200 1768b?atarm?08/03 dc characteristics the following characteristics are applicable to the operating temperature range: t a = -40c to 85c, unless otherwise spec- ified and are certified for a junction temperature up to t j = 100c. notes: 1. v dd is applicable to v ddiom , v ddiop , v ddpll and v ddosc 2. i o = output current. table 109. dc characteristics symbol parameter conditions min typ max units v ddcore dc supply core 1.65 1.95 v v ddosc dc supply oscillator 1.65 1.95 v v ddpll dc supply pll 1.65 1.95 v v ddiom dc supply memory i/os v ddcore v ddcore + 1.5 or 3.6 v v ddiop dc supply peripheral i/os v ddcore v ddcore + 1.5 or 3.6 v v il input low-level voltage -0.3 0.8 v v ih input high-level voltage 2 v dd + 0.3 (1) v v ol output low-level voltage sda10, sdcke, sdwe, ras, cas pins: i ol = 16 ma (2) i ol = 0 ma (2) 0.4 0.2 v other pins: i ol = 8 ma (2) i ol = 0 ma (2) 0.4 0.2 v oh output high-level voltage sda10, sdcke, sdwe, ras, cas pins: i oh = 16 ma (2) i oh = 0 ma (2) v dd - 0.4 (1) v dd - 0.2 (1) v other pins: i oh = 8 ma (2) i oh = 0 ma (2 v dd - 0.4 (1) v dd - 0.2 (1) i leak input leakage current pullup resistors disabled 1 a i pull input pull-up current v dd = 3.0v (1) , v in = 0 129 a v dd = 3.6v (1) , v in = 0 322 c in input capacitance 208-pqfp package 8.8 pf 256-lfbga package 7.6 i sc static current on v ddcore = 2v, mck = 0 hz t a = 25c 179 1157 a all inputs driven tms, tdi, tck, nrst = 1 t a = 85c 1610 7989
597 AT91RM9200 1768b?atarm?08/03 clocks characteristics these parameters are given in the following conditions: v ddcore = 1.8v ambient temperature = 25c the temperature derating factor described in the section ?temperature derating factor? on page 604 and v ddcore volt- age derating factor described in the section ?vddcore voltage derating factor? on page 604 are both applicable to these characteristics. processor clock characteristics master clock characteristics xin clock characteristics (1) notes: 1. these characteristics apply only when the main oscillator is in bypass mode (i.e., when moscen = 0 in the ckgr_mor register. see ?pmc clock generator main oscillator register? on page 276.) table 110. processor clock waveform parameters symbol parameter conditions min max units 1/(t cppck ) processor clock frequency 209.0 mhz t cppck processor clock period 4.8 ns t chmck master clock high half-period 2.2 ns t clmck master clock low half-period 2.2 ns table 111. master clock waveform parameters symbol parameter conditions min max units 1/(t cpmck ) master clock frequency 80.0 mhz t cpmck master clock period 12.5 ns t chmck master clock high half-period 6.3 ns t clmck master clock low half-period 6.3 ns table 112. xin clock electrical characteristics symbol parameter conditions min max units 1/(t cpxin ) xin clock frequency 50.0 mhz t cpxin xin clock period 20.0 ns t chxin xin clock high half-period 0.4 x t cpxin 0.6 x t cpxin t clxin xin clock low half-period 0.4 x t cpxin 0.6 x t cpxin c in xin input capacitance note (1) 25 pf r in xin pulldown resistor note (1) 500 kohm
598 AT91RM9200 1768b?atarm?08/03 power consumption the values in table 113 and table 114 are measured values on the AT91RM9200dk evalua- tion board with operating conditions as follows: v ddio = 3.3v v ddcore = v ddpll = v ddosc = 1.8v t a = 25 c mck = 60 mhz pck = 180 mhz slck = 32.768 khz these figures represent the power consumption measured on the v ddcore power supply. note: 1. code in internal sram. notes: 1. code in internal sram. 2. power consumption on the v ddpll power supply. 3. power consumption on the v ddosc power supply. table 113. power consumption for pmc modes (1) mode conditions consumption unit normal arm core clock enabled. all peripheral clocks deactivated. 31.7 ma idle arm core clock disabled and waiting for the next interrupt. all peripheral clocks deactivated. 15.0 slow clock main oscillator and plls are switched off. processor and all peripherals run at slow clock. 1.7 standby combination of idle and slow clock modes. 1.7 table 114. power consumption by peripheral (1) peripheral consumption unit pio controller 0.6 ma usart 1.6 mci 1.9 udp 1.5 twi 0.4 spi 1.4 ssc 1.8 timer counter channel 0.4 uhp 3.4 emac 4.3 pmc pll (2) slow clock oscillator (3) main oscillator (3) 3144 858 350 ua na ua
599 AT91RM9200 1768b?atarm?08/03 crystal oscillators characteristics 32 khz oscillator characteristics note: 1. r s is the equivalent series resistance, c l is the equivalent load capacitance main oscillator characteristics pll characteristics table 115. 32 khz oscillator characteristics symbol parameter conditions min typ max unit 1/(t cp32khz ) crystal oscillator frequency 32.768 khz duty cycle measured at the pck output pin 40 50 60 % t st startup time v ddosc = 1.8v r s = 50 k ? , c l = 12.5 pf (1) 900 ms table 116. main oscillator characteristics symbol parameter conditions min typ max unit 1/(t cpmain ) crystal oscillator frequency 3 16 20 mhz c l1 , c l2 internal load capacitance (cl1 = cl2) 25 pf c l equivalent load capacitance c l1 = c l2 = 25 pf 12.5 pf duty cycle measured at the pck output pin 40 50 60 % t st startup time v ddpll = 1.8v 1/(t cpmain ) = 3 mhz without any capacitor connected to the main oscillator pins (xin and xout) 14.5 ms table 117. phase lock loop characteristics symbol parameter conditions min typ max unit f out output frequency 80 240 mhz f in input frequency 1 32 mhz k o vco gain 120 190 300 mhz/v i p pump current 36 44 60 a
600 AT91RM9200 1768b?atarm?08/03 transceiver characteristics electrical characteristics table 118. electrical parameters symbol parameter conditions min typ max unit input levels v il low level 0.8 v v ih high level 2.0 v v di differential input sensivity |(d+) - (d-)| 0.2 v v cm differential input common mode range 0.8 2.5 v c in transceiver capacitance capacitance to ground on each line 20 pf i hi-z state data line leakage 0v < v in < 3.3v -5 +5 a r ext recommended external usb series resistor in series with each usb pin with 5% 27 output levels v ol low level output measured with rl of 1.425 kohm tied to 3.6v 0.3 v v oh high level output measured with rl of 14.25 kohm tied to gnd 2.8 v v crs output signal crossover volatge measure conditions described in figure 266 1.3 2.0 v
601 AT91RM9200 1768b?atarm?08/03 switching characteristics figure 266. usb data signal rise and fall times table 119. in slow mode symbol parameter conditions min typ max unit t fr transition rise time c load = 400 pf 75 300 ns t fe transition fall time c load = 400 pf 75 300 ns t frfm rise/fall time matching c load = 400 pf 80 120 % table 120. in full speed symbol parameter conditions min typ max unit t fr transition rise time c load = 50 pf 4 20 ns t fe transition fall time c load = 50 pf 4 20 ns t frfm rise/fall time matching 90 111.11 % 10% 10% 90% v crs t r t f differential data lines rise time fall time fosc = 6mhz/750khz r ext =27 ohms c load buffer (b) (a)
602 AT91RM9200 1768b?atarm?08/03
603 AT91RM9200 1768b?atarm?08/03 AT91RM9200 ac characteristics applicable conditions and derating data conditions and timings computation the delays are given as typical values in the following conditions: v ddiom = 3.3v v ddcore = 1.8v ambient temperature = 25c load capacitance = 0 pf the output level change detection is (0.5 x v ddiom ). the input level is (0.3 x v ddiom ) for a low-level detection and is (0.7 x v ddiom ) for a high- level detection. the minimum and maximum values given in the ac characteristics tables of this datasheet take into account process variation and design. in order to obtain the timing for other condi- tions, the following equation should be used: where: t is the derating factor in temperature given in figure 267 on page 604. vddcore is the derating factor for the core power supply given in figure 268 on page 604. t datasheet is the minimum or maximum timing value given in this datasheet for a load capacitance of 0 pf. vddiom is the derating factor for the iom power supply given in figure 269 on page 605. c signa l is the capacitance load on the considered output pin (1) . csignal is the load derating factor depending on the capacitance load on the related output pins given in min and max in this datasheet. the input delays are given as typical values. note: 1. the user must take into account the package capacitance load contribution (c in ) described in table 109, ?dc characteristics,? on page 596. t t vddcore t datasheet () vddio m c signal csignal () () + () =
604 AT91RM9200 1768b?atarm?08/03 temperature derating factor figure 267. derating curve for different operating temperatures v ddcore voltage derating factor figure 268. derating curve for different core supply voltages 0.8 0.9 1 1.1 1.2 -60 -40 -20 0 20 40 60 80 100 120 140 160 operating temperature (c) derating factor 0.5 1 1.5 2 2.5 3 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4 1.45 1.5 1.55 1.6 1.65 1.7 1.75 1.8 1.85 1.9 1.95 core supply voltage (v) derating factor
605 AT91RM9200 1768b?atarm?08/03 v ddiom voltage derating factor figure 269. derating curve for different io supply voltages note: the derating factor in this example is applicable only to timings related to output pins. 0.5 1 1.5 2 2.5 3 3.5 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 i/o supply voltage (v ) derating factor
606 AT91RM9200 1768b?atarm?08/03 ebi timings smc signals relative to mck table 121, table 122 and table 123 show timings relative to operating condition limits defined in the section ?conditions and timings computation? on page 603. notes: 1. the derating factor is not to be applied to t cpmck . 2. nacss = number of address to chip select setup cycles inserted. 3. n = number of standard wait states inserted. table 121. general-purpose smc signals symbol parameter conditions min max units smc 1 mck falling to nub valid c nub = 0 pf 5.0 7.5 ns c nub derating 0.028 0.045 ns/pf smc 2 mck falling to nlb/a0 valid c nlb = 0 pf 4.9 7.5 ns c nlb derating 0.028 0.045 ns/pf smc 3 mck falling to a1 - a25 valid c add = 0 pf 4.9 7.4 ns c add derating 0.028 0.045 ns/pf smc 4 mck falling to chip select change (no address to chip select setup) c ncs = 0 pf 4.3 6.5 ns c ncs derating 0.028 0.045 ns/pf smc 5 mck falling to chip select active (address to chip select setup) (1) c ncs = 0 pf (nacss x t cpmck ) + 4.3 (2) (nacss x t cpmck ) + 6.5 (2) ns c ncs derating 0.028 0.045 ns/pf smc 6 chip select inactive to mck falling (address to chip select setup) (1) c ncs = 0 pf (nacss x t cpmck ) + 4.4 (2) (nacss x t cpmck ) + 6.5 (2) ns c ncs derating 0.028 0.045 ns/pf smc 7 ncs minimum pulse width (address to chip select setup) (1) c ncs = 0 pf (((n + 2) - (2 x nacss)) x t cpmck ) (2) (3) ns smc 8 nwait minimum pulse width (1) t cpmck ns
607 AT91RM9200 1768b?atarm?08/03 . table 122. smc write signals symbol parameter conditions min max units smc 10 mck rising to nwr active (no wait states) (5) c nwr = 0 pf 4.8 7.2 ns c nwr derating 0.028 0.045 ns/pf smc 11 mck rising to nwr active (wait states) c nwr = 0 pf 4.8 7.2 ns c nwr derating 0.028 0.045 ns/pf smc 12 mck falling to nwr inactive (no wait states) (5) c nwr = 0 pf 4.8 7.2 ns c nwr derating 0.028 0.045 ns/pf smc 13 mck rising to nwr inactive (wait states) c nwr = 0 pf 4.8 7.2 ns c nwr derating 0.028 0.045 ns/pf smc 14 mck rising to d0 - d15 out valid c data = 0 pf 4.1 7.9 ns c data derating 0.028 0.044 ns/pf smc 15 nwr high to nub change (5) c nub = 0 pf 3.4 ns c nub derating 0.028 ns/pf smc 16 nwr high to nlb/a0 change (5) c nlb = 0 pf 3.7 ns c nlb derating 0.028 ns/pf smc 17 nwr high to a1 - a25 change (5) c add = 0 pf 3.3 ns c add derating 0.028 ns/pf smc 18 nwr high to chip select inactive (5) c ncs = 0 pf 3.3 ns c ncs derating 0.028 ns/pf smc 19 data out valid before nwr high (no wait states) (1) (5) c = 0 pf t chmck - 0.8 ns c data derating - 0.044 ns/pf c nwr derating 0.045 ns/pf smc 20 data out valid before nwr high (wait states) (1) (5) c = 0 pf n x t cpmck - 0.6 (2) ns c data derating - 0.044 ns/pf c nwr derating 0.045 ns/pf smc 21 data out valid after nwr high (no wait states) (1) (5) c = 0 pf t clmck - 1.0 ns c data derating - 0.044 ns/pf c nwr derating 0.045 ns/pf smc 22 data out valid after nwr high (wait states without hold cycles) (1) (5) c = 0 pf t chmck - 1.2 ns c data derating - 0.044 ns/pf c nwr derating 0.045 ns/pf smc 23 data out valid after nwr high (wait states with hold cycles) (1) (5) c = 0 pf h x t cpmck - 1.1 (4) ns c data derating - 0.044 ns/pf c nwr derating 0.045 ns/pf
608 AT91RM9200 1768b?atarm?08/03 notes: 1. the derating factor is not to be applied to t clmck , t chmck or t cpmck . 2. n = number of standard wait states inserted. 3. nacss = number of address to chip select setup cycles inserted. 4. h = number of hold cycles inserted. 5. not applicable when address to chip select setup cycles are inserted. smc 24 data out valid before ncs high (address to chip select setup cycles) (1) c = 0 pf (((n + 1) - nacss) x t cpmck ) + t chmck - 1.4 (2) (3) ns c data derating - 0.044 ns/pf c ncs derating 0.045 ns/pf smc 25 data out valid after ncs high (address to chip select setup cycles) (1) c = 0 pf nacss x t cpmck - 0.4 (3) ns c data derating - 0.044 ns/pf c ncs derating 0.045 ns/pf smc 26 nwr minimum pulse width (no wait states) (1) (5) c nwr = 0 pf t chmck - 0.1 ns c nwr derating 0.002 ns/pf smc 27 nwr minimum pulse width (wait states) (1) (5) c nwr = 0 pf n x t cpmck (2) ns c nwr derating 0.002 ns/pf smc 28 nwr minimum pulse width (address to chip select setup cycles) (1) c nwr = 0 pf (n + 1) x t cpmck (2) ns c nwr derating 0.002 ns/pf table 122. smc write signals (continued) symbol parameter conditions min max units
609 AT91RM9200 1768b?atarm?08/03 table 123. smc read signals symbol parameter conditions min max units smc 29 mck falling to nrd active (1) (7) c nrd = 0 pf 4.5 6.8 ns c nrd derating 0.028 0.045 ns/pf smc 30 mck rising to nrd active (2) c nrd = 0 pf 4.7 7.0 ns c nrd derating 0.028 0.045 ns/pf smc 31 mck falling to nrd inactive (1) (7) c nrd = 0 pf 4.5 6.8 ns c nrd derating 0.028 0.045 ns/pf smc 32 mck falling to nrd inactive (2) c nrd = 0 pf 4.5 6.8 ns c nrd derating 0.028 0.045 ns/pf smc 33 d0-d15 in setup before mck falling (8) 0.8 ns smc 34 d0-d15 in hold after mck falling (9) 1.7 ns smc 35 nrd high to nub change (3) c nub = 0 pf (h x t cpmck ) + 0.5 (6) (h x t cpmck ) + 0.8 (6) ns c nub derating 0.028 0.045 ns/pf smc 36 nrd high to nlb/a0 change (3) c nlb = 0 pf (h x t cpmck ) + 0.4 (6) (h x t cpmck ) + 0.7 (6) ns c nlb derating 0.028 0.045 ns/pf smc 37 nrd high to a1-a25 change (3) c add = 0 pf (h x t cpmck ) + 0.3 (6) (h x t cpmck ) + 0.6 (6) ns c add derating 0.028 0.045 ns/pf smc 38 nrd high to chip select inactive (3) c ncs = 0 pf (h x t cpmck ) - 0.3 (6) (h x t cpmck ) - 0.2 (6) ns c ncs derating - 0.045 - 0.028 ns/pf smc 39 chip select inactive to nrd high (3) c ncs = 0 pf (nacss x t cpmck ) + 0.2 (5) (nacss x t cpmck ) + 0.3 (5) ns c ncs derating 0.028 0.045 ns/pf smc 40 data setup before nrd high (8) c nrd = 0 pf 7.5 ns c nrd derating 0.045 ns/pf smc 41 data hold after nrd high (9) c nrd = 0 pf -3.4 ns c nrd derating - 0.028 ns/pf smc 42 data setup before ncs high c nrd = 0 pf 7.3 ns c nrd derating 0.045 ns/pf smc 43 data hold after ncs high c nrd = 0 pf -3.2 ns c nrd derating - 0.028 ns/pf smc 44 nrd minimum pulse width (1) (3) (7) c nrd = 0 pf n x t cpmck - 0.02 (4) ns c nrd derating 0.002 ns/pf
610 AT91RM9200 1768b?atarm?08/03 notes: 1. early read protocol. 2. standard read protocol. 3. the derating factor is not to be applied to t chmck or t cpmck . 4. n = number of standard wait states inserted. 5. nacss = number of address to chip select setup cycles inserted. 6. h = number of hold cycles inserted. 7. not applicable when address to chip select setup cycles are inserted. 8. only one of these two timings needs to be met. 9. only one of these two timings needs to be met. smc 45 nrd minimum pulse width (2) (3) (7) c nrd = 0 pf n x t chmck + t chmck - 0.2 (4) ns c nrd derating 0.002 ns/pf smc 46 nrd minimum pulse width (2) (3) c nrd = 0 pf ((n + 1) x t chmck ) + t chmck - 0.2 (4) ns c nrd derating 0.002 ns/pf table 123. smc read signals (continued) symbol parameter conditions min max units
611 AT91RM9200 1768b?atarm?08/03 figure 270. smc signals relative to mck in memory interface mode notes: 1. early read protocol. 2. standard read protocol with or without setup and hold cycles. mck internal signal nrd (1) nrd (2) ncs nwait a1 - a25 d0 - d15 read nwr d0 - d15 to write nub/nlb/a0 smc 4 smc 4 smc 4 smc 4 smc 3 smc 3 smc 1 smc 2 smc 1 smc 2 smc 29 smc 31 smc 30 smc 32 smc 10 smc 12 smc 14 smc 40 smc 41 smc 33 smc 34 smc 44 smc 45 smc 19 smc 21 smc 18 smc 17 smc 15 smc 16 smc 26 smc 38 smc 37 smc 35 smc 36 smc 1 smc 2 smc 3 smc 4 smc 8 smc 29 smc 30 smc 31 smc 32 smc 33 smc 34 smc 35 smc 36 smc 37 smc 38 smc 4 smc 40 smc 41 smc 44 smc 45 smc 4 smc 4 smc 3 smc 1 smc 2 smc 11 smc 13 smc 27 smc 14 smc 22 smc 20 smc 1 smc 2 smc 3 smc 30 smc 32 smc 4 smc 4 smc 33 smc 34 smc 35 smc 36 smc 37 smc 38 smc 40 smc 41 smc 45 smc 1 smc 2 smc 3 smc 4 smc 4 smc 11 smc 13 smc 14 smc 20 smc 23 smc 27
612 AT91RM9200 1768b?atarm?08/03 figure 271. smc signals relative to mck in lcd interface mode notes: 1. standard read protocol only. 2. with standard wait states inserted only. mck internal signal nrd (1) ncs nwait a1 - a25 d0 - d15 read nwr (2) d0 - d15 to write nub/nlb/a0 smc 8 smc 1 smc 2 smc 1 smc 2 smc 3 smc 3 smc 5 smc 6 smc 7 smc 5 smc 6 smc 7 smc 30 smc 33 smc 34 smc 32 smc 35 smc 36 smc 37 smc 39 smc 42 smc 43 smc 46 smc 11 smc 13 smc 14 smc 24 smc 25 smc 28
613 AT91RM9200 1768b?atarm?08/03 sdramc signals relative to sdck table 124 and table 125 below show timings relative to opera ting condition limits defined in the section ?conditions and timings computation? on page 603. table 124. sdramc clock signal symbol parameter conditions min max units 1/(t cpsdck ) sdram controller clock frequency 80.0 mhz t cpsdck sdram controller clock period 12.5 ns t chsdck sdram controller clock high half-period 5.6 ns t clsdck sdram controller clock low half-period 6.9 ns table 125. sdramc signals symbol parameter conditions min max units sdramc 1 sdcke high before sdck rising edge (1) c sdcke = 0 pf t clmck + 1.2 ns c sdcke derating 0.015 ns/pf sdramc 2 sdcke low after sdck rising edge (1) c sdcke = 0 pf t chmck - 1.4 ns c sdcke derating - 0.023 ns/pf sdramc 3 sdcke low before sdck rising edge (1) c sdcke = 0 pf t clmck + 1.0 ns c sdcke derating 0.015 ns/pf sdramc 4 sdcke high after sdck rising edge (1) c sdcke = 0 pf t chmck - 1.7 ns c sdcke derating - 0.023 ns/pf sdramc 5 sdcs low before sdck rising edge (1) c sdcs = 0 pf t clmck + 1.2 ns c sdcs derating 0.028 ns/pf sdramc 6 sdcs high after sdck rising edge (1) c sdcs = 0 pf t chmck - 1.9 ns c sdcs derating - 0.045 ns/pf sdramc 7 ras low before sdck rising edge (1) c ras = 0 pf t clmck + 0.6 ns c ras derating 0.015 ns/pf sdramc 8 ras high after sdck rising edge (1) c ras = 0 pf t chmck - 1.1 ns c ras derating - 0.023 ns/pf sdramc 9 sda10 change before sdck rising edge (1) c sda10 = 0 pf t clmck + 0.8 ns c sda10 derating 0.015 ns/pf sdramc 10 sda10 change after sdck rising edge (1) c sda10 = 0 pf t chmck - 1.2 ns c sda10 derating - 0.023 ns/pf sdramc 11 address change before sdck rising edge (1) c add = 0 pf t clmck + 0.6 ns c add derating 0.028 ns/pf sdramc 12 address change after sdck rising edge (1) c add = 0 pf t chmck - 1.5 ns c add derating - 0.045 ns/pf
614 AT91RM9200 1768b?atarm?08/03 note: 1. the derating factor is not to be applied to t clmck or t chmck . sdramc 13 bank change before sdck rising edge (1) c ba = 0 pf t clmck + 0.8 ns c ba derating 0.028 ns/pf sdramc 14 bank change after sdck rising edge (1) c ba = 0 pf t chmck - 1.6 ns c ba derating - 0.045 ns/pf sdramc 15 cas low before sdck rising edge (1) c cas = 0 pf t clmck + 0.9 ns c cas derating 0.015 ns/pf sdramc 16 cas high after sdck rising edge (1) c cas = 0 pf t chmck - 1.5 ns c cas derating - 0.023 ns/pf sdramc 17 dqm change before sdck rising edge (1) c dqm = 0 pf t clmck + 0.7 ns c dqm derating 0.028 ns/pf sdramc 18 dqm change after sdck rising edge (1) c dqm = 0 pf t chmck - 1.4 ns c dqm derating - 0.045 ns/pf sdramc 19 d0-d15 in setup before sdck rising edge 1.3 ns sdramc 20 d0-d15 in hold after sdck rising edge 0.03 ns sdramc 21 d16-d31 in setup before sdck rising edge 2.0 ns sdramc 22 d16-d31 in hold after sdck rising edge -0.2 ns sdramc 23 sdwe low before sdck rising edge c sdwe = 0 pf t clmck + 1.0 ns c sdwe derating 0.015 ns/pf sdramc 24 sdwe high after sdck rising edge c sdwe = 0 pf t chmck - 1.8 ns c sdwe derating -0.023 ns/pf sdramc 25 d0-d15 out valid before sdck rising edge c = 0 pf t clmck - 2.7 ns c data derating -0.044 ns/pf sdramc 26 d0-d15 out valid after sdck rising edge c = 0 pf t chmck - 2.4 ns c data derating -0.044 ns/pf sdramc 27 d16-d31 out valid before sdck rising edge c = 0 pf t clmck - 3.2 ns c data derating -0.044 ns/pf sdramc 28 d16-d31 out valid after sdck rising edge c = 0 pf t chmck - 2.4 ns c data derating -0.044 ns/pf table 125. sdramc signals (continued) symbol parameter conditions min max units
615 AT91RM9200 1768b?atarm?08/03 figure 272. sdramc signals relative to sdck ras a0 - a9, a11 - a13 d0 - d15 read sdck sda10 d0 - d15 to write sdramc 1 sdcke sdramc 2 sdramc 3 sdramc 4 sdcs sdramc 5 sdramc 6 sdramc 5 sdramc 6 sdramc 5 sdramc 6 sdramc 7 sdramc 8 cas sdramc 15 sdramc 16 sdramc 15 sdramc 16 sdwe sdramc 23 sdramc 24 sdramc 9 sdramc 10 sdramc 9 sdramc 10 sdramc 9 sdramc 10 sdramc 11 sdramc 12 sdramc 11 sdramc 12 sdramc 11 sdramc 12 ba0/ba1 sdramc 13 sdramc 14 sdramc 13 sdramc 14 sdramc 13 sdramc 14 sdramc 17 sdramc 18 sdramc 17 sdramc 18 dqm0 - dqm3 sdramc 19 sdramc 20 d16 - d31 read sdramc 21 sdramc 22 sdramc 25 sdramc 26 d16 - d31 to write sdramc 27 sdramc 28
616 AT91RM9200 1768b?atarm?08/03 bfc signals relative to bfck table 126, table 127 and table 128 show timings relative to operating condition limits defined in the section ?conditions and timings computation? on page 603. notes: 1. field bfcc = 1 in register bfc_mr, see ?burst flash controller mode register? on page 221. 2. field bfcc = 2 in register bfc_mr, see ?burst flash controller mode register? on page 221. 3. field bfcc = 3 in register bfc_mr, see ?burst flash controller mode register? on page 221. table 126. bfc clock signal symbol parameter conditions min max units 1/(t cpbfck ) bf controller clock frequency bfck is mck (1) 80.0 mhz bfck is mck/2 (2) 40.0 mhz bfck is mck/4 (3) 20.0 mhz t cpbfck bf controller clock period bfck is mck (1) 12.5 ns bfck is mck/2 (2) 25.0 ns bfck is mck/4 (3) 50.0 ns t chbfck bf controller clock high half-period bfck is mck (1) 6.5 ns bfck is mck/2 (2) 12.8 ns bfck is mck/4 (3) 25.3 ns t clbfck bf controller clock low half-period bfck is mck (1) 6.1 ns bfck is mck/2 (2) 12.3 ns bfck is mck/4 (3) 24.8 ns table 127. bfc signals in asynchronous mode symbol parameter conditions min max units bfc 1 bfck rising to a1-a25 valid (1) c add = 0 pf t clbfck - 0.2 ns c add derating - 0.028 ns/pf bfc 2 bfck rising to a1-a25 change (1) c add = 0 pf t clbfck - 1.0 ns c add derating - 0.045 ns/pf bfc 3 bfck falling to bfavd active (1) c bfavd = 0 pf t clbfck - 1.1 t clbfck - 0.3 ns c bfavd derating - 0.044 - 0.028 ns/pf bfc 4 bfck falling to bfavd inactive (1) c bfavd = 0 pf t clbfck - 1.8 t clbfck + 0.2 ns c bfavd derating - 0.044 0.044 ns/pf bfc 5 bfavd minimum pulse width (1) c bfavd = 0 pf t cpbfck + 1.0 ns c bfavd derating 0.001 ns/pf bfc 6 bfck rising to bfoe active c bfoe = 0 pf - 0.4 0.1 ns c bfoe derating - 0.044 0.044 ns/pf bfc 7 bfck rising to bfoe inactive c bfoe = 0 pf - 1.1 0.7 ns c bfoe derating - 0.044 0.044 ns/pf
617 AT91RM9200 1768b?atarm?08/03 notes: 1. the derating factor is not to be applied to t cpbfck . 2. a = number of address valid latency cycles defined in the bfc_mr avl field. 3. o = number of output enable latency cycles defined in the bfc_mr oel field. 4. applicable only with multiplexed address and data buses. 5. only one of these two timings needs to be met. 6. only one of these two timings needs to be met. bfc 8 bfoe minimum pulse width (1) c bfoe = 0 pf (a x t cpbfck ) + 0.9 (2) ns c bfoe derating 0.028 ns/pf bfc 9 d0-d15 in setup before bfck rising edge (5 ) - 0.1 ns bfc 10 d0-d15 in hold after bfck rising edge (6) 1.0 ns bfc 11 data setup before bfoe high (5) c bfoe = 0 pf - 0.9 ns c bfoe derating - 0.044 ns/pf bfc 12 data hold after bfoe high (6) c bfoe = 0 pf 2.0 ns c bfoe derating 0.028 ns/pf bfc 13 bfck rising to bfwe active c bfwe = 0 pf - 0.6 - 0.05 ns c bfwe derating - 0.044 - 0.028 ns/pf bfc 14 bfck rising to bfwe inactive c bfwe = 0 pf - 1.3 0.5 ns c bfwe derating - 0.044 0.044 ns/pf bfc 15 bfck rising to ad0-ad15 valid (1 ) (4) c data = 0 pf t clbfck - 0.2 ns c data derating - 0.028 ns/pf bfc 16 bfck rising to ad0-ad15 not valid (1 ) (4) c data = 0 pf t clbfck - 0.8 ns c data derating - 0.044 ns/pf bfc 17 data out valid before bfck rising (1 ) (5) c data = 0 pf t clbfck + 0.5 ns c data derating 0.028 ns/pf bfc 18 data out valid after bfck rising (1 ) (6) c data = 0 pf t chbfck + 0.7 ns c data derating 0.028 ns/pf bfc 19 data out valid before bfwe high (1 ) (5) c = 0 pf t clbfck - 0.5 ns c data derating - 0.028 ns/pf c bfwe derating 0.044 ns/pf bfc 20 data out valid after bfwe high (1 ) (6) c = 0 pf t chbfck + 0.3 ns c data derating 0.028 ns/pf c bfwe derating - 0.044 ns/pf bfc 21 number of address valid latency cycles (1 ) ((a + 1) x t cpbfck ) (2) ((a + 1) x t cpbfck ) (2) ns bfc 22 number of output enable latency cycles (1) (o x t cpbfck ) (3) (o x t cpbfck ) (3) ns table 127. bfc signals in asynchronous mode (continued) symbol parameter conditions min max units
618 AT91RM9200 1768b?atarm?08/03 figure 273. bfc signals relative to bfck in asynchronous mode note: 1. bfcs is asserted as soon as the bfcom field in bfc_mr is different from 0. bfavd d0 - d15 read bfck internal signal d0 - d15 to write bfcs (1) a1 - a25 bfoe bfwe bfc 1 bfc 1 bfc 3 bfc 4 bfc 5 bfc 3 bfc 4 bfc 5 bfc 6 bfc 7 bfc 8 bfc 9 bfc 10 bfc 12 bfc 11 bfc 13 bfc 14 bfc 15 bfc 16 bfc 21 bfc 22 bfc 21 bfc 15 bfc 16 bfc 17 bfc 18 bfc 19 bfc 20
619 AT91RM9200 1768b?atarm?08/03 notes: 1. the derating factor is not to be applied to t cpbfck . 2. a = number of address valid latency cycles defined in the bfc_mr avl field. 3. o = number of output enable latency cycles defined in the bfc_mr oel field. 4. applicable only with multiplexed address and data buses. table 128. bfc signals in burst mode symbol parameter conditions min max units bfc 1 bfck rising to a1-a25 valid (1) c add = 0 pf t clbfck - 0.2 ns c add derating - 0.028 ns/pf bfc 2 bfck rising to a1-a25 change (1) c add = 0 pf t clbfck - 1.0 ns c add derating - 0.045 ns/pf bfc 3 bfck falling to bfavd active (1) c bfavd = 0 pf t clbfck - 1.1 t clbfck - 0.3 ns c bfavd derating - 0.044 - 0.028 ns/pf bfc 4 bfck falling to bfavd inactive (1) c bfavd = 0 pf t clbfck - 1.8 t clbfck + 0.2 ns c bfavd derating - 0.044 0.044 ns/pf bfc 5 bfavd minimum pulse width (1) c bfavd = 0 pf t cpbfck + 1.0 ns c bfavd derating 0.001 ns/pf bfc 6 bfck rising to bfoe active c bfoe = 0 pf - 0.4 0.1 ns c bfoe derating - 0.044 0.044 ns/pf bfc 7 bfck rising to bfoe inactive c bfoe = 0 pf - 1.1 0.7 ns c bfoe derating - 0.044 0.044 ns/pf bfc 9 d0-d15 in setup before bfck rising edge - 0.1 ns bfc 10 d0-d15 in hold after bfck rising edge 1.0 ns bfc 15 bfck rising to ad0-ad15 valid (1 ) (4) c data = 0 pf t clbfck - 0.2 ns c data derating - 0.028 ns/pf bfc 16 bfck rising to ad0-ad15 not valid (1 ) (4) c data = 0 pf t clbfck - 0.8 ns c data derating - 0.044 ns/pf bfc 21 number of address valid latency cycles (1 ) ((a + 1) x t cpbfck ) (2) ((a + 1) x t cpbfck ) (2) ns bfc 22 number of output enable latency cycles (1) (o x t cpbfck ) (3) (o x t cpbfck ) (3) ns bfc 23 bfck falling to bfbaa active (1) c bfbaa = 0 pf t clbfck - 1.0 t clbfck - 0.1 ns c bfbaa derating - 0.044 - 0.028 ns/pf bfc 24 bfck falling to bfbaa inactive (1) c bfbaa = 0 pf t clbfck - 1.7 t clbfck + 0.1 ns c bfbaa derating - 0.044 0.044 ns/pf bfc 25 bfrdy change hold after bfck rising edge 0.1 ns bfc 26 bfrdy change setup before bfck rising edge 0.3 ns
620 AT91RM9200 1768b?atarm?08/03 figure 274. bfc signals relative to bfck in burst mode note: 1. bfcs is asserted as soon as the bfcom field in bfc_mr is different from 0. bfavd d0 - d15 read bfck if signal controlled address advance d0 - d15 to write if multiplexed bus only bfcs (1) a1 - a25 bfoe bfrdy bfc 1 bfc 3 bfc 4 bfc 5 bfc 6 bfc 7 bfc 15 bfc 16 bfc 21 bfc 22 bfbaa if signal controlled address advance bfc 23 bfc 24 bfc 24 bfc 23 bfck if clock controlled address advance bfc 25 bfc 25 bfc 6 bfc 7 bfc 26 bfc 26 bfc 9 bfc 10 bfc 9 bfc 10 bfc 9 bfc 10 bfc 9 bfc 9 bfc 10 bfc 9 bfc 10 bfc 9 bfc 10 bfc 9 bfc 10 bfc 9 bfc 10 bfc 9 bfc 10 bfc 9 bfc 10
621 AT91RM9200 1768b?atarm?08/03 jtag/ice timings ice interface signals table 129 shows timings relative to operating condition limits defined in the section ?condi- tions and timings computation? on page 603 figure 275. ice interface signals table 129. ice interface timing specifications symbol parameter conditions min max units ice 0 ntrst minimum pulse width 20.00 ns ice 1 ntrst high recovery to tck high 0.86 ns ice 2 ntrst high removal from tck high 0.90 ns ice 3 tck low half-period 8.00 ns ice 4 tck high half-period 8.00 ns ice 5 tck period 20.00 ns ice 6 tdi, tms, setup before tck high -0.13 ns ice 7 tdi, tms, hold after tck high 0.10 ns ice 8 tdo hold time c tdo = 0 pf 4.17 ns c tdo derating 0 ns/pf ice 9 tck low to tdo valid c tdo = 0 pf 6.49 ns c tdo derating 0.028 ns/pf tck ice 3 ice 4 ice 7 ice 6 ice 9 ice 8 tms/tdi tdo ice 0 ice 5 ntrst ice 1 ice 2
622 AT91RM9200 1768b?atarm?08/03 jtag interface signals table 130 shows timings relative to operating condition limits defined in the section ?condi- tions and timings computation? on page 603 table 130. jtag interface timing specifications symbol parameter conditions min max units jtag 0 ntrst minimum pulse width 20.00 ns jtag 1 ntrst high recovery to tck high -0.16 ns jtag 2 ntrst high recovery to tck low -0.16 ns jtag 3 ntrst high removal from tck high -0.07 ns jtag 4 ntrst high removal from tck low -0.07 ns jtag 5 tck low half-period 8.00 ns jtag 6 tck high half-period 8.00 ns jtag 7 tck period 20.00 ns jtag 8 tdi, tms setup before tck high 0.01 ns jtag 9 tdi, tms hold after tck high 3.21 ns jtag 10 tdo hold time c tdo = 0 pf 2.38 ns c tdo derating 0 ns/pf jtag 11 tck low to tdo valid c tdo = 0 pf 4.66 ns c tdo derating 0.028 ns/pf jtag 12 device inputs setup time -1.23 ns jtag 13 device inputs hold time 3.81 ns jtag 14 device outputs hold time c out = 0 pf 7.15 ns c out derating 0 ns/pf jtag 15 tck to device outputs valid c out = 0 pf 7.22 ns c out derating 0.028 ns/pf
623 AT91RM9200 1768b?atarm?08/03 figure 276. jtag interface signals tck jtag 7 jtag 6 jtag 9 jtag 8 tms/tdi tdo ntrst jtag 12 jtag 13 device outputs jtag 5 jtag 4 jtag 3 jtag 0 jtag 1 jtag 2 jtag 11 jtag 10 device inputs
624 AT91RM9200 1768b?atarm?08/03 etm timings timings data table 131 shows timings relative to operating condition limits defined in the section ?condi- tions and timings computation? on page 603. figure 277. etm signals design considerations when designing a pcb, it is important to k eep the differences between trace length of etm signals as small as possible to minimize skew between them. in addition, crosstalk on the trace port must be kept to a minimum as it can cause erroneous trace results. stubs on these traces can cause unpredictable responses, thus it is recommended to avoid stubs on the trace lines. the tclk line should be series-terminated as close as possible to the microcontroller pins. the maximum capacitance presented by the trac e connector, cabling and interfacing logic must be less than 15 pf. table 131. etm timing characteristics symbol parameter conditions min typ max units 1/(t cptclk ) trace clock frequency 1/(2 x t cppck ) 86.54 mhz t cptclk trace clock period 11.56 2 x t cppck ns t chtclk tclk high half-period t cptclk /2 + 0.02 ns t cltclk tclk low half-period t cptclk /2 - 0.02 ns etm 0 data signals out valid before tclk rising edge c = 0 pf t cltclk - 1.06 ns c data derating 0.044 ns/pf etm 1 data signals out valid after tclk rising edge c = 0 pf t chtclk - 0.49 ns c data derating 0.044 ns/pf etm 2 data signals out valid before tclk falling edge c = 0 pf t chtclk - 1.03 ns c data derating 0.044 ns/pf etm 3 data signals out valid after tclk falling edge c = 0 pf t cltclk - 0.51 ns c data derating 0.044 ns/pf t chtclk t cltclk t cptclk tclk tsync tps[2:0] tpk[15:0] etm 0 etm 1 etm 2 etm 3
625 AT91RM9200 1768b?atarm?08/03 AT91RM9200 mechanical characteristics thermal and reliability considerations thermal data in table 132, the device lifetime is estimated using the mil-217 standard in the ?moderately controlled? environmental model (this model is described as corresponding to an installation in a permanent rack with adequate cooling air), depending on the device junction temperature. (for details see the section ?junction temperature? on page 626.) note that the user must be extremely cautious with this mtbf calculation. it should be noted that the mil-217 model is pessimistic with respect to observed values due to the way the data/models are obtained (test under severe conditions). the life test results that have been measured are always better than the predicted ones. table 133 summarizes the thermal resistance data depending on the package. reliability data the number of gates and the device die size are provided table 134 so that the user can cal- culate reliability data for another standard and/or in another environmental model. table 132. mtbf versus junction temperature junction temperature (t j ) (c) estimated lifetime (mtbf) (year) 100 6 125 3 150 2 175 1 table 133. thermal resistance data symbol parameter condition package typ unit ja junction-to-ambient thermal resistance still air pqfp208 33.9 c/w lfbga256 35.6 jc junction-to-case thermal resistance pqfp208 15.7 lfbga256 7.7 table 134. reliability data parameter data unit number of logic gates 4461 k gates number of memory gates 2458 k gates device die size 33.9 mm 2
626 AT91RM9200 1768b?atarm?08/03 junction temperature the average chip-junction temperature, t j , in c can be obtained from the following: 1. 2. where: ja = package thermal resistance, junction-to-ambient (c/w), provided in table 133 on page 625. jc = package thermal resistance, junction-to-case thermal resistance (c/w), provided in table 133 on page 625. heat sink = cooling device thermal resistance (c/w), provided in the device datasheet. p d = device power consumption (w) estimated from data provided in the section ?power consumption? on page 598. t a = ambient temperature (c). from the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling device is necessary or not. if a cooli ng device is to be fitted on the chip, the second equation should be used to compute the resulting average chip-junction temperature t j in c. t j t a p d ja () + = t j t a p ( d ( heatsink jc )) ++ =
627 AT91RM9200 1768b?atarm?08/03 package drawings figure 278. 208-lead pqfp package drawing cc1 table 135. 208-lead pqfp package dimensions (in mm) symbol min nom max symbol min nom max c 0.11 0.23 b1 0.17 0.20 0.23 c1 0.11 0.15 0.19 ddd 0.10 l 0.65 0.88 1.03 tolerances of form and position l1 1.60 ref aaa 0.25 r2 0.13 0.3 ccc 0.1 r1 0.13 bsc s0.4 d 31.20 a4.10 d1 28.00 a1 0.25 0.50 e 31.20 a2 3.20 3.40 3.60 e1 28.00 b 0.17 0.27 e 0.50
628 AT91RM9200 1768b?atarm?08/03 figure 279. 256-ball bga package drawing
629 AT91RM9200 1768b?atarm?08/03 AT91RM9200 ordering information table 136. ordering information ordering code package rom code revision temperature operating range AT91RM9200-qi-002 pqfp 208 002 industrial (-40 c to 85 c) AT91RM9200-ci-002 bga 256
630 AT91RM9200 1768b?atarm?08/03
631 AT91RM9200 1768b?atarm?08/03 document details title AT91RM9200 datasheet literature number 1768 revision history version a publication date: 22-apr-03 version b publication date: 22-aug-03 changes since last issue page 36 new figure 8, arm920t internal functional block diagram. page 56 corrected fields in cp15 register 7 register table. page 62 updated figure 9, AT91RM9200 debug and test block diagram with corrected dtxd and drxd signal names and transfer direction of signals tst0 - tst1 and nrst. page 85 change signal name to npcs0. page 86 changes to figure 15, boot program algorithm flow diagram. page 87 corrected bms state to high during reset. corrected address for internal rom mapping. page 89 in table 21 and text, corrected device names at45dbxxx. page 91 changes to figure 20, serial dataflash download. page 96 updated table 24 with new pins used and table note. page 108 code change in section description of the svcxmodem structure. page 109 code change in table 29: xmodem service, first table cell. page 110 code change in section using the service. page 111 code change in table 30: dataflash service methods, first table cell. page 116 code change in steps 1 and 2 in section using the service. page 233 changed table 58, i/o line description. page 245 in aic source mode register, corrected descriptions of bits prior and srctype. page 255 change number of programmable clocks to four. correct oscillator speed to read 32.768 khz. page 256 updated section i/o lines with new information on clocks. page 257 new pmc block diagram, figure 117.
632 AT91RM9200 1768b?atarm?08/03 page 258 updated processor clock and programmable clock outputs descriptions. updated clock generator description. page 259 new clock generator block diagram, figure 118. section slow clock oscillator startup time updated. page 261 added section main oscillator bypass. page 263 updated section pllb divider by 2. page 264 in section master clock controller, changed references to pllb output to pllb clock. new figure 124: master clock controller. in section processor clock source, specified differences between arm7-based and arm9-based systems. page 265 section programmable clock output controller updated to show change in number of programmable clocks. page 267 in table 60: clock switching timings (w orst case), changed plla output to plla clock and pllb output to pllb clock. page 268 in figure 125: switch master clock from slow clock to plla clock and in figure 126: switch master clock from main clock to slow clock, changed signal names and wave- form labels. page 269 in figure 127: change plla programming, changed signal names and labels. new fig- ure 128: programmable clock output programming. page 270 changed register names in table 61: pmc register mapping: pmc_mor to ckgr_mor, pmc_mcfr to ckgr_mcfr, pmc_pllar to ckgr_pllar and pcm_pllbr to ckgr_pllbr. remove registers pmc_pck4, pmc_pck5, pmc_pck6 and pmc_pck7 (addresses 0x0050 to 0x005c). page 271 in register pmc_scer, deleted bits pck7 to pck4, fields 15 to 12. all bit names updated to include ?enable?. in uhp bit description, deleted reference to 12 mhz clock. page 272 in register pmc_scdr, deleted bits pck7 to pck4, fields 15 to 12. all bit names updated to include ?disable?. in uhp bit description, deleted reference to 12 mhz clock. page 273 in register pmc_scsr, deleted bits pck7 to pck4, fields 15 to 12. all bit names updated to include ?status?. in uhp bit description, corrected to read ?usb host port?. page 276 changed register name to pmc clock generator main oscillator register. moscen bit description changed to include information on main clock signal and crystal connection. oscount bit description changed to remove multiplication factor for slow clock cycles. page 277 changed register name to pmc clock generator main clock frequency register. cor- rected in mainrdy field description reference to mainf. page 278 changed register name to pmc clock generator pll a register. in outa and mula bits, changed references to plla output to pll a clock.
633 AT91RM9200 1768b?atarm?08/03 page 279 changed register name to pmc clock generator pll b register. in outb and mulb bits, changed references to pllb output to pll b clock. changed bit description for usb_96m. page 280 in pmc_mckr, new clock source selections specified for css. mdiv bit condition added. page 281 in pmc_pck0 to pmc_pck3, new clock source selections specified for css. page 282 in pmc_ier and pmc_idr, bits pck7rdy, pck6rdy, pck5rdy and pck4rdy removed. page 283 in pmc_sr, bits pck7rdy, pck6rdy, pck5rdy and pck4rdy removed. page 284 in pmc_imr, bits pck7rdy, pck6rdy, pck5rdy and pck4rdy removed. page 312 added note to figure 135. page 331 in dbgu chip id register, corrected nvptyp field to 000 for rom. page 343 in table 67: pio register mapping, pio_owsr access changed to read-only. page 358 in pio_owsr, access changed to read-only. page 368 changed all references from cpha to ncpha. updated figures 159 and 160 for clarity. page 391 in chdiv and cldiv bit descriptions in register twi_cwgr, corrected equations for calculation of scl high and low periods. in chdiv, cldiv and ckdiv bit descriptions in register twi_cwgr, scl replaced by twck. page 452 updated figure 214, transmit frame format in continuous mode. updated figure 215, receive frame format in continuous mode. page 460 in register ssc_rfmr, new description of bit datlen. page 596 in table 109, dc characteristics, changed conditions for static current. page 598 new consumption figures in table 113 and table 114. page 599 in table 115: 32 khz oscillator characteristics, v ddosc defined in startup time condi- tions. in table 116: main oscillator characteristics, v ddpll defined in startup time conditions. in table 117: phase lock loop characteristics, corrected errors in pump current max/min values. page 601 in table 120: switching characteristics in full speed, min/max values for rise/fall time matching added. page 614 in table 125: sdramc signals, changed min values for sdramc 23 to sdramc 28 .
634 AT91RM9200 1768b?atarm?08/03
i AT91RM9200 1768b?atarm?08/03 table of contents AT91RM9200 overview..................................................................................... 1 features............................................................................................................... 1 description .......................................................................................................... 2 block diagram..................................................................................................... 3 key features ....................................................................................................... 4 arm920t processor ........................................................................................ 4 debug and test................................................................................................ 4 boot program ................................................................................................... 5 embedded software services .......................................................................... 5 reset controller ............................................................................................... 5 memory controller............................................................................................ 5 external bus interface...................................................................................... 6 static memory controller.................................................................................. 6 sdram controller............................................................................................ 6 burst flash controller ...................................................................................... 7 peripheral data controller................................................................................ 7 advanced interrupt controller .......................................................................... 7 power management controller ........................................................................ 8 system timer ................................................................................................... 8 real time clock ............................................................................................... 8 debug unit ....................................................................................................... 8 pio controller .................................................................................................. 9 usb host port.................................................................................................. 9 usb device port .............................................................................................. 9 ethernet mac................................................................................................. 10 serial peripheral interface.............................................................................. 10 two-wire interface.......................................................................................... 10 usart ........................................................................................................... 10 serial synchronous controller ....................................................................... 11 timer counter ................................................................................................ 11 multimedia card interface .............................................................................. 11 AT91RM9200 product properties................................................................. 13 power supplies ................................................................................................. 13 pinout................................................................................................................. 13 208-lead pqfp package pinout .................................................................... 14 mechanical overview of the 208-lead pqfp package .................................. 15 256-ball bga package pinout........................................................................ 16 mechanical overview of the 256-ball bga package...................................... 18 peripheral multiplexing on pio lines ............................................................. 18 pio controller a multiplexing ......................................................................... 19 pio controller b multiplexing ......................................................................... 20 pio controller c multiplexing ......................................................................... 21 pio controller d multiplexing ......................................................................... 22 pin name description....................................................................................... 23
ii AT91RM9200 1768b?atarm?08/03 peripheral identifiers ........................................................................................ 28 system interrupt............................................................................................. 29 external interrupts.......................................................................................... 29 product memory mapping................................................................................ 30 external memory mapping ............................................................................. 30 internal memory mapping .............................................................................. 31 peripheral mapping ........................................................................................ 32 peripheral implementation............................................................................... 34 usart ........................................................................................................... 34 timer counter ................................................................................................ 34 arm920t processor overview..................................................................... 35 overview............................................................................................................ 35 block diagram................................................................................................... 36 arm9tdmi processor ...................................................................................... 37 instruction type.............................................................................................. 37 data types ..................................................................................................... 37 arm9tdmi operating modes ........................................................................ 37 arm9tdmi registers .................................................................................... 38 arm instruction set overview ....................................................................... 40 thumb instruction set overview .................................................................... 41 cp15 coprocessor............................................................................................ 42 cp15 register access ................................................................................... 43 memory management unit (mmu) ................................................................... 44 domain........................................................................................................... 44 mmu faults .................................................................................................... 44 caches, write buffers and physical address ................................................ 45 instruction cache (icache) ............................................................................ 45 data cache (dcache) and write buffer ......................................................... 45 arm920t user interface .................................................................................. 47 cp15 register 0, id code and cache type .................................................. 47 cp15 register 1, control ............................................................................... 49 cp15 register 2, ttb .................................................................................... 51 cp15 register 3, domain access control register ....................................... 52 cp15 register 4, reserved ........................................................................... 53 cp15 register 5, fault status register ......................................................... 53 cp15 register 6, fault address register ...................................................... 54 cp15 register 7, cache operation register ................................................. 55 cp15 register 8, tlb operations register ................................................... 57 cp15 register 9, cache lockdown register ................................................. 58 cp15 register 10, tlb lockdown register................................................... 59 cp15 registers 11, 12, reserved.................................................................. 59 cp15 register 13, fcse pid register .......................................................... 60 cp15 register 14, reserved ......................................................................... 60 cp15 register 15, test configuration register ............................................. 60
iii AT91RM9200 1768b?atarm?08/03 debug and test features (dbg test).......................................................... 61 overview............................................................................................................ 61 block diagram................................................................................................... 62 application examples ...................................................................................... 63 debug environment ....................................................................................... 63 test environment ............................................................................................. 63 debug and test pin description ..................................................................... 64 functional description..................................................................................... 65 test mode pins .............................................................................................. 65 embedded in-circuit emulator ....................................................................... 65 debug unit ..................................................................................................... 65 embedded trace macrocell ........................................................................... 65 ieee 1149.1 jtag boundary scan ............................................................... 69 AT91RM9200 id code register .................................................................... 83 boot program................................................................................................. 85 overview............................................................................................................ 85 flow diagram .................................................................................................... 86 bootloader......................................................................................................... 87 valid image detection .................................................................................... 88 structure of arm vector 6 ............................................................................. 89 bootloader sequence..................................................................................... 90 boot uploader ................................................................................................... 94 external communication channels ................................................................ 94 hardware and software constraints............................................................... 96 embedded software services ...................................................................... 97 overview............................................................................................................ 97 service definition ............................................................................................. 97 service structure............................................................................................ 97 using a service .............................................................................................. 98 embedded software services ....................................................................... 101 definition ...................................................................................................... 101 rom entry service ...................................................................................... 101 tempo service ............................................................................................. 102 xmodem service.......................................................................................... 105 dataflash service........................................................................................ 111 crc service ................................................................................................ 117 sine service ................................................................................................. 118 AT91RM9200 reset controller ................................................................... 119 overview.......................................................................................................... 119 reset conditions .......................................................................................... 119 reset management...................................................................................... 120
iv AT91RM9200 1768b?atarm?08/03 required features for the reset controller ................................................. 121 memory controller(mc)............................................................................... 123 overview.......................................................................................................... 123 block diagram................................................................................................. 124 functional description................................................................................... 125 bus arbiter ................................................................................................... 125 address decoder ......................................................................................... 125 remap command ........................................................................................ 127 abort status ................................................................................................. 128 misalignment detector ................................................................................. 128 memory controller interrupt ......................................................................... 129 user interface.................................................................................................. 129 mc remap control register ........................................................................ 130 mc abort status register ............................................................................ 131 mc abort address status register .............................................................. 133 mc master priority register ......................................................................... 134 external bus interface (ebi) ....................................................................... 135 overview.......................................................................................................... 135 block diagram................................................................................................. 136 i/o lines description...................................................................................... 137 application example ...................................................................................... 139 hardware interface....................................................................................... 139 connection examples .................................................................................. 141 product dependencies................................................................................... 142 i/o lines....................................................................................................... 142 functional description................................................................................... 142 bus multiplexing ........................................................................................... 142 pull-up control ............................................................................................. 142 static memory controller.............................................................................. 142 sdram controller........................................................................................ 142 burst flash controller .................................................................................. 142 compactflash support ................................................................................ 143 smartmedia and nand flash support ........................................................ 146 external bus interface (ebi) user interface ................................................. 148 ebi chip select assignment register .......................................................... 149 ebi configuration register........................................................................... 150 static memory controller (smc) ................................................................ 151 overview.......................................................................................................... 151 block diagram................................................................................................. 152 application example ...................................................................................... 153 hardware interface....................................................................................... 153 product dependencies................................................................................... 153
v AT91RM9200 1768b?atarm?08/03 i/o lines....................................................................................................... 153 functional description................................................................................... 154 external memory interface ........................................................................... 154 write access ................................................................................................ 156 read access ................................................................................................ 159 wait state management............................................................................... 161 setup and hold cycles................................................................................. 164 lcd interface mode ..................................................................................... 168 memory access waveforms ........................................................................ 169 static memory controller (smc) user interface........................................... 185 smc chip select registers.......................................................................... 186 sdram controller (sdramc) .................................................................... 189 overview.......................................................................................................... 189 block diagram................................................................................................. 190 i/o lines description...................................................................................... 190 application example ...................................................................................... 191 hardware interface....................................................................................... 191 software interface ........................................................................................ 192 product dependencies................................................................................... 194 sdram devices initialization....................................................................... 194 i/o lines....................................................................................................... 195 interrupt........................................................................................................ 195 functional description................................................................................... 195 sdram controller write cycle .................................................................... 195 sdram controller read cycle .................................................................... 196 border management .................................................................................... 197 sdram controller refresh cycles .............................................................. 198 power management ..................................................................................... 199 sdram controller (sdramc) user interface .............................................. 201 sdramc mode register ............................................................................. 202 sdramc refresh timer register ............................................................... 203 sdramc configuration register ................................................................. 204 sdramc self-refresh register.................................................................... 206 sdramc low-power register..................................................................... 206 sdramc interrupt enable register............................................................. 207 sdramc interrupt disable register ............................................................ 207 sdramc interrupt mask register ............................................................... 208 sdramc interrupt status register.............................................................. 208 burst flash controller (bfc)...................................................................... 209 overview.......................................................................................................... 209 block diagram................................................................................................. 210 i/o lines description ..................................................................................... 210 application example ...................................................................................... 211
vi AT91RM9200 1768b?atarm?08/03 burst flash interface .................................................................................... 211 product dependencies................................................................................... 212 supported burst flash devices.................................................................... 212 i/o lines....................................................................................................... 212 functional description................................................................................... 212 burst flash controller reset state............................................................... 212 burst flash controller clock selection......................................................... 212 burst flash controller asynchronous mode................................................. 213 burst flash controller synchronous mode .................................................. 215 burst flash controller (bfc) user interface ................................................ 221 burst flash controller mode register .......................................................... 221 peripheral data controller (pdc) ............................................................... 223 overview.......................................................................................................... 223 block diagram................................................................................................. 223 functional description................................................................................... 224 configuration................................................................................................ 224 memory pointers .......................................................................................... 224 transfer counters ........................................................................................ 224 data transfers ............................................................................................. 225 priority of pdc transfer requests ............................................................... 225 peripheral data controller (pdc) user interface ........................................ 226 pdc receive pointer register ..................................................................... 226 pdc receive counter register ................................................................... 227 pdc transmit pointer register .................................................................... 227 pdc transmit counter register .................................................................. 227 pdc receive next pointer register ............................................................ 228 pdc receive next counter register ........................................................... 228 pdc transmit next pointer register ........................................................... 228 pdc transmit next counter register .......................................................... 229 pdc transfer control register .................................................................... 229 pdc transfer status register...................................................................... 230 advanced interrupt controller (aic) .......................................................... 231 overview.......................................................................................................... 231 block diagram................................................................................................. 232 application block diagram ............................................................................ 232 aic detailed block diagram .......................................................................... 232 i/o line description........................................................................................ 233 product dependencies................................................................................... 233 i/o lines....................................................................................................... 233 power management ..................................................................................... 233 interrupt sources.......................................................................................... 233 functional description................................................................................... 234 interrupt source control ............................................................................... 234
vii AT91RM9200 1768b?atarm?08/03 interrupt latencies ....................................................................................... 236 normal interrupt ........................................................................................... 237 fast interrupt................................................................................................ 239 protect mode................................................................................................ 242 spurious interrupt......................................................................................... 243 general interrupt mask ................................................................................ 243 advanced interrupt controller (aic) user interface .................................... 244 aic source mode register .......................................................................... 245 aic source vector register ......................................................................... 245 aic interrupt vector register ....................................................................... 246 aic fiq vector register ...................................................................................... 246 aic interrupt status register ....................................................................... 247 aic interrupt pending register .................................................................... 247 aic interrupt mask register ......................................................................... 248 aic core interrupt status register .............................................................. 248 aic interrupt enable command register..................................................... 249 aic interrupt disable command register .................................................... 249 aic interrupt clear command register ....................................................... 250 aic interrupt set command register .......................................................... 250 aic end of interrupt command register ..................................................... 251 aic spurious interrupt vector register ........................................................ 251 aic debug control register......................................................................... 252 aic fast forcing enable register................................................................ 253 aic fast forcing disable register ............................................................... 253 aic fast forcing status register................................................................. 254 power management controller (pmc) ....................................................... 255 overview.......................................................................................................... 255 product dependencies................................................................................... 256 i/o lines....................................................................................................... 256 interrupt........................................................................................................ 256 oscillator and pll characteristics ............................................................... 256 peripheral clocks ......................................................................................... 256 usb clocks .................................................................................................. 256 block diagram................................................................................................. 257 functional description................................................................................... 258 operating modes definition.......................................................................... 258 clock definitions .......................................................................................... 258 clock generator ........................................................................................... 258 slow clock oscillator ................................................................................... 259 main oscillator ............................................................................................. 260 divider and pll blocks ................................................................................ 262 clock controllers .......................................................................................... 263 clock switching details ................................................................................. 267 master clock switching timings .................................................................. 267 clock switching waveforms......................................................................... 268
viii AT91RM9200 1768b?atarm?08/03 power management controller (pmc) user interface ................................ 270 pmc system clock enable register............................................................ 271 pmc system clock disable register ........................................................... 272 pmc system clock status register............................................................. 273 pmc peripheral clock enable register ....................................................... 274 pmc peripheral clock disable register ...................................................... 274 pmc peripheral clock status register ........................................................ 275 pmc clock generator main oscillator register ........................................... 276 pmc clock generator main clock frequency register ............................... 277 pmc clock generator pll a register ......................................................... 278 pmc clock generator pll b register ......................................................... 279 pmc master clock register ......................................................................... 280 pmc programmable clock register 0 to 3 .................................................. 281 pmc interrupt enable register .................................................................... 282 pmc interrupt disable register ................................................................... 282 pmc status register.................................................................................... 283 pmc interrupt mask register ....................................................................... 284 system timer (st) ....................................................................................... 285 overview.......................................................................................................... 285 block diagram................................................................................................. 285 application block diagram ............................................................................ 285 product dependencies................................................................................... 286 power management ..................................................................................... 286 interrupt sources.......................................................................................... 286 watchdog overflow ...................................................................................... 286 functional description................................................................................... 286 system timer clock ....................................................................................... 286 period interval timer (pit) ........................................................................... 286 watchdog timer (wdt) ............................................................................... 287 real-time timer (rtt) ................................................................................. 287 system timer (st) user interface ................................................................. 289 st control register...................................................................................... 289 st period interval mode register ................................................................ 290 st watchdog mode register ....................................................................... 290 st real-time mode register....................................................................... 291 st status register ....................................................................................... 291 st interrupt enable register........................................................................ 292 st interrupt disable register ....................................................................... 292 st interrupt mask register .......................................................................... 293 st real-time alarm register ....................................................................... 293 st current real-time register.................................................................... 294 real time controller (rtc)......................................................................... 295 overview.......................................................................................................... 295
ix AT91RM9200 1768b?atarm?08/03 block diagram................................................................................................. 295 product dependencies................................................................................... 295 power management ..................................................................................... 295 interrupt........................................................................................................ 295 functional description................................................................................... 296 reference clock........................................................................................... 296 timing .......................................................................................................... 296 alarm............................................................................................................ 296 error checking ............................................................................................. 296 updating time/calendar .............................................................................. 297 real time controller (rtc) user interface................................................... 298 rtc control register ................................................................................... 299 rtc mode register ..................................................................................... 300 rtc time register ...................................................................................... 301 rtc calendar register................................................................................ 302 rtc time alarm register ............................................................................ 303 rtc calendar alarm register ..................................................................... 304 rtc status register .................................................................................... 305 rtc status clear command register ......................................................... 306 rtc interrupt enable register ..................................................................... 307 rtc interrupt disable register .................................................................... 308 rtc interrupt mask register ....................................................................... 309 rtc valid entry register ............................................................................. 310 debug unit (dbgu) ..................................................................................... 311 overview.......................................................................................................... 311 block diagram................................................................................................. 312 product dependencies................................................................................... 313 i/o lines....................................................................................................... 313 power management ..................................................................................... 313 interrupt source ........................................................................................... 313 uart operations............................................................................................ 313 baud rate generator ................................................................................... 313 receiver ....................................................................................................... 314 transmitter ................................................................................................... 316 peripheral data controller............................................................................ 317 test modes .................................................................................................. 317 debug communication channel support..................................................... 319 chip identifier ............................................................................................... 319 ice access prevention ................................................................................ 319 debug unit user interface ............................................................................. 320 debug unit control register ........................................................................ 321 debug unit mode register ........................................................................... 322 debug unit interrupt enable register .......................................................... 323 debug unit interrupt disable register ......................................................... 324 debug unit interrupt mask register ............................................................. 325
x AT91RM9200 1768b?atarm?08/03 debug unit status register.......................................................................... 326 debug unit receiver holding register ........................................................ 328 debug unit baud rate generator register.................................................. 329 debug unit chip id register ........................................................................ 330 debug unit chip id extension register ....................................................... 332 debug unit force ntrst register.............................................................. 332 parallel input/output controller (pio) ....................................................... 333 overview.......................................................................................................... 333 block diagram................................................................................................. 334 product dependencies................................................................................... 335 pin multiplexing ............................................................................................ 335 external interrupt lines ................................................................................ 335 power management ..................................................................................... 335 interrupt generation ..................................................................................... 335 functional description................................................................................... 336 pull-up resistor control ............................................................................... 337 i/o line or peripheral function selection .................................................... 337 peripheral a or b selection .......................................................................... 337 output control.............................................................................................. 337 synchronous data output............................................................................ 338 multi drive control (open drain) .................................................................. 338 output line timings ..................................................................................... 338 inputs ........................................................................................................... 339 input glitch filtering ..................................................................................... 339 input change interrupt ................................................................................. 340 i/o lines programming example .................................................................. 341 parallel input/output controller (pio) user interface.................................. 342 pio enable register .................................................................................... 344 pio disable register.................................................................................... 344 pio status register ..................................................................................... 345 pio output enable register......................................................................... 345 pio output disable register ........................................................................ 346 pio output status register.......................................................................... 346 pio input filter enable register .................................................................. 347 pio input filter disable register.................................................................. 347 pio input filter status register ................................................................... 348 pio set output data register ...................................................................... 348 pio clear output data register................................................................... 349 pio output data status register ................................................................. 349 pio pin data status register....................................................................... 350 pio interrupt enable register ...................................................................... 350 pio interrupt disable register ..................................................................... 351 pio interrupt mask register......................................................................... 351 pio interrupt status register ....................................................................... 352 pio multi-driver enable register.................................................................. 352
xi AT91RM9200 1768b?atarm?08/03 pio multi-driver disable register ................................................................. 353 pio multi-driver status register................................................................... 353 pio pull up disable register ....................................................................... 354 pio pull up enable register ........................................................................ 354 pio pad pull up status register ................................................................. 355 pio peripheral a select register ................................................................. 355 pio peripheral b select register ................................................................. 356 pio peripheral ab status register .............................................................. 356 pio output write enable register ............................................................... 357 pio output write disable register .............................................................. 357 pio output write status register ................................................................ 358 serial peripheral interface (spi) ................................................................. 359 overview.......................................................................................................... 359 block diagram................................................................................................. 360 application block diagram ............................................................................ 361 product dependencies................................................................................... 362 i/o lines....................................................................................................... 362 power management ..................................................................................... 362 interrupt........................................................................................................ 362 functional description................................................................................... 362 master mode operations.............................................................................. 362 spi slave mode ........................................................................................... 367 data transfer ............................................................................................... 368 serial peripheral interface (spi) user interface ........................................... 370 spi control register .................................................................................... 371 spi mode register ....................................................................................... 372 spi receive data register .......................................................................... 374 spi transmit data register ......................................................................... 374 spi status register ...................................................................................... 375 spi interrupt enable register ...................................................................... 376 spi interrupt disable register...................................................................... 377 spi interrupt mask register ......................................................................... 378 spi chip select register.............................................................................. 379 two-wire interface (twi) ............................................................................. 381 overview.......................................................................................................... 381 block diagram................................................................................................. 381 application block diagram ............................................................................ 381 product dependencies................................................................................... 382 i/o lines....................................................................................................... 382 power management ..................................................................................... 382 interrupt........................................................................................................ 382 functional description................................................................................... 382 transfer format ........................................................................................... 382
xii AT91RM9200 1768b?atarm?08/03 modes of operation...................................................................................... 383 transmitting data......................................................................................... 383 read/write flowcharts................................................................................. 385 two-wire interface (twi) user interface ...................................................... 388 twi control register.................................................................................... 389 twi master mode register .......................................................................... 390 twi internal address register ..................................................................... 391 twi clock waveform generator register.................................................... 391 twi status register ..................................................................................... 392 twi interrupt enable register...................................................................... 393 twi interrupt disable register ..................................................................... 394 twi interrupt mask register ........................................................................ 395 twi receive holding register ..................................................................... 396 twi transmit holding register .................................................................... 396 universal synchronous asynchronous receiver transceiver (usart) 397 overview.......................................................................................................... 397 block diagram................................................................................................. 398 application block diagram ............................................................................ 399 i/o lines description ..................................................................................... 399 product dependencies................................................................................... 399 i/o lines....................................................................................................... 399 power management ..................................................................................... 400 interrupt........................................................................................................ 400 functional description................................................................................... 400 baud rate generator ................................................................................... 400 receiver and transmitter control ................................................................ 404 synchronous and asynchronous modes...................................................... 405 iso7816 mode ............................................................................................. 415 irda mode .................................................................................................... 418 rs485 mode ................................................................................................ 421 modem mode ............................................................................................... 422 test modes .................................................................................................. 422 usart user interface ................................................................................... 424 usart control register .............................................................................. 425 usart mode register................................................................................. 427 usart interrupt enable register ................................................................ 430 usart interrupt disable register ............................................................... 431 usart interrupt mask register................................................................... 432 usart channel status register ................................................................. 433 usart receive holding register ............................................................... 435 usart transmit holding register .............................................................. 435 usart baud rate generator register ....................................................... 436 usart receiver time-out register ............................................................ 437 usart transmitter timeguard register ..................................................... 437 usart fi di ratio register ...................................................................... 438
xiii AT91RM9200 1768b?atarm?08/03 usart number of errors register .............................................................. 439 usart irda filter register ..................................................................... 440 serial synchronous controller (ssc)........................................................ 441 overview.......................................................................................................... 441 block diagram................................................................................................. 442 application block diagram ............................................................................ 442 pin name list .................................................................................................. 443 product dependencies................................................................................... 443 i/o lines....................................................................................................... 443 power management ..................................................................................... 443 interrupt........................................................................................................ 443 functional description................................................................................... 444 clock management ...................................................................................... 445 transmitter operations ................................................................................ 447 receiver operations .................................................................................... 448 start.............................................................................................................. 448 frame sync .................................................................................................. 450 data format ................................................................................................. 450 loop mode ................................................................................................... 452 interrupt........................................................................................................ 452 ssc application examples ............................................................................ 453 serial synchronous controller (ssc) user interface .................................. 455 ssc control register ................................................................................... 456 ssc clock mode register ........................................................................... 457 ssc receive clock mode register ............................................................. 458 ssc receive frame mode register ............................................................ 460 ssc transmit clock mode register ............................................................ 462 ssc transmit frame mode register ........................................................... 464 ssc receive holding register .................................................................... 466 ssc transmit holding register ................................................................... 466 ssc receive synchronization holding register.......................................... 467 ssc transmit synchronization holding register......................................... 467 ssc status register .................................................................................... 468 ssc interrupt enable register ..................................................................... 470 ssc interrupt disable register .................................................................... 471 ssc interrupt mask register ....................................................................... 472 timer counter (tc)...................................................................................... 473 overview.......................................................................................................... 473 block diagram................................................................................................. 474 pin name list .................................................................................................. 475 product dependencies................................................................................... 475 i/o lines....................................................................................................... 475 power management ..................................................................................... 475
xiv AT91RM9200 1768b?atarm?08/03 interrupt........................................................................................................ 475 functional description................................................................................... 475 tc description ............................................................................................. 475 capture operating mode.............................................................................. 478 waveform operating mode ............................................................................ 480 timer counter (tc) user interface ................................................................ 487 tc block control register............................................................................ 488 tc block mode register .............................................................................. 488 tc channel control register ....................................................................... 489 tc channel mode register: capture mode................................................. 490 tc channel mode register: waveform mode ............................................. 492 tc counter value register .......................................................................... 495 tc register a............................................................................................... 495 tc register b............................................................................................... 495 tc register c .............................................................................................. 496 tc status register....................................................................................... 496 tc interrupt enable register ....................................................................... 498 tc interrupt disable register....................................................................... 499 tc interrupt mask register .......................................................................... 500 multimedia card interface (mci)................................................................. 501 overview.......................................................................................................... 501 block diagram................................................................................................. 502 application block diagram ............................................................................ 503 product dependencies................................................................................... 504 i/o lines....................................................................................................... 504 power management ..................................................................................... 504 interrupt........................................................................................................ 504 bus topology.................................................................................................. 504 multimedia card operations .......................................................................... 506 command-response operation.................................................................... 507 data transfer operation .............................................................................. 508 read operation............................................................................................ 509 write operation ............................................................................................ 510 sd card operations........................................................................................ 511 multimedia card (mci) user interface ........................................................... 512 mci control register.................................................................................... 513 mci mode register ...................................................................................... 514 mci data timeout register.......................................................................... 515 mci sd card register ................................................................................. 516 mci argument register................................................................................ 516 mci command register............................................................................... 517 mci sd response register ......................................................................... 518 mci sd receive data register.................................................................... 519 mci sd transmit data register................................................................... 519 mci status register ..................................................................................... 520
xv AT91RM9200 1768b?atarm?08/03 mci interrupt enable register...................................................................... 522 mci interrupt disable register ..................................................................... 523 mci interrupt mask register ........................................................................ 524 usb device port (udp) ............................................................................... 525 overview.......................................................................................................... 525 block diagram................................................................................................. 526 product dependencies................................................................................... 527 i/o lines....................................................................................................... 527 power management ..................................................................................... 527 interrupt........................................................................................................ 527 typical connection......................................................................................... 528 functional description................................................................................... 529 usb v2.0 full-speed introduction................................................................ 529 handling transactions with usb v2.0 device peripheral ............................ 531 controlling device states ............................................................................. 542 usb device port (udp) user interface ......................................................... 544 usb frame number register ...................................................................... 545 usb global state register........................................................................... 546 usb function address register .................................................................. 547 usb interrupt enable register ..................................................................... 548 usb interrupt disable register .................................................................... 549 usb interrupt mask register ....................................................................... 550 usb interrupt status register ...................................................................... 551 usb interrupt clear register ....................................................................... 554 usb reset endpoint register ...................................................................... 555 usb endpoint control and status register ................................................. 556 usb fifo data register.............................................................................. 560 usb device host port (uhp) ...................................................................... 561 overview.......................................................................................................... 561 block diagram................................................................................................. 561 product dependencies................................................................................... 562 i/o lines....................................................................................................... 562 power management ..................................................................................... 562 interrupt........................................................................................................ 562 functional description................................................................................... 562 host controller interface .............................................................................. 562 host controller driver................................................................................... 563 typical connection......................................................................................... 564 ethernet mac (emac)................................................................................. 565 overview.......................................................................................................... 565 block diagram................................................................................................. 566 application block diagram ............................................................................ 566
xvi AT91RM9200 1768b?atarm?08/03 product dependencies................................................................................... 567 i/o lines....................................................................................................... 567 power management ..................................................................................... 567 interrupt........................................................................................................ 567 functional description................................................................................... 568 media independent interface ....................................................................... 569 transmit/receive operation ........................................................................ 570 frame format extensions ............................................................................ 571 dma operations........................................................................................... 572 address checking ........................................................................................ 574 ethernet mac (emac) user interface .......................................................... 575 emac control register................................................................................ 577 emac configuration register ...................................................................... 578 emac status register ................................................................................. 580 emac transmit address register ............................................................... 581 emac transmit control register ................................................................. 582 emac transmit status register .................................................................. 583 emac receive buffer queue pointer register............................................ 584 emac receive status register ................................................................... 585 emac interrupt status register................................................................... 586 emac interrupt enable register .................................................................. 587 emac interrupt disable register ................................................................. 588 emac interrupt mask register .................................................................... 589 emac phy maintenance register .............................................................. 590 emac hash address high register ............................................................ 591 emac hash address low register ............................................................. 591 emac specific address (1, 2, 3 and 4) high register ................................. 592 emac specific address (1, 2, 3 and 4) low register.................................. 592 emac statistics register block registers ................................................... 593 AT91RM9200 electrical characteristics .................................................... 595 absolute maximum ratings........................................................................... 595 dc characteristics.......................................................................................... 596 clocks characteristics ................................................................................... 597 processor clock characteristics ................................................................. 597 master clock characteristics ....................................................................... 597 xin clock characteristics (1) ....................................................................... 597 power consumption....................................................................................... 598 crystal oscillators characteristics ............................................................... 599 32 khz oscillator characteristics ................................................................. 599 main oscillator characteristics..................................................................... 599 pll characteristics ........................................................................................ 599 transceiver characteristics........................................................................... 600 electrical characteristics .............................................................................. 600 switching characteristics ............................................................................. 601
xvii AT91RM9200 1768b?atarm?08/03 AT91RM9200 ac characteristics ............................................................... 603 applicable conditions and derating data .................................................... 603 conditions and timings computation .......................................................... 603 temperature derating factor ....................................................................... 604 vddcore voltage derating factor ............................................................ 604 vddiom voltage derating factor ................................................................ 605 ebi timings ..................................................................................................... 606 smc signals relative to mck ..................................................................... 606 sdramc signals relative to sdck ............................................................ 613 bfc signals relative to bfck..................................................................... 616 jtag/ice timings .......................................................................................... 621 ice interface signals ................................................................................... 621 jtag interface signals ................................................................................ 622 etm timings ................................................................................................... 624 timings data ................................................................................................ 624 design considerations ................................................................................. 624 AT91RM9200 mechanical characteristics................................................. 625 thermal and reliability considerations ....................................................... 625 thermal data ............................................................................................... 625 reliability data ............................................................................................. 625 junction temperature .................................................................................. 626 package drawings .......................................................................................... 627 AT91RM9200 ordering information ........................................................... 629 document details ........................................................................................ 631 revision history ........................................................................................... 631
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